digital testing: built-in self-test

04/21/23Based on text by S. Mourad

"Priciples of Electronic Systems"

Digital Testing: Built-in Self-test

Outline

BIST and embedded testing Why BIST Primitive polynomials LFSR Response compression BILBO

Define Built-In Self-Test

Implement the function of automatic test equipment (ATE) on circuit under test (CUT).

Hardware added to CUT:• Pattern generation (PG)

• Response analysis (RA)

• Test controller

StoredTest

Patterns

Storedresponses

PinElectronics

Comparatorhardware

Test control HW/SW

ATE

PG

RA

Go/No-go signature

Tes

t co

ntr

ol

log

icCK

BISTEnable

Built-in self-test

Disadvantage of LSSD & other scan techniques:

1. Test generation necessary for combinational part2. Long test time since test have to be shifted

in & out3. Only stuck-at faults are tested - not good for VLSI

Built-in self test

Test generation is NP complete. This prompted a search for built-in structures

* Built-in self test BIST is an alternative to automatic test vector generation

* Test generation & verification done by circuits built into the chip

* Pseudo-random test vector generation is accomplished by using shift registers

Built-in self-test in VLSI

Test patterns generated on chipresponses to test evaluated on chipexternal operations only to initialize test & clock go no go resultsadditional pins & silicon area minimized

Built-in self test types

operation (concurrent or not)

test design (exhaustive or not)

test vector generation (deterministic or pseudorandom)

data compression (full or compresses test vectors)

A general built-in self test approach

Built-in self test

* Deterministic testing identifies test vectors to detect specific faults* Pseudorandom testing detects # of faults by any

test vector * Fault coverage increases rapidly at the beginning

and slows down towards the end* The response data is compressed using a signature

analysis * Linear feedback shift registers (LFSR) used to

generate test vectors and compress responses

Pseudorandom Integers

0

5

1

3

7

6 2

4

Start

+3

Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2 . . .

0

5

1

3

7

6 2

4

Start

+2

Sequence: 2, 4, 6, 0, 2 . . .

Xk = Xk-1 + 3 (modulo 8) Xk = Xk-1 + 2 (modulo 8)

Maximum length sequence: 3 and 8 are relative primes.

Pseudo-Random Pattern Generation

Standard Linear Feedback Shift Register (LFSR) Produces patterns

algorithmically – repeatable

Has most of desirable random # properties

May not cover all 2n input combinations

Long sequences needed for good fault coverage

either hi = 0, i.e., XOR is deleted or hi = Xi

Initial state (seed): X0, X1, . . . , Xn-1

must not be 0, 0, . . . , 0

Pseudo-Random Pattern Generator

Y1 Y2 Y3

Q

QD

Q

QD

Q

QD

Y1 Y2 Y3

Clk

Y0

Q

QD

Q

QD

Q

QDClk

Y0

(c)

(b)

Q

QD

Q

QD

Q

QD

Y1 Y2 Y3

Clk

Y0

(a)

Various LFSR configurations

Pseudo-random Patterns

(a) (b) (c)Clk Y0 Y1Y2Y3 ClkY0 Y1Y2Y3 ClkY0 Y1Y2Y3

1 001 1 001 1 0011 1 100 1 0 100 1 1 1002 1 110 2 0 010 2 0 1103 0 111 3 1 001 3 0 0114 1 011 4 1 0015 0 1016 0 0107 1 001

Initial state

Repeated states

Q

QD

Q

QD

Q

QD

Y1 Y

2 Y

3

Clk

Y0

(c)Q

QD

Q

QD

Q

QD

Y1 Y2 Y3

Clk

Y0

(a)

Modified LFSR

Y 1 Y 2 Y 3

Q

QD

Q

QD

Q

QD

Clk

Zero

Y 0

Produces pseudorandom sequence of length 8

Clk Y0 Y1Y2Y3 Y1’Y2’

0 001 1

1 1 000 12 1 100 03 1 110 04 0 111 05 1 011 06 0 101 07 0 010 08 0 001 1

Forcing all possible states in LFSR

Initial state

Standard LFSR

XOR Gate Y NY 1

D FF D FF D FF

C1 C2

Y 2 Y N-1

CN-1 CN

+

+ + +

XOR operations performed outside of the shift register

Modular LFSR

XOR Gate Y NY 1 Y 2 Y N-1

D FF D FF D FF

CNC1 C2 CN-1

++ + +

XOR operations performed inside the shift register

Linear feedback shift registers

Two basic configurations :- internal XOR (IE)- external XOR (EE)

Feedback connections based on coefficients ofa characteristic polynomial :P(X) = C0 + C1X + C2X2 +…+ CnXn

An LFSR with n-flip flops can assume (2n-1) states with depend upon :initial state, input, and feedback

Linear feedback shift registers

1

INTERNAL CONNECTIONS (MODULAR)

EXTERNAL CONNECTIONS (STANDARD)

P(X) = 1+ X 3 + X 4

X X2 X3 X4

X4 X3 X2 X 1

Characteristic Polynomial

LFSR Equivalence

Q

QD

Q

QD

Q

QD

Y 1 Y 2 Y 3

Clk

Y0

(a)

P(X)=1+X+X3

Clk Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3

1 1 0 0 1 1 0 0 1

2 1 1 0 0 1 1 0 1

3 1 1 1 0 0 1 1 1

4 0 1 1 1 1 1 1 0

5 1 0 1 1 0 0 1 1

6 0 1 0 1 0 1 0 0

7 0 0 1 0 1 0 1 0

Q

QD

Q

QD

Q

QD

Clk

Y1 Y2 Y3

Y0

Test generation in BIST

LFSR generally works without input - so only theinitial state & interconnections decide the next state

A generator which generates exactly (2n-1) differentstates is called a maximal-length generator

All polynomials are either primitive (irreducible) or nonprimitive


A primitive polynomial generates a max length sequence of test vectors. The number of primitivepolynomials of order n grows rapidly with n

p - any prime number which divides (2n-1)

( ) ( )nn p

n

2 1

11

Modulo 2 Operations

a b a b a+b a+b a-b a - b

sum carry difference borrow

0 0 0 0 0 0 00 1 1 1 0 1 11 0 1 1 0 1 01 1 0 0 1 0 0

Define time translation operation as X k = X (t-k)

Math Foundation of LFSR

Yj can be represented as: Yj(t) = Yj-1(t - 1) for j 0

We can express Yj in terms of Y0 as: Yj (t) =Y0(t - j)

Denote the translation operator as X k, where k represents

the time translation units, then Yj (t) =Y0(t)X j

On the other hand in LFSR

Where the summation is equivalent to an XOR operation.

Then we get

N

jjj tYCtY

10 )()(

NjforXtYCtY jN

jj

1)()(1

00

Math of LFSR Generators

From linearity we have

and

We can then write this expression as Y0 (t) PN (X) = 0

For non-trivial solutions, Y0(t) 0, then we must have

PN (X) = 0.

Where,

PN (X) is called the characteristic polynomial of the LFSR.

N

j

jj XCtYtY

100 )()(

01)(1

0

N

j

jj XCtY

1)(1

N

j

jjN XCXP

Primitive Polynomials

Examples of primitive polynomials with minimum number of terms

N Polynomials1,2,3,4,6,7,15,22 1 + X + Xn

3,5,11, 21, 29 1 + X2 + Xn

10,17,20,25,28,31 1 + X3 + Xn

9 1 + X4 + Xn

23 1 + X5 + Xn

18 1 + X7 + Xn

8 1 + X2 + X3 + X4 + Xn

12 1 + X + X3 + X4 + Xn

13 1 + X + X4 + X6 + Xn

14, 16 1 + X + X3 + X4 + Xn


For instance for n=8 a minimum polynomial is

Example :Let us follow test generation using a primitive polynomial

x x3 1

84321)( XXXXXP

Reciprocal Polynomials

The reciprocal polynomial of P(X) is defined by:

so PR(X) = XN + Cj XN-j for 1 j N

Thus every coefficient Cj in P(X) is replaced by CN-j in PR(X)

For example, the reciprocal of polynomial P(X) = 1 + X + X3

is PR(X) = 1 + X2 + X3

N

j

jj

NN

NR XCXXPXXP1

1)/1(

Operations on PolynomialsPolynomial multiplicationx4 + x3 + + 1. x + 1 . x4 + x3 + + 1 x5 + x4+ + x . x5 + + x3 + x + 1 since x4 + x4 = 0.

Division is of particular interest when LFSRs are used for response compaction.

x2 + x + 1 .x2 + 1 ) x4 + x3 + + 1

x4 + + x2 . x3 + x2 + + 1 x3 + + x .

x2 + x + 1 x2 + + 1

x

the reminder R(x)=x

Operations on Polynomials

Reminder of the division of the input sequence polynomial by the LFSR polynomial gives the signature for the compacted response

Q(X) X4 + X3 + 1 1 1 0 0 1 X3 + X2 + 1 |X7 + X5 + X4 + +1 1 1 0 1 | 1 0 1 1 0 0 0 1

X7 + X6 + X4 1 1 0 1 X6 + X5 +1 1 1 0 0 0 0 1

X6 + X5 + +X3 1 1 0 1 X3 + +1 1 0 0 1 X3 + X2 + 1 1 1 0 1

R (X) X2 0 1 0 0

Polynomial for the input data signature

Properties of Polynomials

An irreducible polynomial is that polynomial which cannot be factored and it is divisible by only itself and 1. An irreducible polynomial of degree n is characterized by :

An odd number of terms including the 1 term Divisibility into 1 + xk, where k = 2n - 1.

Any polynomial with all even exponents can be factored and hence is reducibleAn irreducible polynomial is primitive if the smallest positive integer k that allows the polynomial to divide evenly into 1 + xk occurs for k = 2n - 1, where n is the degree of the polynomial.

Properties of Polynomials

All polynomials of degree 3 are:x3 + 1= 0x3 + x2 + 1 = 0 Primitivex3 + x + 1 = 0 Primitivex3 + x2 + x + 1= 0

But, x3 + 1= (x + 1)( x2 + x + 1)x3 + x2 + x + 1 = (x + 1)( x2 + 1)

There are several primitive polynomial of degree N. We are interested in those with fewer terms since they need less XOR gates in the LFSR. Among primitive polynomial of degree 16 are

x16 + x5 + x3 + x2 + 1 and x16 + x4 + x3 + x + 1.

Check for Primitive Polynomial

Consider a 3-rd order primitive polynomial

x3 + x + 1 = 0 If this polynomial is primitive it must divide evenly into 1 + x 7 (7 = 2 3 – 1) where 3 is the degree of the polynomial.

We can check that1 + x 7= (x 3 + x + 1)(x 4 + x 2 + x + 1)

Test data compression

To verify response of a tested circuit use test data compression

Ones count compression ex 10011010 => 0(x)=4

Transition count compression ex 10011010 => c(x) =5

Parity check compression ex 10011010 => p(x) =0

Syndrome testing (normalized # of 1’s ) ex 10011010+> s(x) =4/8

Compression using Walsh spectraCyclic code compression (LFSR)

Parity Compression

Li

iirP

1

TestPatterns CUT

r i

Q

QSET

CLR

D+P i -1

Computes parity

Ones Count

CUTResponsesTest

PatternsCOUNTER

If we have a test of length L and the fault-free count is m, then the possibility of aliasing is

[C (L, m) - 1] patterns out of total number of possible strings of length L, (2L - 1).

One Count example

11110000

11001100 1100000011101010

10101010

a

b

c

f

(11100)

(10010)

(10110)

(10100)(10110)

For m = 5 and L = 8, aliasing probability will be Pa (m) =( C(8,5)-1 ) / (2^8-1) =55 /255 0.2. Not a very reliable method

Transition Count

1

1

1

i

L

ii rr

CUT +Test

Patterns

Q

QSET

CLR

D

r i

r i -1

Computes transitions

Signature Analysis

TEST SETL

CIRCUIT UNDERTEST

(CUT)

LSFRN

STAGES

km

Uses LFSR to obtain a signature

LFSR as Response Analyzer

Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter

Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial

CRCC divides the PO polynomial by its characteristic polynomial Leaves remainder of division in LFSR Must initialize LFSR to seed value (usually 0) before testing

After testing – compare signature in LFSR to precomputed signature of fault-free circuit

Signature Analysis

LFSR seed is “00000”

Signature by Logic Simulation

Input bitsInitial State

10001010

X0

010001111

X1

001000010

X2

000100001

X3

000010101

X4

000001010 Signature

Signature by Polynomial DivisionInput bit stream: 0 1 0 1 0 0 0 1

0 ∙ X0 + 1 ∙ X1 + 0 ∙ X2 + 1 ∙ X3 + 0 ∙ X4 + 0 ∙ X5 + 0 ∙ X6 + 1 ∙ X7

X2

X7

X7

+ 1

+ X5

X5

X5

+ X3

+ X3

+ X3

X3

+ X2

+ X2

+ X2

+ X

+ X

+ X + 1

+ 1

X5 + X3 + X + 1Char. polynomial

remainder

Signature: X0 X1 X2 X3 X4 = 1 0 1 1 0

Polynomial division equivalence of data compression

Test generation based on a nonprimitive polynomial

x4 + x2 +1

generates only 6 out of possible 15 states

Multiple-Input Signature Register (MISR)

Problem with ordinary LFSR response compacter: Too much hardware if one of these is put on each

primary output (PO)

Solution: MISR – compacts all outputs into one LFSR Works because LFSR is linear – obeys superposition

principle Superimpose all responses in one LFSR – final

remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial

Modular MISR Example

X0 (t + 1)

X1 (t + 1)

X2 (t + 1)

001

010

110

=X0 (t)

X1 (t)

X2 (t)

d0 (t)

d1 (t)

d2 (t)

+

Space Compaction – parallel outputs

M4

PSA

1 2 3 4

M3M2 M

M1

M2

M3

M4

SSA

1 2 3 4

M(X)= M1+ X1M2+ X2M3+ X3M4

M1

M2

M3

M4

BELLMAC

LSFR

Test data compression BIST

To reduce the number of response data a compression Based on LFSR (signature analysis) is used.

Probability that 2 sequences which differ by 1 bit only will have the same signature is zero

Data entering LFSR serially produces a reminder of the division of the data stream polynomial by the polynomial used for LFSR design


A faulty data stream will yield the same signature (reminder of polynomial division) as a fault-free data when they have the same reminder

The likelihood of this is in the range of where n is the number of the compressor bits

The same effect can be obtained on multi-input shift registers with faster processing speed & smaller chip area.

n2/1

Fault-free signature

2n-1 faulty signatures


As in the single-input case the probability of detecting uniformly distributed fault in the output stream is (1 - 2-n )

Probability of not detecting error after checking its signature is greater than 2-n - the probability of not catching the signature error.

Example 1: n = 4, Aliasing probability = 6.25%Example 2: n = 8, Aliasing probability = 0.39%Example 3: n = 16, Aliasing probability = 0.0015%

LFSR Design Guidelines

Chose r large enough to reduce 2-r

Repeat test using different feedback connectionsRepeat test with different test vectorCompress serial output of MISR into LFSR to capture errors

In using LFSR for data compression:

BILBO RegistersBuilt-in logic block observation BILBO is widely used in BIST applicationsBILBO which is a special purpose LFSR can be used as latches & shift register during normal mode

Four modes of operation depend upon B1B2 values, for B1B2 equal to :

11 BILBO is a set of register cells

00 BILBO is a LFSR

10 BILBO is a multiple-input signature analysis or pseudorandom test generator

01 is a register reset mode - all registers are set to zero

Test Per Scan BIST

Scan register

Scan register

Comb. logic

Scan register

Comb. logic

Scan register

Comb. logic

PG

RA

BISTControl

logic

PI and PO disabled during test

BIST enable

Go/No-go signature

Built-in Logic Block Observer (BILBO)

Combined functionality of D flip-flop, pattern generator, response analyzer, and scan chain Reset all FFs to 0 by scanning in zeros

C1

C2

Scan-in

C1

C2

Scan-in

(a)

Reg 1

Comb.A

Reg 2

Reg 3

Comb.B

LFSR

Comb.A

BILBO

MISR

Comb.B

C1C2

C1 C2 Mode

0 0 Scan 0 1 Clear 1 0 MISR 1 1 Normal

(b)

(c)

BILBO Registers

C1

C2

Scan-in

C1C2Mode0 0 Scan0 1 Clear1 0 MISR1 1Normal

C1

C2

Scan-in

C1 C2 Mode 1 1 Normal

OutputsQ1,Q2,Q3

Scan-out

x1

321

BILBO Registers

C1

C2

Scan-in

C1 C2 Mode 0 0 Scan

OutputsScan-out

Scan-out

x1 x2 x3

321

C1

C2

Scan-in

C1 C2 Mode 1 0 MISR

OutputsQ1, Q2, Q3

x1 x3x2

321

BILBO Registers

Mode 1 : B1 B2 = 11

Mode 2 : B1 B2 = 00

Mode 3 : B1 B2 = 10

A general BIST configuration incorporating BILBO registers

A BILBO configuration including all memory elements

Subcircuit partitioning & diagnostics

minimize BIST overheadminimize the performance degradationincorporate the memory elements in BILBO registersmaximize fault coverage - use exhaustive test if necessary

Partitioning is useful to reduce size of UUT &increase fault coverage. Partitioning objectives:


Example : Partitioning of a circuit for autonomous testing


no don’t care allowedinitialize all memory elements (preferably include them in BILBO register)avoid race & hazard

Partitioning requirements

Some diagnostics is possible in BIST, butadditional test must be run to identify faulty submodule

BIST Summary

LFSR pattern generator and MISR response analyzer – preferred BIST methods

BIST has overheads: test controller, extra circuit delay, primary input MUX, pattern generator, response compacter, DFT to initialize circuit and test the test hardware (should not take more that 5% of the design area)

BIST benefits: At-speed testing for delay and stuck-at faults Drastic ATE cost reduction Field test capability Faster diagnosis during system test Less effort to design testing process Shorter test application times

digital testing: built-in self-test

Documents