dimension critique

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT 1

2006

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La Nanoélectronique et la mécanique quantique font-elles

bon ménage ? Simon Deleonibus

Laboratoire Nanodispositifs Electroniques (Electronic Nanodevices Laboratory)

CEA/LETI/Département NANOTEC(NANOTEC Division) CEA Grenoble

17 rue des Martyrs 38054 Grenoble Cedex France

Tel : 33 (0)4 38 78 59 73 Fax: 33 (0)4 38 78 54 59

email: [email protected]


2006



1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

No

mb

re d

e t

ran

sis

tors

par

pu

ce

100µm

10µm

1µm

0,10µm

10 nm

Dim

ensi

on c

riti

que

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

Progrès possible grâce à l’introduction continue d’innovations

micr

opro

cesse

urs

mémoire

s dynamiques

(DRAM

)

course à l’intégration / course à la miniaturisation

Introduction contacts « plugs »(3niv met)

Introduction vias « plugs »,CMP(4niv met)

Introduction FSG(6 niv met)

Introduction damascene(5niv met)

Introduction Cu (7niv met)

Introduction Cu+H(M)SQ (9niv met)

Introduction polymères +ALD (10niv met)

Introduction ULK (11niv met)

Introduction poly gate

Introduction polycide

1 milliard

•loi de Moore initiale (1965) : nbr. transistors x 2 /an

Office PC

Main Frame

C.T.V.

VCRDefense

Home PC

InternetPortable

Convergence

10 millions

Introduction STI, salicide

CameraDigitale

DRAM X4/3an

s

MPU X2.5/3ans


2006



Three major product families

• High Performance (HP) t=CV/I

– Connection to power network

• Low Operating Power (LOP)

– Intermittent Nomadic Function

• Low Stand-by Power (LSTP) Pstat= VddxIoff

– Permanent Nomadic Function

Nomadic consumer and professional products: biggest market share

Pdyn=CVdd2 f

Ptot=Pstat+ Pdyn

few 109 tr./system

109 tr./system

few 108 tr./system


2006



La baisse des coûts, moteur de la diffusion de la microélectronique

1995

Une réduction des coûts unique dans l’histoire de l’industrie

(40 000 F)

(3 000 F)

(800 F)

(200 F)

(35 F)

(3 F)

(40 centimes) (3 centimes)

(500 000 F)

Coût de 1 million de transistors(équivalent à un livre de 200 pages)

1973 1977 1981 1984 1987 1990 2000 2005


2006



Les deux secrets de la microélectronique

Miniaturisation

Traitement collectif

De plus en plus de transistors par centimètre carré de Silicium

De plus en plus de centimètres carrés de Silicium traités simultanément

1 lot de fabrication à ST Crolles 2 : = 500 milliards

de transistors !!!

1 lot de fabrication à ST Crolles 2 : = 500 milliards

de transistors !!!

En 2015, l’ensemble des livres de la BNF F. Mitterrand sur une seule puce de silicium !

Plaques de silicium de 100, 200, puis 300 mm de diamètre

Lot de fabrication

Réduction des coûts


2006



1999: First 20nm MOSFET

20nm poly-gate MOSFET(hybrid lithography)

SiO² hard-mask

Gate length: 20nmGate oxide thickness:1.2nmExtensions; BF2 pockets; n+ HDDS.Deleonibus et al. ED Letters April 2000

Simulation(ATHENA/SILVACOTM)

Estimated metallurgical length: 4 nm(1018cm-3)

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0 0.5 1 1.5

Lg=20nmLg=25nm

Id(A

)Vd(V)

1.2nm gate oxyde

Beyond the roadmap !!

source

gateextension

drainHDD

pockets

Lm

Lg

Gate oxide


2006



Low field mobility Low field mobility degradation due to halo degradation due to halo overlap mostly in the case overlap mostly in the case of efficient SCE controlof efficient SCE control

LETI: G. Bertrand et al., ULIS 2003, SSE 2004

Leakage currents and Access resistance are still issues

source

gateextension

drainHDD

pockets

Lm

Lg

Gate oxide

Nanoscale bulk MOSFET Lg= 15nm

Lg~16nm

6893 P18

0

60

120

0

100

200

300

400

500

0,01 0,1 1 10

Gmmax

Gmmax

Rsd

>>2000 .µm

Rsd

=1200 .µm

Gm

max

(S

/m)

@ V

d=

50

mV

Gm

sat (

S/m

) @

Vd=

1.5

V

Lg

Scattering by impurities of Scattering by impurities of highly doped short channelhighly doped short channel ( room temperature)( room temperature)


2006



Sommaire

•Introduction et contexte

•Dispositifs CMOS : physique, effets ultimes (géometries ultimes)

•Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling)

•Nécessaires « Boosters » pour maintenir le progrès

-Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite

-Nouvelles architectures CMOS Nanoélectronique

•Architectures post CMOS. Opportunités mémoires

•Conclusions : futurs systèmes/puce(SOC), feuille de route


2006



Sommaire










2006



source

grille

extensiondrain

HDD

substratCanal

isolant de grilleLg

Tox

Xj

L

Transistor MOS

2ox .2

µCTGDsatD VVV

L

WI

2

0

exp0

q

kT

CC

CCC

L

WµCI

kT

qVII

Dox

ssDoxD

GD

Courant d’inversion faible (« sous le seuil ») Courant de saturation

(inversion forte)

G

BFFBT C

QVV 2

Tension de seuil

n(p) n(p)p(n)


2006



Saturation regime and non equilibrium

Velocity saturation : vsat max ≤vth

where:eff

th m

kTv

2

Velocity overshoot : vinj>vsat

Non equilibrium (non stationary transport).

If no collision in channel : ballistic transport

effm

qµ

2

2

1

kE

meff


2006



Classical parasitic effects

SCE : Short channel effect (charge sharing S-D-G)

Effet de canal court(perte de contrôle charge)

DIBL: Drain Induced barrier Lowering Abaissement de barrière induit par le drain

punch through

gate current

DIBL

SCE

oVg

oVdoVs(0V)

LeKBV FT 2/1)2(

L

VVT d2

substrate current

ox

i

CNq

KBS2

L

xx

xej

j

121 0

201,0 µm

2006



Caractéristiques et effets parasites dans un transistor MOS

10-15

10-13

10-11

10-9

10-7

10-5

10-3

-1 -0.5 0 0.5 1 1.5

Vd=50mVVd=1.5VVd=50mVVd=1.5V

Id (

A)

Vg (V)

b/

10-14

10-12

10-10

10-8

10-6

10-4

10-2

-1 -0.5 0 0.5 1 1.5

Vd=50mVVd=1.5VVd=50mVVd=1.5V

Id (

A)

Vg (V)

a/

65nm

75nm

perçage DIBL(*)

VT=DIBL+SCE SCE(*)inversion forte

inversion faible(pente 1/S)

VT

VT: tension de seuil

Lg = 75 nm

Lg = 65 nm

Vg step = 250 mV

W = 10 µm

0 0.4 0.8 1.2 1.60

1

2

3

4

5

6

Id (

mA

)

Vd (V)

Vg=1.5V « Courant de saturation »

ox

D

CC

qkTS 1).10log(.

0XC Si

D

ox

oxox

TC

Sous le seuil

oxD CC

decmVq

kTS /62)10log(.


2006



Parasitic effects in an ultimate MOSFET

Punch-through

Direct tunneling gate current

DIBL+SCE + punch-through : classical effects* Direct tunneling current through gate oxide * Field assisted tunneling current drain/channel diode

DIBL

SCE

oVg

oVd

Field assisted tunneling current

ToxEUmqh

P 024exp

- E

U0

Tox

I~ F2exp[-A Eg 3/2 / F]

* direct tunneling current between source and drain(<10nm)

S-D direct tunneling


2006



Sommaire









2006



ITRS: 3 devices families according to applicationsIsat, Vdd vs Ioff ITRS 2003

0

500

1000

1500

2000

2500

3000

0,001 0,01 0,1 1 10 100 1000

Ioff(nA/µm)

Isat

(µA

/µm

)

0

0,2

0,4

0,6

0,8

1

1,2

1,4

VD

D(V

)

LOP HPLSTPLow STandby Power Low Operating Power High Performance

18

110

110

18110

18

22

3245

65

80

90

100

110

18

110

18

110

18

Ptot= Pstat + Pdyn

Pstat= VddxIoff

and Pdyn=CVdd2 f

d= CV/Isat

MOSFET Engineering

2006



Classical MOSFET linear scalingChannel length K

Voltage U

Gate oxide K

Junction depth K

Electric field U/K2

Channel doping U/K

Parasitic capacitance K(ACox,ACj)

Current (vel. sat.) U2/K(U)

Delay(vel. sat.) K2/U(K)

Power (vel. sat.) U3/K(U2)

Speed.Power product KU2 Baccarani et al,IEDM 1984

To double density (X2), (follow Moore’s law)

then

Nowadays ITRS trend from technology node to

the next node !!

2

2K

i.e.

Node n: D

Node n+1: K.D


2006



Sommaire










2006



Basic Quantum effects on energy

222

2

L

n

mEn

rkin

ne .0

b0 TEU2mq

h

4πexpP

-Energy Barrier: tunneling

Schroedinger’s equation:

Possible solutions:Eigenvalues for energy E and eigenfunctions

(E, k - allowed values in reciprocal space)Typical significant cases in Microelectronics

-Potential well : Standing waves

L

Tb

and combination of both: inversion layer at MOS gate oxide interface!

L

nkn

U0

EVm

).1

(2 rr

2


2006



Quantum confinement => degeneracy splitting

(id. standing waves)

repopulation of higher energy levels with different meff

higher threshold energies required

« dead depleted » zone due to reflexion of electron wave function

Coexistence of 3D and 2D electron gases at a MOSFET interface

2D electron gas energy splitting in triangular potential

2D gas discretized levels

3D gascontinuum

M O S

EF

quantum correctionquantum correction

« Dead depleted » zone


2006



Example: Global Strain on Si/SiGe

EcEv

lh hh (4) (2)

Si

Six Ge1-xEv =0.74x

Ev Ec

(2) (4)hh lh

Six Ge1-x

Si Ec =0.6x

Relaxed Si

Biaxial Compressive strain

Si standardsubstrate

SiGe

a= 5.43

Relaxed Si

Biaxial Compressive strain

Si standardsubstrate

SiGe

a= 5.43

Biaxial tensile strain

Relaxed SiGe

SiGe relaxedvirtual substrate

Si

5.43<a<5.65

Biaxial tensile strain

Relaxed SiGe


Si

5.43<a<5.65

Relaxed SiGe


Si

5.43<a<5.65

Band offset and splitting Lower meff bands accessible


2006



Strain and bandgap engineeringCompressive strain Tensile strain Tensile strain

Six Ge1-x

Si

In Si1-x-y GexCy No strain if x=10y

Si

Si1-y Cy

Si

Six Ge1-x

a= 5.43

5.43<a<5.65

Compressive strain Tensile strain Tensile strain

Six Ge1-x

Si

Six Ge1-x

Si

In Si1-x-y GexCy No strain if x=10y

Band offset and splittingBand offset and splitting

Si

Si1-y Cy

Si

Si1-y Cy

Si

Six Ge1-x

SiSi

Six Ge1-x

a= 5.43

5.43<a<5.65

Global

Local

Stressors (CESL, source & drain, salicide,…)

nMOSnMOS

30nmsSiSiGe

30nmsSiSiGe

pMOS

pMOSnMOS

Band offset and splitting

EcEv

lh hh (4) (2)

Si

SixGe1-xEv=0.74x

Ev Ec

(2) (4)hh lh

Si

Si1-y CyEc=-6.5y

Ev Ec

(2) (4)hh lh

Six Ge1-x

Si Ec=0.6x


2006



Strained Si + strained Ge channels

0

5 10-6

1 10-5

1.5 10-5

2 10-5

2.5 10-5

3 10-5

-1.2 -0.8 -0.4 0 0.4 0.8 1.2

A

x6

VD=+/-1.2V

W=400µm

LG=10µm

TiN CVD gate

x1.65

Gate overdrive VG-V

TH (V)

Dra

in C

urre

nt I

Dsa

t (A/µ

m)

Dra

in C

urre

nt I

Dsa

t (A/µ

m)

Dra

in C

urre

nt I

Dsa

t (A/µ

m)

PMOS NMOS

s-Si

Si

s-Ge

SiDra

in C

urre

nt I

Dsa

t (A/µ

m)

80

160

240

320

400

480

560

0 2 105 4 105 6 105 8 105 1 106

Mob

ility

(cm

2 .V-1

.s-1

)

Effective field (V/cm)

s-Ge

s-Si

Si refs.

Si refs.

(holes)

(holes)

(electrons)

(electrons)

universal

universal

HfO2/TiN

gate stackelectrons

holes

• Improved hole mobility in compressively strained Ge and electron mobility in tensely strained Si

• Symetrical drain current for any dual channel CMOS

LETI: Weber et al., IEDM, 2005


2006



-40

-20

0

20

40

60

80

100

0,01 0,1 1 10

Lo

w f

ield

Mo

bili

ty g

ain

(%

)

Effective Gate Length (µm)

symbols = exp.lines=input for Id model

Strained Devices

= CESL-sSi

= sSi= sSiGe

LETI: F.Andrieu et al. VLSI Tech. Symp, June 2005,Kyoto

ESL-sSi : m* reduction strain enhancement sSiGe : m* reduction extra charged defects sSi : quantization effects phonon scattering not dominant

Original & in-depth characterisation of µeff in strained devices

ESL-sSi : m* reduction strain enhancement sSiGe : m* reduction extra charged defects sSi : quantization effects phonon scattering not dominant

Original & in-depth characterisation of µeff in strained devices

Short channel issues on strained architectures

Global + Local

Global


2006



Ultimate transport properties in Si. Ballistic effects

Initial injection velocity at source Reflexion on ionized dopants(channel or drain) Interface roughness Backscattering at the source , from dopants

will reduce ballisticity

Tunneling component

Thermionic component

xy

Energy subband iValley j

BallisticBallistic currentcurrentTunneling component

Thermionic component

xy

Energy subband iValley j

BallisticBallistic currentcurrent

Figure 1. 2-D potential energy distribution in the channel. The essential mechanisms governing the carrier transmission are also illustrated.

Thermionic current

Tunneling current

Ballistic

and

Diffusive

Transport2/1

*

2)(

)(

)(2

m

knv

VVCn

nvqnT

TI

Tgeff

satD

<v(n)> average thermal velocity

Ceff gate/channel capacitance

T: transmittance

Lg< Lm(mean free path 100nm@300K)

S.Datta etal, IEDM 1998, San Francisco(CA) Dec 1998

G.Bertrand et al SNW2000 Honolulu(HI), ULIS2003Munchen(FRG)


2006



Scaling supply voltage

Issues to address(trade of Performance & Power): room temperature operation threshold voltage controlparasitic effects

The most severe constraints are due to(*) :doping concentration fluctuations small volume,asymetry short channel effects low VT vs. VT - low Vsupply -

Tox thickness,doping concentration, Xj

leakage current in subthreshold regime even with S=60mV/dec(FDSOI) and VT = 0,20V (Vsupply=0,5V) we will get Ioff = 1nA/µm

tunnel currents SiO2 tunneling dielectric , F-N high doping level

P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f

(*) much higher impact than thermal fluctuation, energy equipartition, quantum fluctuations S.Deleonibus et al. ESSDERC 1999, Leuven, Sept 1999


2006



High K dielectric integration:Replacing SiO2

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)

J g, simulated for SiON, planar bulk

Jg, limit for SiON, planar bulk

EOT, planar bulk

EOT, UTB FD

EOT, DG

High-k needed beyond thiscrossover point

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG

High -k needed beyond thiscrossover point

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

2005 2007 2009 2011 2013 2015 2017 2019

Calendar Year

J g(A

/cm

2)

0

5

10

15

20

25

EO

T (A

)



EOT, planar bulk

EOT, UTB FD

EOT, DG


ox

ioxi ttEOT

Tox=1.2nm Active area(10cm2 circuit): 1cm2

*Pstat(0.5V)= 5W => 500W/m2(1/2 AM1) *Pstat(1V) = 50W => 5kW/m2

*Pstat(1.5V) = 750W !! => 75kW/m2!! (Small Nuclear Power station to keep 50 000 PC in standby mode!! …)

SixOxN yor large mobility gap

SiHigh KmaterialGate

(poly,metal)

(*) SiO2 AlN Al2O3 Si3N4 Ta2O5 TiO2 BaTiO3 HfO2 ZrO2

Ec(MV/cm) 10 -13 6-15 5 5-10 3.5 1 3

ε r 3.9 8.5 10 7.5 22-27 15 -40

60 -100

>1000 30 25

Eg(eV) 9 6.2 7-8 5 4.4 3.2 4.3 5.68 5.16 -7.8

(*) Bulk materials characteristics

Possible candidates


2006



Metal Workfunctions m

tox

tdepletion

tinversionS D

G

Cg-ox

Cg-depl.

Cg-inv.

Tgateeletcrode

Cg =1

1

Cg-ox

1

Cg-depl

1

Cg-inv+ +

tox

tdepletion

tinversionS D

G

Cg-ox

Cg-depl.

Cg-inv.

Tgateeletcrode

tox

tdepletion

tinversionS D

G

Cg-ox

Cg-depl.

Cg-inv.

Tgateeletcrode

Tgateeletcrode

Cg =1

1

Cg-ox

1

Cg-ox

1

Cg-depl

1

Cg-depl

1

Cg-inv

1

Cg-inv+ +

SMSze Physics of Semiconductor Devices 1981 J.Hauser IEDM 1999 Short Course

Nb 3.99-4.30

Al 4.06-4.20

Ta 4.12-4.25

Mo 4.30-4.60

Zr 3.90-4.05

V 4.12-4.30

Ti 3.95-4.33

TaN 4.2-3.9

Ec

Ev

Ei

Co 4.41-5.00 Ru 4.60-4.71

W 4.10-5.20 Rh 4.75-4.98

Os 4.70-4.83 Au 4.52-4.77

Cr 4.50-4.60 Pd 4.80-5.22

ZrSi2 TiSi2

TaSi2 CrSi2

MoSi2WSi2

NiSi2CoSi2

RhSi PdSi

WNx

TiNx 4.60-4.90

qSi= 4.05eV

qmSi(Ei)=4.61eV

Vacuum level

Re 4.72-5.00

Ir 5.00-5.70

Pt 5.32-5.50

RuO2 4.90-5.20

Eg=

1.12

eV

TaSixNy

WSixNy

WCxNy

TiSixNy

mn(Ei+0.2V)

mp(Ei-0.2V)

mn+(Ei+0.55V)

mp+(Ei-0.55V)

Midgap

Silicon

reduce gate depletion capacitance

« Dead depleted » zone

invdeplox tttEOT


2006



Sommaire










2006



Silicon On Insulator

A

B

SOI wafer A

New A B

Smart-Cutsplitting at 500°C

Annealing 1100°CCMP touch polishing

Wafer A becomes B

A

B

A

BB

SOI wafer AA

New A B

Smart-Cutsplitting at 500°C

Annealing 1100°CCMP touch polishing

Wafer A becomes B

SiO2

Si

tSi

L

M. Bruel, Elec. Lett., vol. 31, n° 14, p. 1201, 1995

A B

A

A

A

B

Initialsilicon

Oxidation

Smart-Cutimplant

Cleaning andbonding

Buried oxide

H+ ions5.1016 cm-2

AA B

A

A

A

B

A

B

Initialsilicon

Oxidation

Smart-Cutimplant

Cleaning andbonding

Buried oxide

H+ ions5.1016 cm-2

Smart-Cut process Cj

-reduced parasitic capacitance -improved isolation -improved electrostatics

improved FOM /bulk

20

40

60

80

100

120

140

160

180

0 0.02 0.04 0.06 0.08 0.1Pr

opag

atio

n de

lay

(ps)

Power consumption (µW/MHz/gate)

Single inverterL = 0.25 µm

Wp/W

n=5/2.5

BULK

SOI


2006



Co-integrated Dual Strained Channel On Insulator

down to 12nm gate length with a high-k/metal gate stack

F. Andrieu et al., IEEE SOI conf., 2005

20nm

pFETs LTiN=12nm

BOX

Si0.6Ge0.4

sSDOI

20nm

sSDOI

nFETs LTiN=14 nm

NiSiPoly Si

TiNHfO2

0

200

400

600

800

1000

-1.2 -0.6 0 0.6 1.2

Dra

in C

urr

en

t (µ

A/µ

m)

Drain Voltage (V)

WG=10µm

LG=15nm

DCOI

|VG-V

Tlin|=1V; 0.8V; ...

nMOS

pMOS

0

50

100

150

200

250

300

350

0 5 1012 1 1013

Si/HfO2

sSi/HfO2

DCOI/HfO2

Si/SiO2

sSi/SiO2

Hol

e M

obili

ty (

cm2/ V

s)

Inversion Charge Density (cm-2)

+100%

SOI or sSDOI

DCOI

LG=10µm

0

400

800

0 5 1012 1 1013

Si/HfO2

sSi/HfO2

Si/SiO2

sSi/SiO2

Ele

ctro

n M

obili

ty (

cm2/ V

s)

Inversion Charge Density (cm-2)

+85%+100%

SOI

sSDOI

LG=10µm

VT matching SOI -> LP DCOI -> HP


2006



Fully Depleted SOIV

T(V

)

Tsi(nm)

Bulk or PD SOI like

FDSOI

Quantum

confinementN+ poly gate

J.Lolivier et al, ECS Spring meeting, Paris, May 2003

222

2

sieffn T

n

mE

Quantum confinement in thin film(TSi thk):

111 2

2ox

siAffbT C

TqNVV Fully depleted SOI:

Low Doped thin channel

=> Lower dopant fluctuations

=> Higher VT stability vs thickness

Gate Workfunction engineering for dual gate /undoped FD channel Low VDD


2006



With thinner buried oxide, fringing fieldsin substrate depletion region

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

Fringing fields through buriedoxide contributeto SCE

Adding a ground-plane help reducingSCE and DIBL but degrade Ssw

Except if ground-plane connected to gate=> Double-gate device

1 2

3 4

With thinner buried oxide, fringing fieldsin substrate depletion region

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

Fringing fields through buriedoxide contributeto SCE

Adding a ground-plane help reducingSCE and DIBL but degrade Ssw

Except if ground-plane connected to gate=> Double-gate device

1 2

3 4

FDSOI optimization from single gate to multi gate

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

GATE

SOURCE DRAIN

SILICON SUBSTRATE

PLANAR DGMOS

Planar or non planar?

(design/layout issue very strong)

BOX

GATE

CHANNEL

FINFET, Tri Gate FET


2006



Double gate - channel population

Ravaioli, SINANO Modeling Summer School Glasgow Aug 2005


2006



Double gate versus Single gate(FDSOI) MOSFET by Wafer Bonding(Lg=40nm)

M.Vinet et al. , SSDM 2004, Sept2004, Tokyo

IST NESTOR project


2006



Planar Double gate by wafer bonding

Lg~13nm

Lg~8nm

Lg~13nm

Lg~8nm

LETI: M.Vinet et al. IEEE EDL, May 2005

IonN(10nm) =1130µA/µm IoffN(10nm)=7µA/µm

Lg=10nm

IonN(20nm) = 1250 µA/µm IoffN(20nm)= 1.3 µA/µm

Lg=20nm

Best Ion/Ioff trade off @ Lg=10nm

published to date!!


2006



FET Non Planar MultigateFET Non Planar Multigate

Excellent ION/IOFF ratio of 5.105 for a 10 nm non planar device and very good channel control

LETI : Jahan et al, VLSI Tech Symposium, June 2005 Kyoto(Japan)

Functional N-Fets tested down to Lg=10 nm

NMOS: ION=326µA/µm, IOFF=600pA/µm @ VD=1.2V, SS=90mV/dec, DIBL=130mV

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

-0.2 0 0.2 0.4 0.6 0.8 1 1.2VG (V)

I D (

A/µ

m)

NMOSLg=10 nm

WFIN=50 nm

VD=0.1V

VD=1.2V

TEM cross-section of a 60 nm silicon finger fet device

Si

HfO2TiN

Lg = 10 nm


2006



Silicon On Insulator based architecturesSubthreshold regime – optimizing electrostatics

• Subthreshold regime is limited to 60mV/decade at 300K

SiO2

gate

SiO2

SiFilm thickness tSi required for a given L value

x 1/4

X 1/2

x1

X 1-2B.Doyle – VLSI’03 10A-2, 2003M. Ieong et al. Science vol. 306 Dec. 2004

* No direct S-D tunnel introduced …

Ratio : tsi/L

SiO2

Si

tSi

L

SiO2

Si

Planar Fully Depleted SOI

Planar Double-gate, FinFET

Tri-gate,-FET

Surrounding-gate(nanowire)

2006



Gate SiPoly/TiN/HfO2

SiChannels

HM

S/D SEG

SOISource Drain

BOX

multigate devices HfO2/TiN gate stack

nanowire matrix with HfO2/TiN gate

Planar multichannels:

SiHfO2/TiNSi

HfO2/TiNSi

HfO2/TiNSi

SiHfO2/TiNSi

HfO2/TiNSi

HfO2/TiNSi

RTB: 3D Nanowire matrix

(a) CVD growth of single nanowire

200 nm(b) CVD growth within Al2O3 pattern

(c) MBE growth of wire heterostucture

Courtesy of : T.Ernst et al., E.Hadji et al.

From Multichannels to Nanowires (planar and 3D)


2006



Sommaire










2006



General trend towards few electron electronics


2006



Candidates for Post CMOS Nanoelectronics


2006



Coulomb blockade effect and Single Electron Transistor


2006



10 -11

10 -10

10 -9

10 -8

10 -7

10 -6

10 -5

-0,4 -0,2 0 0,2 0,4 0,6

Vd=100µV

Vd=300µV

Vd=500µV

Dra

in C

urr

en

t (A

)

Vg

T=75K

T=20K

Lg=20nm W=10µm

Limits: from CMOS to SET-MOS

CEA /CEA-LETI:

M. Specht et al. IEDM1999

G. Bertrand et al., Proceedings ULIS 2003


2006



Few electron phenomena will appear in future NV memory generations

Molas et al., IEDM2004, San Francisco(CA), Dec. 2004

Si substrate

Control gate

ADAMANT

N= 1012cm-2, = 5nm

LPCVD Si

Non Volatile (Flash) Memories

multilevel storage!!

Defect in conventional Flash memories (Stress Induced Leakage Current): => retention

10 10010

102

103N

um

ber

of e

lect

ron

sp

er

bit

, N

Flash TechnologyNode[nm]

VTh-max=3VNOR Flash

NAND Flash

Si-Nanocrystals Memories(NAND )

35nm

200

10 10010

102

103N

um

ber

of e

lect

ron

sp

er

bit

, N

Flash TechnologyNode[nm]

VTh-max=3VNOR Flash

NAND Flash

Si-Nanocrystals Memories(NAND )Si-Nanocrystals

Memories(NAND )

35nm

200

35nm

200

insulator

Tunn.Ox

Control gate

Floating gate

Control gate

Nanocrystals


2006



Molecular Memories

WORM

• Memory applications of molecular electronics– Strong market demand – High density and low cost– Redundancy

• Few examples– Porphyrins …– Thermal budget > 400°C– Multi-Bit/cell

Meyyappan NASA 2004

Bocian UC Riveside 2003

Forrest Princeton 2003


2006



Sommaire








•Conclusions : futurs systèmes/puce(SOC), feuille de route architectures


2006



Integration of new functions on chip. Future System On Chip

MEL-ARI Nanoelectronics Roadmap

few e-memories

Training, education issues to mix devices in design!!

Integration of new materials for new functions with new devices exploiting new physical phenomena Pluri and inter

disciplinarity!!


2006



Perspectives: Dispositifs CMOS Nanoelectroniques

• Réduction de leurs dimensions : visibilité jusqu’à Lg=5nm(2020) /encore de nombreux défis!!

• Constitueront la plateforme de base de la Nanoelectronique Nouvelles fonctionnalités sur la puce=> Pluridisciplinarité

• Consommation énergétique constitue le défi majeur tout en gagnant en performances (Valim: sub 1V). => Optimisation : architectures des dispositifs(*) et systèmes

(*) effets quantiques rôle majeur


2006



Construire un pôle compétitif internationalement

Education

Industrie

• Multidisciplinarité• Excellence • Masse critique• Plate-forme technologique

RechercheOperationnel en 20064000 personnes en 2007

170 M€ investis par les partenaires

Merci de votre attention


2006



Formulaire(1)

Courant dans le transistor en régime linéaire: (Vd<Vdsat):

Courant dans le transistor en régime de saturation : (Vd=Vdsat):

A Vd=Vdsat le canal est pincé

Transconductance: régime linéaire

Transconductance: régime de saturation

Temps de propagation par porte CMOS:

d= CV/Isat si les TMOS N et P sont symétriques(Isat N=IsatP)

s=1/2 CV/(IsatN-1 + IsatP-1) si les TMOS ne sont pas symétriques

Courant sous le seuil(VG<VT)

2. DTGDoxDlin

VVVV

L

WµCI

2ox .2

µCTGDsatD VVV

L

WI

DG

Dm V

L

W

V

Ig ox

maxmax µC

)(µCox TGG

Dsatmsat VV

L

W

V

Ig

2

0

exp0

q

kT

CC

CCC

L

WµCI

kT

qVII

Dox

ssDoxD

GD

outloadDS CCC /


2006



SkT

qLog

dqV

kT

dLog I

kT

qLog

C

C

G

D

w

ox

10 10 1.

( ).

Effets de canaux courts(partage de charges entre la source le drain et la grille)

Pente en faible inversion

TEUme

hP o2

4exp

Probabilité d’effet tunnel

Formulaire(2)

F

EgAFI

2/32 exp

Effet Fowler Nordheim(effet tunnel assisté par le champ électrique)

12141214

2/12/1

j

jox

oxB

j

j

ox

wBT x

W

W

x

L

t

x

W

L

x

C

CV

ox

BFFBT C

QVV 2

Tension de seuil

qinvdeploxG CCCC

1111Capacité de couplage grille/ canal(déplétion+effets quantiques

dans le canal)

ox

oxms

ox

oxmsFB C

Q

C

QV

G

BFFBT C

QVV 2

P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f

ox

SiAFFBT C

TqNVV

22

sMMS

VT avec contribution (déplétion+ effets quantiques)

VT TMOS SOI Fortement déserté

Puissance totale, Puissance dynamique


2006



Flow for Future Simulations: from Poisson / Drift Diffusion to Schroedinger/Monte Carlo

coll

BBkBr

B

t

ff.

qEf.

m

k

t

f

)( rr V

Corrected Boltzmann’s equation

EVmeff

).1

(2 rr

2


2006



Downscaling … and modeling

Quantum transportWigner function modelGreen function modelQuantum hydrodynamic model

Semi-classical transport

Hydrodynamic modelMonte-Carlo method

Classical transport Drift-diffusion model

Simulation model

60 70 80 90 00

100 m

10 m

1 m

100 nm

10 nm

year

dim

ensi

ons


2006



Material µn (cm2V-1s-1) µp (cm2V-1s-1) th (W/m/K) Rel. K Eg(eV) Vsat(107cm/s)

Si 1400 500 141 11.9 1.12 0,86

Ge 3900 1900 59.9 16 0.66 0,60

GaAs 8900 400 46 12.5 1.42 0,72

C-Diamond

1800 1800 >1500 5.7 5.47 2,7

InSb 78000 750 _ 16.8 0.16 5,0

Opportunities for other materials on Silicon

LETI: S.Deleonibus, ICSICT 2004, Beijing, Oct. 2004 , S.Deleonibus et al., Int.Journ. High Speed Electronics, March 2006

Highest thMost compact logic High short channel effect immunity

Highest µn but Worst µn/µp!!

Passive layer combine w BOx(thermal shunt)/graphite

Well established high quality material (>40yrs experience) Oxidizable !

Silicon compatible Available in all fabs

Opto Power RF applications Ge compatible


2006



Perspectives: Nanoelectronics CMOS devices

• Scaling can be foreseen down to Lg=5nm.• Nanoelectronics Base platform • Power consumption: major issue (sub

1V supply voltage). => Device/ system architecture optimization

New routes (LETI playground)

3D integration: elementary function

New SOC concepts(analog, RF, Hi Perf,Memories): compound SC/OI/Si based substrate, molecular electronics, …

New device architectures: Max Ion/Ioff and Low Power Multigate, Multichannels, Nanowires, Nanotubes, IMOS,…

FDSOI: Advanced substrate (BOX, stressors, thermal shunts,…) Dual strained channels(GeOI option); Dual metal gates (Hi Perf); Metallic S&D (Schottky vs ohmic cts)

65nm 45nm 32nm 22nm‘07 ‘09 ‘12

PDSOI

‘15

bulk

strain

ADD substrateengineering

ADD High µ material

MuGFETMuCFET

…

µ ?

elec

tro

stat

ic c

ntr

ol

SiON

poly

high k

metal

gate stack

planar 3D

65nm 45nm 32nm 22nm‘07 ‘09 ‘12

PDSOI

‘15

bulk

strain

ADD substrateengineering

ADD High µ material

MuGFETMuCFET

…

µ ?

elec

tro

stat

ic c

ntr

ol

SiON

poly

SiON

poly

high k

metal

high k

metal

gate stack

planar 3D

ther

mal

µ+

dimension critique

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