€¦ · dissipation with respect to the other state-of-the-art ternary and quaternary circuits. 1...

www.ietdl.org

IE

d

Published in IET Computers & Digital TechniquesReceived on 25th May 2011Revised on 20th March 2013Accepted on 16th April 2013doi: 10.1049/iet-cdt.2013.0023

T Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp. 167–181oi: 10.1049/iet-cdt.2013.0023

ISSN 1751-8601

A universal method for designing low-power carbonnanotube FET-based multiple-valued logic circuitsMohammad Hossein Moaiyeri1,2, Reza Faghih Mirzaee2, Akbar Doostaregan2, Keivan Navi1,3,

Omid Hashemipour1

1Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran2Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, GC, Tehran, Iran3Department of Electrical Engineering and Computer Science, University of California, Irvine, CA, USA

E-mail: [email protected]

Abstract: This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotubefield effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFETdevice such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as wellas the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designinghigh-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOSarchitecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includesall the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in thisstudy is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without staticpower dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology,demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static powerdissipation with respect to the other state-of-the-art ternary and quaternary circuits.

1 Introduction

Complementary metal oxide semiconductor (CMOS) hasbeen the predominant technology of the past two decadesproviding the required dimension scaling for implementingenergy-efficient and high-density very large scaleintegration (VLSI) circuits and systems. The majority ofessential applications such as financing, telecommunication,education and even medical care are dependent on CMOStechnology. Nevertheless, by the unavoidable scaling downof the feature size of the metal oxide semiconductor (MOS)transistor deeper in nanoscale, the CMOS technology facesmany critical challenges and difficulties. Problems such asvery high leakage currents, high power density, largeparametric variations and decreased gate control hinder thesuccessive dimension scaling of the CMOS technology andreduce its suitability for the near future low-power,high-performance and high-density applications.To overpower these challenges and difficulties, some

beyond-CMOS nanodevices such as carbon nanotube fieldeffect transistor (CNTFET), quantum-dot cellular automata(QCA) and single electron technology (SET) have beenintroduced to possibly replace the conventional bulk-CMOStechnology in the near future [1–3]. These nanodevicesbenefit from low-power consumption, ballistic transportattributes under low supply voltages and very small sizesthat make them very suitable for ultra-low-power,ultra-high-performance and ultra-high-density chip design.

Nevertheless, considering these nanotechnologies, CNTFETcan be more applicable because of its similarities toMOSFET in terms of inherent electronic characteristics. Onaccount of this similarity, previously designed structuresbased on CMOS platforms can still be utilised in CNTFETtechnology without any significant modifications. Theremarkable one-dimensional band-structure of the CNTFETdevice represses backscattering and brings about ballistictransport characteristics, which leads to very high-speedoperation [4]. In addition, CNTFET generally has thebenefit of a much more high-performance operation, lowerpower consumption, very high carrier velocity and highertransconductance, in comparison with the MOS transistors.Many CNTFET-based circuits such as full adders [5] and

multiple-valued logic (MVL) and arithmetic circuits [2,6–9] have already been presented in the literature. However,the multiple-valued logic circuits could be of more interestin the CNTFET nanotechnology. This is due to the fact thatthe most suitable and prevalent method for designingvoltage-mode MVL circuits is the multiple-threshold(multiple-Vth) design technique and the desired thresholdvoltage can be acquired by adopting correct diameters forthe nanotubes of the CNTFET device [2, 6–9].Unlike the binary logic, in MVL systems there are more

than two authorised logic levels and logical and arithmeticoperations can be performed on more than two logic values.As a result, in MVL many logical and arithmetic operationscould be executed with higher speed and smaller number of

167& The Institution of Engineering and Technology 2013

Fig. 1 Structure of a MOSFET-like CNTFET

www.ietdl.org
computation stages [8]. The main challenges of the binarylogic in designing large and dense chips are theinterconnections and pin-out problems that restrict thenumber of connections inside and outside of the circuits.By utilising MVL, wires convey more information, whichleads to savings in the number of interconnections and inthe insulation between them, and also pins carry moreinformation that results in saving in the number of pins[10]. In addition, MVL storage permits storing moreinformation per memory cell. Moreover, many real lifeapplications, such as robotics, process control and decisionsystems can be implemented more efficiently by usingMVL systems. Using MVL systems results in chips withmore density, smaller area, less complexity and veryhigh-bandwidth parallel and serial data transfer. MVL canbe even used to solve the binary problems more efficiently.For instance, the third logic value for testing the binarycircuits can be used as a medium for signaling the faultyoperation [11].In spite of these great advantages, from the implementation
point of view, MVL designs must be compatible with theexisting binary technologies. Several high-performanceMVL circuits have already been proposed in the literaturethat considerably enhanced this area of research [2, 6–9,12]. However, the common major problem of all thesedesigns is their high static power dissipation which is evenhigher than the other power components specifically atnanoscale. In general, the total power consumption isclassified into four components, that is, dynamic, shortcircuit, static and leakage power consumptions and can becalculated by (1) [13]

Ptotal = Pdynamic + Pshort-circuit + Pleakage + Pstatic

= VDD fclk∑i

Vswing, i × Cload, i × ai

( )(

+∑i

Ishort-circuit, i+∑i

Ileakage, i+∑i

Istatic, i

)(1)

where VDD is the power supply voltage, fclk is the systemclock frequency, Vswing,i is the voltage swing of the node i,Cload,i is the load capacitance at node i, αi is the switchingactivity factor at node i, and Ishort-circuit,i, Istatic,i and Ileakage,iare the short-circuit, static and leakage currents, respectively.The static power, which is caused by the DC currents and

is consumed through the paths from VDD to GND duringthe stable states of the circuits, is a significant consumedpower in MVL circuits, specifically at nanoranges [2].This problem considerably restricts the suitability ofthe previously presented MVL circuits for low-powerapplications, specifically for portable battery-poweredsystems [13].In this paper, a universal method for designing MVL

circuits with no static power dissipation is proposed fornanoelectronics in which the paths from VDD to ground(GND) are eliminated in the static state of the circuits. Thisleads to considerably lower power consumption and energyefficiency.In the rest of this paper, Sections 2 and 3 review the

CNTFET technology and MVL design, respectively. Thenew low-power CNTFET-based MVL circuits are proposedin Section 4. Section 5 contains the simulation results andcomparisons and finally, Section 6 concludes this paper.


2 A brief review of CNTFETs

Carbon nanotubes (CNTs) as rolled sheets of graphite can becategorised into single-walled CNTs (SWCNTs), composedof a single cylinder and multi-walled CNTs, composed ofmore than one cylinder [14]. The chirality vector of a CNTis specified by the (n, m) pair, called chiral number. Thispair indeed determines the formation angle of the carbonatoms along the nanotube. If n –m≠ 3k (k [ Z) theSWCNT is semiconductor, otherwise it is conductor [4].Semiconducting SWCNTs can be used as the channel ofthe CNTFET device. In addition to the uniquecharacteristics of the CNT material, removing the channelof the transistor from the silicon bulk leads to removal andreduction of many parasitic elements. Moreover, unlike theMOSFET devices, P- and N-type CNTFETs have the samemobility (μn = μp) and as a result same drive currents. Thisunique feature of the CNTFET device is very consequentialfor simplifying the design and transistor sizing proceduresof complex CNTFET-based circuits [15]. The other greatadvantage of the CNTFET nanodevice compared with thenanoscale MOSFET is that its I–V characteristics are similarto well-tempered classic MOSFET devices.Three different types of CNTFETs have already been

introduced in the literature, that is, SB-CNTFET,T-CNTFET and MOSFET-like CNTFET [16]. However,considering these types of CNTFETs, MOSFET-likeCNTFET is more suitable for circuit design based on theCMOS architectures, because of more similarity withMOSFET in terms of device structure and inherentcharacteristics. In addition, the main advantage ofMOSFET-like CNTFET is that its source/drain (S/D)-channel junctions have no Schottky barrier, and as aresult, it has considerably higher ON current andconsequently is very suitable for ultra-high-performanceapplications. The structure of a MOSFET-like CNTFET isillustrated in Fig. 1.A CNTFET has threshold voltage (Vth), similar to a

MOSFET, which is the voltage needed for turning on thedevice electrostatically through the gate. Another uniqueproperty of the CNTFET device is that the desired thresholdvoltage can be determined for a CNTFET by adopting aproper diameter for its CNTs. This is due to the fact thatthe bandgap of a CNT, which is a measure of the CNTFETthreshold voltage, is directly dependent to its diameter. Thispractical attribute makes CNTFET more flexible thanMOSFET and makes it very suitable for designing

IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp. 167–181doi: 10.1049/iet-cdt.2013.0023

www.ietdl.org
voltage-mode MVL circuits. The threshold voltage of aCNTFET is nearly considered as the half bandgap and iscalculated by (2) [17]
Vth ≃Ebg

2e= a0Vp

eDCNT≃ 0.436

DCNT(nm)(2)

where Ebg is the CNT bandgap, e is the unit electron charge,a0 (≃0.144 nm) is the carbon-to-carbon bond length in aCNT, Vπ (≃3.033 eV) is the carbon π–π bond energy in thetight bonding model and DCNT is the diameter of thenanotubes. It can be inferred from (2) that the thresholdvoltage of a CNTFET is inversely proportional to thediameter of its nanotubes, which is calculated by (3) [17]

DCNT =��3

√a0

��n2 + nm+ m2

√

p≃ 0.0783

��n2 + nm+ m2

√(3)

Besides the unique advantages of the CNTFET device, thisemerging nanotechnology faces some challenges in terms ofVLSI-compatible mass production, based on the currentfabrication technologies, such as high-resistance CNT-metalcontacts, misaligned and mispositioned CNTs, metallicchannel CNTs and relatively high fabrication costs.However, promising efforts are being made to overcomethese physical challenges in the recent years. In [18], aneffective method has been proposed for considerablyreducing the CNT-metal resistance by utilising a graphiticinterfacial layer between CNT and metal. In addition, asynthesis procedure for manufacturing SWCNTs withspecific (n, m) chirality numbers has been presented in[19]. Post-processing methods to set the desired thresholdvoltage of multitube CNTFETs has been presented in [20].In addition, in [21, 22], fabrication of imperfection-immuneVLSI-compatible sequential and combinational CNTFETlogic circuits has been presented. These logic circuits, suchas D-latches and half-adder sum generators, are the basicbuilding blocks of VLSI digital systems. Furthermore,chemical doping of CNTs to fabricate and integrate N- andP-type CNTFETs on the same substrate is an important areaof the future research in order to obtain complementaryVLSI CNTFET-based circuits [22].

3 A brief review of MVL design

Let us consider an m-valued function F(X) with k variables,where X = {x1, x2, x3, …, xk} and each xi can adopt valuesfrom M = {0, 1, 2, …, m − 1}. Therefore the function F(X)

is a mapping f :Mk→M and consequently there are mmk

different functions possible in the set f.

Table 1 Truth table of the ternary basic logical functions

a1 a2 NTI, a1 STI, a1 PTI, a1 NTNAND

0 0 2 2 2 20 1 2 2 2 20 2 2 2 2 21 0 0 1 2 21 1 0 1 2 01 2 0 1 2 02 0 0 0 0 22 1 0 0 0 02 2 0 0 0 0


However, among these possible functions, NOT, NANDand NOR operations seem to be more important as they arethe building blocks of many other complex logical andarithmetic circuits. These fundamental logical functions canbe defined in an m-valued k-variable system according to(4), (5) and (6)

NOT(a) = m− 1− a (4)

NAND a1, a2, ..., ak( ) = m− 1−min a1, a2, ..., ak

( )(5)

NOR a1, a2, ..., ak( ) = m− 1−max a1, a2, ..., ak

( )(6)

The ternary logic is a common MVL, which includes threesignificant logic levels. These logic levels can be consideredas ‘0’, ‘1’ and ‘2’ symbols, which are counterpart to 0,½ VDD and VDD voltage levels. Three different types oflogics are defined for the ternary logic, that is, negative,standard and positive such as negative ternary inverter(NTI), standard ternary inverter (STI) and positive ternaryinverter (PTI) [11]. Table 1 demonstrates the truth table ofthe basic logical functions of the ternary logic.Similar to the ternary logic, the basic logical functions of

the quaternary and penternary (five-valued) systems canalso be defined according to (5–7). The quaternary logicincludes four ‘0’, ‘1’, ‘2’ and ‘3’ logic symbols, which arecommonly counterpart to 0, ⅓VDD, ⅔VDD and VDD voltagelevels. In addition, the penternary logic comprises five ‘0’,‘1’, ‘2’, ‘3’ and ‘4’ logic symbols, which are commonlyequivalent to 0, ¼VDD, ½VDD, ¾VDD and VDD voltage levels.Several types of CMOS-based MVL circuits have already

been proposed in the literature as the emerging of MOSFETtechnology [12], [23–33]. However, they suffer from manydrawbacks which make them unsuitable for the current andthe upcoming technologies. For instance, designs of [12],[23–26] dissipate high static power, designs of [23] and[24] require large off-chip resistors, designs of [23–25],[27] and [28] utilise multiple supply voltages and designsof [26–30] use depletion-mode MOSFETs that havebecome obsolete.In addition, some new structures for CMOS analog inverter

have already been proposed, which could be considered asinverters for any arbitrary radix, including the ternary andquaternary logics [30–33]. However, because of theinability of the analogue inverter to restore the outputvoltage levels and the absence of noise immunity, ananalog inverter cannot truly be used as a classical MVLinverter.In the recent years, some state-of-the-art CNTFET-based

MVL circuits have been proposed in the literature. SomeCNTFET-based ternary logic circuits have been proposed in

STNAND PTNAND NTNOR STNOR PTNOR

2 2 2 2 22 2 0 1 22 2 0 0 02 2 0 1 21 2 0 1 21 2 0 0 02 2 0 0 01 2 0 0 00 0 0 0 0


www.ietdl.org
[7]. Despite the advantages of utilising CNTFET transistors,they use large ohmic resistors that are difficult to beimplemented on-chip and integrated with CNTFETs andalso lead to area wastage and performance degradation. Toovercome the above-mentioned difficulties, other ternarylogical and arithmetic circuits have been proposed in [4]and [8] in which P-CNTFET active loads have been utilisedinstead of large ohmic resistors. This technique leads to abetter integration, higher performance, less area overheadand larger noise margins, in comparison with theconventional CNTFET-based ternary circuits of [7].Recently, state-of-the-art CNTFET-based ternary logicaland arithmetic circuits has also been proposed in [2], whichinclude all the possible ternary logics, that is, negative,standard and positive, in one structure and outperform thepreviously proposed CMOS and CNTFET designs in termsof performance, power consumption and robustness. Inaddition to ternary logic, in [34], high-performanceCNTFET-based circuits have been introduced forquaternary logic, which has tried to solve the problems ofthe previous MOSFET-based quaternary designs.Nevertheless, all of the above-mentioned state-of-the-art
MVL circuits [2, 4, 7, 8, 34] also suffer from static powerconsumption. Indeed, a considerable amount of theiraverage power consumption is the static power consumption[2], which restricts their suitability for ultra-low-powerapplications [13, 16].

4 Proposed low-power CNTFET-basedMVL circuits

4.1 Fundamentals of the proposed method

The basic schema of the proposed technique is shown inFig. 2a, which is based on PTI and NTI gates. The outputs

Fig. 2 Basic schema of the proposed technique

a Basic schema of the proposed ideab Before applying ΔVP voltagec After applying ΔVP voltaged Final schema equivalent circuit after applying ΔVP voltage


of the PTI and NTI gates are connected together by meansof two capacitors that make a weighting sum of their inputs[35]. The voltage of the connection node of the capacitorsis calculated as follows

VSTI =CNVN + CPVP

CN + CP(7)

It is notable that in (7), the input capacitance of the next stagecapacitance load (CL), which is composed of very smallcapacitors of the next stage CNTFETs, is ignored for thesimplicity of calculation.By utilising identical capacitances for CP and CN, same

weighting factors are obtained. As a result, the outputvoltage of the capacitors is calculated according to (8)

VSTI =VN + VP

2(8)

Based on (8), the output voltage of STI will be the mean valueof the output voltages of NTI and PTI. Therefore if the inputvoltage becomes VDD, the output voltages of NTI and PTIwill be equal to 0 V and as a result the voltage of STI willalso be equal to 0 V. If the input voltage becomes 0 V, theoutput voltages of NTI and PTI will be VDD and thereforethe voltage of STI will also be VDD. Finally, if the inputvoltage becomes ½VDD, the output voltage of NTI will beequal to 0 V and the output voltage of PTI will be VDD andconsequently according to (9) the voltage of STI will beequal to ½VDD. The considerable advantage of thisproposed method is the absence of static power dissipation,because there is no path from VDD to the ground and


www.ietdl.org
consequently no DC current flows, while the circuit operatesin the static mode.In the proposed idea, the capacitors perform voltage
division by charging and discharging the electrical load.Therefore it may be conceived that the residue charges mayaffect the output voltage, when inputs change. Someconvincing surveys have been carried out throughmathematical equations and simulations to investigate theauthenticity of the capacitance voltage divider.Fig. 2b demonstrates the capacitance divider (considering

the output CL), with its input voltages taken apart from thecapacitors and are shown separately as the voltage sources.Writing a Kirchhoff’s voltage law (KVL) relation on thecircuit of Fig. 2b results in (9)

VCP, 0+ VInP, 0

= VCN, 0+ VInN, 0

= VCL, 0(9)

Fig. 3 Proposed CNTFET-based ternary logic circuits

a Ternary inverterb Ternary bufferc Ternary NANDd Ternary NOR


By applying a differential voltage ΔVP on one of the inputs, asdemonstrated in Fig. 2c, the capacitors of Fig. 2b will berecharged while satisfying (10)

QP = QN + QL (10)

Writing a KVL relation on the circuit of Fig. 2c results in (11)

DVP + VCP, 0+ VInP, 0

− QP

CP= VCN, 0

+ VInN, 0+ QN

CN

= VCL, 0+ QL

CL(11)

By considering (9) and (11), the following equation is


www.ietdl.org
obtained, which is equivalent to Fig. 2d
DVP − QP

CP= QN

CN= QL

CL(12)

Finally, (13) is achieved from the series capacitors that provesthe correct functionality of the divider

DVSTI =CPDVP

CP + CN + CL(13)

4.2 Proposed CNTFET-based MVL circuits

Based on Table 1, the basic schema of Fig. 2a, and thecomplementary CNTFET design method, a novelCNTFET-based ternary inverter circuit is proposed, whichis demonstrated in Fig. 3a. The transition regions of PTIand NTI of the proposed ternary inverter are set byadopting proper threshold voltages for CNTFETs that aredetermined by the diameter of the CNTs [2, 4, 6–8].Transition points can also be set by adopting proper numberof nanotubes (N ) for the CNTFETs. Based on (2) and (3),for the CNTFETs of the proposed ternary circuits with thediameters of 0.783 and 1.487 nm, the chiral numbers wouldbe (10, 0) and (19, 0) and the threshold voltage values(|Vth|) would be 0.557 and 0.293 V, respectively. As aresult, high-Vt N-type and low-Vth P-type CNTFETs areutilised for implementing PTI and low-Vth N-type andhigh-Vth P-type CNTFETs are used for implementing NTI.According to (8), the STI signal is generated based on thePTI and NTI signals by a voltage division.

Fig. 4 Proposed CNTFET-based 3-input ternary logic circuits

a 3-input STNANDb 3-input STNOR


The capacitor network of the basic idea is implemented byutilising CNTFET capacitors [36]. One plate of a CNTFETcapacitor is the gate and the other plate is the source–drain–substrate junction. The capacitance of a CNTFET capacitorcan be expressed by (14)

CCNTFET = NCCNT + Cgate (14)

where N is the number of nanotubes under the gate, CCNT isthe capacitance of one carbon nanotube in the CNTFETdevice and Cgate is the capacitance because of the gate sizein the CNTFET transistor. Therefore CCNTFET is nearlyproportional to N.The great advantage of the proposed ternary inverter is that

there is no path from VDD to GND and no DC current duringits stable states and consequently it has zero static powerdissipation.Based on the proposed method of design, a novel

CNTFET-based ternary buffer with no static power isproposed that is demonstrated in Fig. 3b. This ternarybuffer generates all the possible types of ternary signals inone structure and includes negative ternary buffer (NTB),standard ternary buffer (STB) and positive ternary buffer(PTB). The proposed ternary buffer gate is indeed a ternaryvoltage level restorer which can be utilised in larger ternarycircuits. Utilising the proposed ternary buffer instead of twocascaded ternary inverters, results in using two lessCNTFETs and also shorter critical path.Based on the functionalities presented in Table 1 as well as

the idea of Fig. 2a, new ternary NAND and NOR gates withno static power consumption are proposed, which are


Fig. 5 Proposed CNTFET-based quaternary and penternary logic circuits

a Quaternary inverterb Quaternary NANDc Quaternary NORd Penternary invertere Penternary NANDf Penternary NOR

www.ietdl.org

composed of CNTFET transistors and capacitors. Theproposed ternary NAND and NOR circuits are shown inFigs. 3c and d, respectively.

Fig. 6 Basic operation of the proposed MVL inverters

a Quaternary inverterb Penternary inverter


Unlike the previously proposed ternary gates such as [7, 8,12, 25], in all of the proposed ternary circuits allthe negative, standard and positive ternary logics are


Table 2 Characteristics of the used CNTFET model

Parameter Brief description Value

Lch physical channel length ≥10 nmLss the length of doped CNT source-side

extension region≥10 nm

Ldd the length of doped CNT drain-sideextension region

≥10 nm

Lgeff the scattering mean free path in theintrinsic CNT channel and S/D regions

100 nm

pitch the distance between the centres of twoneighbouring CNTs within the samedevice

20 nm

Leff the mean free path in p + /n + doped CNT ≥15 nmsub_pitch sub-lithographic (e.g. CNT gate width)

pitch≥4 nm

Kox the dielectric constant of high-k top gatedielectric material (HfO2)

16

T_ox the thickness of high-k top gate dielectricmaterial

4 nm

Ksub the dielectric constant of substrate (SiO2) 4Csub the coupling capacitance between the

channel region and the substrate (SiO2)40 aF/μm

Efi the Fermi level of the doped S/D tube 6 eVphi_M the work function of source/drain metal

contact4.6 eV

phi_S CNT work function 4.5 eV

Table 3 Simulation results of the ternary logic gates

Parameters Delay(×10−12 s)

Average powerconsumption(×10−7 W)

Energyconsumption(×10−18 J)

Standard ternary NOTsproposed STI 16.579 1.9392 3.2151STI of [2] 15.628 4.3190 6.7496STI of [7] 28.354 211.84 600.65STI of [8] 19.495 10.131 19.748STI of [25] 18.405 534.51 983.77Standard ternary buffersproposed STB 10.696 2.3781 2.5436STB of [2] 27.432 5.8422 16.036STB of [7] 31.426 194.66 611.76STB of [8] 30.727 12.191 37.458STB of [25] 34.371 575.44 1977.8Standard ternary NANDsproposedSTNAND

20.931 2.2739 4.7595

STNAND of [2] 19.890 3.4460 6.8539STNAND of [7] 77.848 234.31 1824.1STNAND of [8] 26.721 7.0751 18.906STNAND of [25] 23.979 453.97 1088.6Standard ternary NORsproposedSTNOR

19.807 1.8899 3.7433

STNOR of [2] 17.143 3.2401 5.5545STNOR of [7] 33.065 135.25 447.21STNOR of [8] 24.126 7.3595 17.755STNOR of [25] 31.419 286.82 901.15

www.ietdl.org
implemented in one structure, which leads to using lowernumber of transistors.In addition, in the proposed designs only two distinct
diameters are used, which results in simplicity of the designand better manufacturability compared with the otherstate-of-the-art ternary designs such as [2, 8] which requireCNTFETs with three different diameters.The proposed ternary 2-input NAND and NOR circuits can

also be extended to ternary NAND and NOR with more thantwo inputs by utilising negative and positive TNANDs andTNORs with more than two inputs. For instance, Fig. 4demonstrates the 3-input STNAND and STNOR that utilise3-input positive and negative NANDs and NORs with theCMOS style. For designing these ternary circuits also, onlytwo different CNT diameters are required.Another great advantage of the proposed idea is its

expandability for designing MVL circuits with any arbitrarynumber of logic levels such as quaternary logic. Based on(5–7) as well as the proposed universal method ofdesigning MVL circuits, novel CNTFET-based quaternarylogic gates are proposed. The proposed quaternary logicgates that are shown in Figs. 5a–c are designed based onsimple CNTFET-based basic logic gates with theconventional CMOS configurations. The transition points ofthe basic gates are set by adopting correct diameters for thechannels of the CNTFETs. It is notable that for designingthe proposed quaternary CNTFET-based circuits only threedifferent diameters are used for the nanotubes, whereas thisnumber of diameters has been used in the previous worksfor designing ternary logic circuits. For the CNTFETs ofthe proposed quaternary circuit with the diameters of 0.783,1.487 and 2.27 nm, the chirality numbers would be (10, 0),(19, 0) and (29, 0) and the threshold voltage values (|Vth|)would be almost 0.557, 0.293 and 0.192 V, respectively.The voltage transfer characteristics (VTCs) of the utilised

inherently binary inverters of the proposed QNOT areshown in Fig. 6a, as a case in point. According to Fig. 6a,the output voltage of QNOT is obtained based on (15) inwhich VOut1, VOut2 and VOut3 are the output voltages of theinverters of Fig. 5a

VQNOT = VOut1 + VOut2 + VOut3

3(15)

It is notable that the proposed quaternary logic circuits aredesigned based on the inherently binary inverters, while thepreviously proposed quaternary logic circuits such as [28,30] are limited to utilise depletion-type MOSFETs, whichhas become obsolete. Moreover, designs of [30] requirethree different supply voltages.Based on the proposed universal method of designing

MVL logic circuits, novel CNTFET-based penternary logicgates are also proposed, which are illustrated in Figs. 5d–f.It is worth mentioning that for designing the proposedpenternary CNTFET-based circuits only three differentdiameters for the nanotubes of the CNTFETs are used, allless than 3 nm, while this number of diameters has beenused in the previously presented works for designingternary logic circuits. For the CNTFETs of the proposedpenternary logic circuits with the diameters of 0.783, 1.096and 2.975 nm the chirality numbers would be (10, 0), (14,0) and (38, 0), respectively, and consequently the thresholdvoltage values (|Vth|) are about 0.557, 0.392 and 0.144 V,respectively. The VTCs of the utilised inherently binaryinverters of the proposed PNOT are shown in Fig. 6b. Theoutput voltage of PNOT is calculated according to (16) in


which VOut1, VOut2, VOut3 and VOut4 are the output voltagesof the inverters of Fig. 5d

VPNOT = VOut1 + VOut2 + VOut3 + VOut4

4(16)

To the best of our knowledge, this is the first time that thebasic penternary logic gates are proposed fornanoelectronics. In addition, for designing the proposedquaternary and penternary circuits only three different CNTdiameters, all less than 3 nm, has been used, while thisnumber of diameters has been used for designing ternarylogic circuits in the previous works.


www.ietdl.org
Further, in addition to the absence of static power
dissipation, by increasing the number of logic levels in theproposed method of design, the critical paths of the circuitsremain unchanged.It is notable that although multi-Vth nano-MOSFETs are

available, they cannot be used to implement the proposedmethod with Lch = 32 nm at 32 nm technology node,because of the very low gain of the nano-MOSFET-basedbinary inverters, in the transition region, compared withtheir CNTFET-based counterparts [15], which is notsufficient for this application. As illustrated in Fig. 6, thegain of the input binary inverters is a very determiningfactor for correct functionality, robustness and precision ofthe proposed MVL designs. In order to increase the gain ofthe MOSFET binary inverters sufficiently, the channellength of the MOSFETs should increase considerably whichleads to significant speed degradation and area wastage.However, the gain of the CMOS binary inverters is stilllower than their CNTFET counterparts [34].Moreover, although on-chip capacitors are available in

MOSFET technology, including metal–insulator–metalcapacitor (MIMcap) and MOS capacitor (MOScap) [37],

Fig. 7 Transient response of the proposed ternary structures


MIMcap has very low density (fF/μm2), specifically in therecent technologies that low-k insulators are used forseparating the conducting parts, and MOScap suffers fromhigh non-linearity and is not suitable for MVL and analogdesign. However, another advantage of using CNTFETs inthe proposed method is the possibility of using high-kCNTFET capacitors.

5 Simulation results, analysis andcomparison

In this section, the proposed MVL logic circuits are examinedin various conditions, using Synopsys HSPICE simulatorwith the Compact simulation program with integratedcircuit emphasis (SPICE) Model for 32 nm CNTFET (Lch =32 nm), including all the possible non-idealities [38–40].This standard model has been designed for unipolarenhancement-mode MOSFET-like CNTFET devices inwhich each transistor may include one or more CNTsas its channel. This model also considers a realistic,circuit-compatible CNTFET structure and includes practical


Fig. 8 Power and energy consumption of the ternary circuits in the presence of process variations

www.ietdl.org

176 IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp. 167–181& The Institution of Engineering and Technology 2013 doi: 10.1049/iet-cdt.2013.0023

Table 4 Simulation results of the proposed quaternary andpenternary logic circuits

VDD, V 0.8 V 0.9 V 1 V

Standard quaternary logic gatesdelay ( × 10− 12 s)proposed QNOT 24.136 19.067 16.912QNOT of [34] 4.4315 3.0603 2.9412proposed QNAND 36.321 24.552 17.925QMIN of [34] 8.9671 7.0831 7.5787proposed QNOR 35.151 26.527 25.330QMAX of [34] 7.5766 7.0552 7.1490Power consumption ( × 10− 6 W)proposed QNOT 0.4593 1.3579 3.3217QNOT of [34] 18.339 24.306 31.588proposed QNAND 0.5169 1.6775 3.7860QMIN of [34] 20.668 27.381 35.507proposed QNOR 0.5430 1.5531 3.5827QMAX of [34] 20.677 27.398 35.550Energy consumption ( × 10− 17 J)proposed QNOT 1.1086 2.5892 5.6176QNOT of [34] 8.1271 7.4381 9.2911proposed QNAND 1.8776 3.7961 6.7864QMIN of [34] 18.533 19.394 26.909proposed QNOR 1.9088 4.4500 9.0751QMAX of [34] 15.665 19.329 25.414Standard penternary logic gatesdelay ( × 10− 12 s)proposed PNOT 108.03 65.126 42.353proposed PNAND 202.33 97.235 45.498proposed PNOR 199.96 97.974 61.760Power consumption ( × 10− 6 W)proposed PNOT 0.8876 1.9560 4.3874proposed PNAND 0.9743 2.1664 4.9039proposed PNOR 0.9361 2.0793 4.7132Energy consumption ( × 10− 17 J)proposed PNOT 9.5891 12.739 18.582proposed PNAND 19.714 21.065 22.312proposed PNOR 18.719 20.372 29.109

www.ietdl.org
device non-idealities, parasitics, Schottky barrier effects at thecontacts, inter-CNT charge screening effects, doped source–drain extension regions, scattering (non-ideal near-ballistictransport), back-gate (substrate bias) effect and source/drainand gate resistances and capacitances. The model alsoincludes a full transcapacitance network for more accuratetransient and dynamic performance simulations. Theparameters of the CNTFET model and their values, withbrief descriptions, are listed in Table 2.For testing the ternary inverters and buffers, all the 2→ 1,
1→ 0, 0→ 1, 1→ 2, 2→ 0 and 0→ 2 transitions areconsidered. For testing the two-input ternary circuits, acomplete input pattern with all the 81 possible transitionsfrom an input combination to another is fed to the circuits.In addition, the quaternary and penternary logic circuits aresimulated based on the input pattern presented in [28]. Thedelay of all transitions from one-input to another aremeasured and the maximum obtained value is reported asthe propagation delay of each circuit.To measure the average power consumption accurately and

to prevent underestimation, all the possible inputcombinations for measuring the average power consumptionof the circuits are considered. This guarantees that themeasured average power consumption is an accuratereading of the power consumption of the circuit [41]. Inorder to make a compromise between the powerconsumption and the delay of the circuits, the performanceof the circuits can be evaluated by measuring the averageenergy consumption, which is defined as the multiplicationof the average power consumption and the maximum delay.Therefore the energy consumption could be a significantparameter for evaluating the performance of the circuits [42].Each ternary circuit is simulated by considering a ternary

FO4, composed of four ternary inverters of the same logicstyle of that circuit, at its output load. The simulationresults, including the worst-case delay, the average powerconsumption and the average energy consumption, are alsolisted in Table 3 for 0.9 V supply voltage, which is thestandard voltage for 32 nm technology node and the bestresults at each voltage are demonstrated in bold.According to the contents of Table 3, designs presented in

[7] have considerably lower performance and higher powerconsumption, because of utilising large ohmic resistors andtheir high static power dissipation, while their outputs arearound ½VDD and 0 V. Moreover, the proposed ternarycircuits outperform the other designs in terms of powerconsumption and energy efficiency, mostly because of theelimination of static power dissipation, which will bediscussed later.Moreover, the transient response of the proposed ternary

structures are shown in Fig. 7 in which restoring the voltagelevels of non-full-swing input signals at the outputs of theSTI and STB circuits is clearly demonstrated.As the proposed CNTFET-based MVL circuits are

designed based on the multiple-Vth method, the impact ofthe process variations on the threshold voltages of theCNTFETs should definitely be examined. The mostimportant parameters that determine the threshold voltagevalue of a CNTFET are the diameter of its nanotubes andthe thickness of its gate oxide layer (T_ox). In addition, asthe proposed MVL circuits are designed for low-powerapplications, after checking their correct operation, the mostsignificant parameter, which should be evaluated in thepresence of process variations, is the average powerconsumption. Moreover, for evaluating the performance ofthe circuits in the presence of process variations, the


average energy consumption variation can also bemeasured. Here on, Monte-Carlo transient analysis with areasonable number of 30 iterations per simulation is carriedout using the HSPICE simulator. Furthermore on eachiteration, the calculation is repeated 10 times and the largestdeviation is saved as the result of that iteration. Thestatistical significance of 30 iterations is very high. If acircuit operates correctly for all the 30 iterations, there is a99% probability that over 80% of all the possiblecomponent values operate properly. It is notable that thedistribution of the diameter and T_ox is assumed asGaussian with 8-sigma distribution [43, 44]. The meanvalues for the diameters are set to the values demonstratedin Fig. 3 and the mean value of T_ox of all CNTFETs isset to 4 nm. Considering the impreciseness of fabricationtechniques, a standard deviation from the mean in the rangeof 0.04 to 0.2 nm is taken into account for each meandiameter value [45]. Furthermore, the value of T_ox isdeviated up to 50% of its mean value.The simulation results of STIs and STNORs as examples of

the one-input and two-input ternary logic circuits are shownin Fig. 8. It can be inferred from the results that the powerand energy consumption of the proposed CNTFET-basedternary logic circuits are less sensitive to the parametricvariations, compared with the state-of-the-art designs of[2] and [8], specifically for the larger parametric deviations.As stated before, while the previous state-of-the-artCNTFET-based designs required three different CNTdiameters, the number of required CNTFET diameters in


Fig. 9 Transient response of the proposed MVL circuits

a Quaternary logicb Penternary logic

www.ietdl.org

the proposed ternary designs is only two, which enhancestheir robustness and manufacturability.Another aspect of the process variations, which should be

taken into consideration in the proposed MVL structures, isthe possible mismatch between the capacitors, mainlycaused by the possible difference between the numbers ofthe nanotubes under the gate of the CNTFET capacitors.The simulation results prove the correct operation of theproposed circuits and its 25% maximum variation in theenergy consumption, when up to 35% difference betweenthe numbers of CNTs of the CNTFET capacitors is takeninto account for testing the proposed ternary circuits.The proposed quaternary and penternary circuits, designed

based on the proposed universal method, are also simulated at


1, 0.9 and 0.8 V power supply voltages. The simulationresults of these designs are listed in Table 4 which indicatesthe low-power operation and energy efficiency of the novelproposed quaternary and penternary logic circuits.The proposed quaternary logic circuits are also compared

with the state-of-the-art high-performance CNTFET-baseddesigns previously proposed in the literature [34]. The otherquaternary and penternary logic circuits, as stated inSection 3, have been designed based on depletiontransistors that have become obsolete and are not applicablein the recent nanoscale technologies. According to theresults, the proposed quaternary logic circuits considerablyoutperform the design of [34] in terms of average powerconsumption and energy efficiency, especially at lower


Table 5 Average static power consumption (including leakage)of the MVL circuits

Ternary designs ( × 10− 8 W)

proposed STI 1.195STI of [2] 5.769STI of [8] 14.46average improvement 88.55%proposed STB 1.218STB of [2] 11.03STB of [8] 29.21average improvement 92.39%proposed STNAND 2.007STNAND of [2] 7.468STNAND of [8] 10.75average improvement 77.22%Proposed STNOR 1.641STNOR of [2] 5.236STNOR of [8] 11.12average improvement 76.95%Quaternary designs ( × 10− 6 W)proposed QNOT 1.3476QNOT of [34] 21.615improvement 93.76%proposed QNAND 1.5677QMIN of [34] 28.665improvement 94.53%proposed QNOR 1.6627QMAX of [34] 29.582improvement 94.37%Penternary designs ( × 10− 6 W)proposed PNOT 1.8853proposed PNAND 2.1340proposed PNOR 2.0101

www.ietdl.org

voltages. As predicted before, the resistive voltage divided inthe designs of [34] leads to high static power consumption.However, because of the absence of any static paths fromVDD to GND in the proposed designs, no static power isdissipated and the power consumption is reducedconsiderably.In addition, the results of the transient analysis of the

proposed quaternary and penternary designs at 0.9 V, whichauthenticate the correct operation of the proposed MVLdesigns, are demonstrated in Figs. 9a and b, respectively.According to (1), the average power consumption is

generally composed of switching, short-circuit, static andleakage components. However in the recent and future

Fig. 10 Static current drawn from the power supply against input volta

a STB of [8]b STB of [2]c proposed STB


circuits, the static and leakage components are becomingvery important. Dissimilar to short-circuit and switchingpowers, static and leakage powers are consumed irrelevantto the switching activity of the circuit. Therefore to measurethe static power, the circuits should be exhaustively testedin stand-by mode for all the possible input combinations[46]. Therefore constant inputs should be fed into thecircuits to prevent switching activity at the end nodes aswell as the intermediate nodes of the circuits. All thepossible input combinations should be fed separately intothe circuits and the obtained power would be the sum ofstatic and the leakage powers. The average static powers ofthe circuits are measured at 0.9 V power supply voltage andare reported in Table 5. According to the results, theproposed method improves the average static power ofternary and quaternary logic circuits by more than 82and 94%, respectively, compared with the previousstate-of-the-art MVL circuits.It is notable that the previous designs have high static

power because of the high static currents flowing from VDD

to GND during their stable states, as a result of resistivevoltage dividing. Moreover, designs of [2] have lower staticpower consumption compared with designs of [8], becauseof existing auto body biasing in the circuits of [2] duringthe stable state that the output voltage is ½VDD. In addition,according to the results, the proposed MVL designs haveextremely lower static power consumption compared withthe other designs, due to the fact that unlike the otherdesigns, there is no path from VDD to GND during thestable states of the proposed circuits.For example, the static current drawn from the power

supply of each of the CNTFET-based standard ternarybuffers, against the input voltage, is illustrated in Fig. 10.According to Fig. 10, the proposed design (Fig. 3b) hasmuch lower static current specifically when the inputvoltage is around ½VDD.

6 Conclusion

Novel low-power and high-performance MVL circuits havebeen proposed for nanoelectronics based on the CNTFETdevices. The proposed CNTFET-based circuits have beendesigned with a universal method for designing MVLcircuits based on multi-Vth nanodevices and have benefited

ge


www.ietdl.org
from the unique properties of CNTFET. The proposed MVLcircuits have simple structures and are designed based on theconventional CMOS architecture by utilising inherentlybinary gates. For designing the proposed circuits, threedifferent CNT diameters, all less than 3 nm, have beenused, which improves the feasibility and manufacturabilityof the designs. To the best of our knowledge this is the firsttime in the open literature that penternary logic circuitshave been proposed for nanoelectronics. The simulationresults confirm the authenticity of the proposed method aswell as the superiority of the proposed ternary circuitsspecifically in terms of the static power dissipation incomparison with the other state-of-the-art ternary circuits.
7 Acknowledgment

The authors would like to thank Dr. Belmond Yoberd for hisliterature contribution.

8 References

1 Kim, Y.-B.: ‘Challenges for nanoscale MOSFETs and emergingnanoelectronics’, Trans. Electr. Electron. Mater., 2010, 11, (3), pp.93–105

2 Moaiyeri, M.H., Doostaregan, A., Navi, K.: ‘Design of energy-efficientand robust ternary circuits for nanotechnology’, IET Circuits DevicesSyst., 2011, 5, (4), pp. 285–296

3 Tehrani, M.A., Safaei, F., Moaiyeri, M.H., Navi, K.: ‘Design andimplementation of multi-stage interconnection networks usingquantum-dot cellular automata’, Microelectron. J., 2011, 42, (6), pp.913–922

4 Lin, S., Kim, Y.-B, Lombardi, F.: ‘A novel CNTFET based ternary logicgate design’. Proc. IEEE Int. Midwest Symp. Circuits and Systems,Cancun, Mexico, August 2009, pp. 435–438

5 Navi, K., Rashtian, M., Khatir, A., Keshavarzian, P., Hashemipour, O.:‘High speed capacitor–inverter based carbon nanotube full adder’,Nanoscale Res. Lett., 2010, 5, (5), pp. 859–862

6 Keshavarzian, P., Navi, K.: ‘Efficient carbon nanotube galois fieldcircuit design’, IEICE Electron. Express, 2009, 6, (9), pp. 546–552

7 Raychowdhury, A., Roy, K.: ‘Carbon-nanotube-based voltage-modemultiple-valued logic design’, IEEE Trans. Nanotechnol., 2005, 4, (2),pp. 168–179

8 Lin, S., Kim, Y., Lombardi, F.: ‘CNTFET-based design of ternary logicgates and arithmetic circuits’, IEEE Trans. Nanotechnol., 2011, 10, (2),pp. 217–225

9 You, K., Nepal, K.: ‘Design of a ternary static memory cell using carbonnanotube-based transistors’, IET Micro Nano Lett., 2011, 6, (6),pp. 381–385

10 Dubrova, E.: ‘Multiple-valued logic in VLSI: challenges andopportunities’. Proc. NORCHIP Conf., Oslo, Norway, November1999, pp. 340–350

11 Serra, M.: ‘Applications of multi-valued logic to testing of binary andMVL circuits’, Int. J. Electron., 1987, 63, (2), pp. 197–214

12 Srivastava, A., Venkatapathy, K.: ‘Design and implementation of a lowpower ternary full adder’, VLSI Des., 1996, 4, (1), pp. 75–81

13 Radhakrishnan, D.: ‘Low-voltage low-power CMOS full adder’, IEEProc. Circuits Devices Syst., 2001, 148, (1), pp. 19–24

14 McEuen, P.L., Fuhrer, M., Park, H.: ‘Single-walled carbon nanotubeelectronics’, IEEE Trans. Nanotechnol., 2002, 1, (1), pp. 78–85

15 Cho, G., Kim, Y., Lombardi, F., Choi, M.: ‘Performance evaluation ofCNFET-based logic gates’. Proc. IEEE Int. Instrumentation andMeasurement Technology Conf., Singapore, May 2009, pp. 909–912

16 Raychowdhury, A., Roy, K.: ‘Carbon nanotube electronics: design ofhigh-performance and low-power digital circuits’, IEEE Trans.Circuits Syst., 2007, 54, (11), pp. 2391–2401

17 Bok, K.Y., Kim, Y.B., Lombardi, F.: ‘Novel design methodology tooptimize the speed and power of the CNTFET circuits’. Proc. IEEEInt. Midwest Symp. Circuits and Systems, Cancun, Mexico, August2009, pp. 1130–1133

18 Chai, Y., Hazeghi, A., Takei, K., et al.: ‘Low-resistance electricalcontact to carbon nanotubes with graphitic interfacial layer’, IEEETrans. Electron Devices, 2012, 59, (1), pp. 12–19

19 Wang, B., Poa, P., Wei, L., Li, L., Yang, Y., Chen, Y.: ‘(n,m) Selectivityof single-walled carbon nanotubes by different carbon precursors onCo–Mo catalysts’, J. Am. Chem. Soc., 2007, 129, (9), pp. 9014–9019


20 Lin, A., Patil, N., Ryu, K., et al.: ‘Threshold voltage and on-off ratiotuning for multiple-tube carbon nanotube FETs’, IEEE Trans.Nanotechnol., 2009, 8, (1), pp. 4–9

21 Zhang, J., Patil, N., Lin, A., Wong, H.-S.P., Mitra, S.: ‘Carbon nanotubecircuits: living with imperfections and variations’. Proc. Design,Automation & Test in Europe Conf. Exhibition (DATE), Dresden,Germany, March 2010, pp. 1159–1164

22 Patil, N., Lin, A., Zhang, J., et al.: ‘Scalable carbon nanotubecomputational and storage circuits immune to metallic andmispositioned carbon nanotubes’, IEEE Trans. Nanotechnol., 2011,10, (4), pp. 744–750

23 Mouftah, H.T., Jordan, I.B.: ‘Integrated circuits for ternary logic’. Proc.Int. Symp. Multiple Valued Logic, Morgantown, West Virginia, UnitedStates, May 1974, pp. 285–302

24 Mouftah, H.T., Smith, K.C.: ‘Injected voltage low-power CMOS for3-valued logic’, IEE Proc. G, 1982, 129, (6), pp. 270–272

25 Srivastava, A.: ‘Back gate bias method of threshold voltage control forthe design of low voltage CMOS ternary logic circuits’, Microelectron.Reliab. Elsevier, 2000, 40, (12), pp. 2107–2110

26 Vasundara, P.K.S., Gurumurthy, K.S.: ‘Quaternary CMOScombinational logic circuits’. Proc. IEEE Int. Conf. Information andMultimedia Technology, Jeju Island, South Korea, December 2009,pp. 538–542

27 Hueng, A., Mouftah, H.T.: ‘Depletion/enhancement CMOS for a lowpower family of three-valued logic circuits’, IEEE J. Solid-StateCircuits, 1985, 20, (2), pp. 609–616

28 Thoidis, I., Soudris, D., Karafyllidis, I., Christoforidis, S., Thanailakis,A.: ‘Quaternary voltage-mode CMOS circuits for multiple-valued logic’, IEE Proc. Circuits Devices Syst., 1998, 145, (2),pp. 71–77

29 Wang, P., Liu, Y., Yang, M., Almaini, A.E.A.: ‘Five-valued circuitquantitative theory and design of five-valued twisted-ring counter’.Proc. Sixth IEEE Int. Conf. ASIC, Shanghai, China, October 2005,vol. 1, pp. 304–308

30 Da Silva, R.C.G., Boudinov, H., Carro, L.: ‘A novel voltage-modeCMOS quaternary logic design’, IEEE Trans. Electron Devices, 2006,53, (6), pp. 1480–1483

31 Berg, Y., Næss, Ø., Aunet, S., Lomsdalen, I., Høvin, M.: ‘A novelfloating-gate binary signal to multiple-valued signal converter formultiple-valued CMOS logic’. Proc. IEEE Int. Conf. Electronics,Circuits and Systems, Dubrovnik, Croatia, September 2002, vol. 2,pp. 579–582

32 Berg, Y., Aunet, S., Mirmotahari, O., Høvin, M.: ‘Novel rechargesemi-floating-gate CMOS logic for multiple-valued systems’. Proc.IEEE Int. Symp. Circuits and Systems, Bangkok, Thailand, May2003, vol. 5, V-193–V-196

33 Gundersen, H., Berg, Y.: ‘Fast addition using balanced ternary countersdesigned with CMOS semi-floating gate devices’. Proc. Int. Symp.Multiple-valued Logic, Oslo, Norway, May 2007, p. 30

34 Moaiyeri, M.H., Navi, K., Hashemipour, O.: ‘Design and evaluation ofCNFET-based quaternary circuits’, Circuits Syst. Signal Process., 2012,31, (5), pp. 1631–1652

35 Doostaregan, A., Moaiyeri, M.H., Navi, K., Hashemipour, O.: ‘On thedesign of new low-power CMOS standard ternary logic gates’. Proc.15th CSI Int. Symp. Computer Architecture and Digital Systems,Tehran, Iran, September 2010, pp. 115–120

36 Kim, Y.B., Kim, Y.-B.: ‘High speed and low power transceiver designwith CNFET and CNT bundle interconnect’. IEEE Int. SOC Conf.,Las Vegas, NV, USA, September 2010, pp. 152–157

37 Danaie, M., Aminzadeh, H., Naseh, S.: ‘On the linearization ofMOSFET capacitors’. IEEE Int. Symp. Circuits and Systems, NewOrleans, USA, May 2007, pp. 1943–1946

38 Deng, J.: ‘Device modeling and circuit performance evaluation fornanoscale devices: silicon technology beyond 45 nm node andcarbon nanotube field effect transistors’. PhD thesis, StanfordUniversity, 2007

39 Deng, J., Wong, H.-S.P.: ‘ACompact SPICE model for carbon-nanotubefield-effect transistors including nonidealities and its application – part i:model of the intrinsic channel region’, IEEE Trans. Electron Devices,2007, 54, (12), pp. 3186–3194

40 Deng, J., Wong, H.-S.P.: ‘A compact SPICE model for carbon-nanotubefield-effect transistors including nonidealities and its application – partii: full device model and circuit performance benchmarking’, IEEETrans. Electron Devices, 2007, 54, (12), pp. 3195–3205

41 Shoarinejad, A., Ung, S.A., Badawy, W.: ‘Low power single bit fulladder cells’, Can. J. Electr. Comput. Eng., 2003, 28, (1), pp. 3–9

42 Navi, K., Moaiyeri, M.H., Faghih Mirzaee, R., Hashemipour, O.,Mazloom Nezhad, B.: ‘Two new low-power full adders based onmajority-not gates’, Microelectron. J., 2009, 40, (1), pp. 126–130


www.ietdl.org
43 El Shabrawy, K., Maharatna, K., Bagnall, D., Al-Hashimi, B.M.:
‘Modeling SWCNT bandgap and effective mass variation using aMonte-Carlo approach’, IEEE Trans. Nanotechnol., 2010, 9, (2),pp. 184–193

44 Lin, S., Kim, Y-B., Lombardi, F.: ‘Design and analysis of a 32 nm PVTtolerant CMOS SRAM cell for low leakage and high stability’, Integr.VLSI J., 2010, 43, (2), pp. 176–187


45 Shahidipour, H., Ahmadi, A., Maharatna, K.: ‘Effect of variability inSWCNT-based logic gates’. Proc. Int. Symp. Integrated Circuits,Singapore, December 2009, pp. 252–255

46 Moaiyeri, M.H., Faghih Mirzaee, R., Navi, K., Nikoubin, T.,Kavehei, O.: ‘Novel direct designs for 3-input XOR function forlow-power and high-speed applications’, Int. J. Electron., 2010, 97,(6), pp. 647–662


€¦ · dissipation with respect to the other state-of-the-art ternary and quaternary circuits. 1...

Documents