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Modeling of Cascde Modulated Power Ampliers
D S Tb Department of Electronic Systems, Aalborg Universit, 922 Aalborg, Denmark
E-mail: ds.tl@esaaudk
Abstct-Two model of he aode modulaed polar poweramplier (PA) are preened. The aode modulaed PA, haoperae a a wih mode amplier wih laE like oupunework, ha a highly nonlinear ranfer haraerii. Thepropoed empirial model i aed on modeling of he peak drainurren hrough he aode onneed ranior. A impliedanalyial model, ha ue mahemaial expreion o deriehe nonlinear ranfer haraerii of he aode modulaedPA, i propoed. The ehavior of he propoed aeand modeli ompared wih he F domain imulaion in a O.13/m MOSproe.
I NTRODUCTIONThe demand for high eciency and high linearit has driven
the power amplier (PA) research into continuously creating
new PA topologies Class-E PAs are capable of achieving
high eciency but they are highly nonlinear The switching
PAs can be linearized using a polar modulation scheme [].The cascode modulation concept published in [2] represents
one specic tpe of a polar PA The cascode modulated PA requires rther linearization to meet the stringent linearit
requirements of mode 3G and 4G wireless standards It is
shown in this paper that the nonlinea transfer characteristic
of the cascode modulated PA can be modeled by a baseband
transistor level model
Various approaches to PA modeling exist Some models provide a mathematical description and design equations for
a particular PA [3]. Other models incoorate various nonidealities (eg device parasitics) and investigate their eect on
the PA performance [4]. Behavioral models represent another
large model family that includes for example polynomial,
Voltea and neural networks based models [5].In this paper two models, the empirical and analytical
model, of the cascode modulated PA are proposed The
proposed models track the AM-AM PA characteristic of the
cascode modulated PA It is shown that by using a baseband
circuit, that is built on a replica circuit of the PA, it
is possible to reproduce the AM-AM characteristic of the
PA The empirical model is a baseband transistor level model of the cascode modulated PA The analytical model
provides a mathematical description of the nonlinear transfer
characteristic of the cascode modulated PA
II MPIRICAL MODEL OF A CASCODE MODULATED PA
The concept of a cascode modulated PA was introduced in[6]. The cascode modulation approach is an alteative tech
nique of ampliing polar modulated signals to a traditional
supply modulation scheme [].
8----8//$ © IEEE
in o
Fig. 1
V
C
100iout
d�
Co Lo
Casco de modulated RF power amplifer schematic.
A de mdulted PA
The schematic of a cascode modulated PA is shown in
Fig l The main feature of the cascode modulated class-E
PA is the abilit to control the output power by varing the
voltage Vcasc. The cascode voltage Vcasc can be employed
to control the average output power level [6] or it can be used to apply varing envelope signal in the case of a polar
transmitter [2] The output network of the cascode modulated
PA in Fig is designed to operate in a class-E like mode The
constant aplitude phase modulated signal is applied to the
switch-transistor Msw. The varing envelope signal is applied
to gate of the cascode device Mcasc.The main advantage of the casco de modulation tecnique
is the wide output power dynamic range and good reliabilit[2] The major drawback is high AM-AM nonlinearit
For the modeling puose, the PA does not contain an
impedance transformation network The PA is loaded by its
optimum load resistance RL of 3.74 n. It is assumed that the
phase modulated (sine wave) signal VrE,in has 5 % duty
cycle and its amplitude is .2 V
B, Emprl mdel
The proposed empirical model represents a baseband model
(that tracks the AM-AM PA characteristic) of the cascode
modulated PA The schematic of the empirical model is shown
in Fig 2. The goal of the modeling is to build an equivalent
circuit, which produces a cuent that is proportional to the
PA's output current In the analysis of the relation between
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Rs
I ref
va 0- v ca 0-
(a) b
Fg 2. n f th ut PA wth thDC unt u ref n ung th DC vtg u VEQ
the output current out and cascode voltage V only the
ON period of the cycle is considered. This is based on theassumption that in the OFF period the switch transistor Mlwis OFF and the output power is independent of the cascode
voltage VThe peak current through the switch can be expressed
as a nction of the output current according to [7] as
I d peak = I + l out = I [1 - � ( )], sm (1)= out [1 - sin]
where out is the amplitude of the output cuent outcontains only the ndamental component) and is the initial
phase shi constant. This equation can be rher simplied
has to be chosen exactly as ° for optimum class-E performance [7]) and the output current can be written as
I I dpk I d + I dfudout 7 7(2)
where I d and I dfud are the and ndamental drain
current components respectively. Equations (1) and (2) are
derived using a simplied ideal class-E aplier with an ideal
switch. The peak ain cuent I dpk depends on the cascode voltage or, in the polar applications, it depends
on the mean value of the V voltage.
From (1) it is evident that the relation between the output
current and peak ain cuent is linear. Therefore, in order to
model the nonlinear behavior of the cascode modulated the relation between the peak drain current and V voltage is
of interest. The ndamental output current calculated from
the peak ain current using (2) is plotted in Fig. 3 and
compared with the simulated fundamental output cuent of
the cascode modulated to demonstrate good match. The
simulated curve represents the output cuent obtained from
a harmonic balance simulation of the circuit.
The next step is to synthesize a circuit that ehibits the
transfer characteristic shown in Fig. The proposed empirical
� 0.3 · ��"o
- 02 ·
01
o
�
i
o 02 0 06 08 1 12 1 16 18Vcsc IV]
Fg 3 PA utut unt ut y 2 n th tu utfunnt utut unt vu V vtg
0.7r
=
=
:
�
.
06
ld,Empiril model
•05
� 0 _ 0
02
01
o
_�L- �
o 02 0 06 08 1 12 1 16 18Vcsc IV]
Fg 4. Sut k n unt f th ut PA nth ut vu V vtg
baseband model shown in Fig. 2(a), that is based on the
replica circuit M2w and M2eac of the cascode conected
transistors, meets this criteria. The purpose of R is to
smoothen the transition of the cascode transistor ain cuent
om the saturation to the linear region. The value of the R resistor is empirically obtained as
R � 20 . Rcascode 3 where Rod is the resistance of the cascode circuit at the saturation point of the drain. In the simulated circuit
Rcascode = 7 , R = 7 .1 a nd I ref = 7 5A
In order to model the conditions the cascode transistors
experience during the simulation, the ain voltage dr has to be limited to 1.8
The circuit behavior can be described as follows. If is
zero there is no current owing through the cascode circuit.
The dr voltage is 1.8 V; one part of the I rf cuent ows
to R and the second part retus back to the supply teinal
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through the diode D1 If the ase voltage is higher than the
threshold voltage of M2 then the cascode circuit starts
to draw cuent. The amount of drawn current is directly
controlled by the asc voltage. The cascode transistor M2
is in saturation and its drain cuent increases with asc. The
cascode circuit resistance decreases. The cascode current will
not saturate hard and suddenly because a part of the Irfcurrent ows to R. The ratio of R to Rcascod controls the
slope and maximum ain cuent through transistor M2 as
it enters the linear region.
The comparison of peak ain currents of the replica circuit
and cascode modulated PA versus V voltage is shown in
Fig. 4. The empirical model provides good match with the R
simulated curves. There is a small discrepancy in the region
where the casco de transistor operates in saturation.
The DC model om Fig. 2(a) can be re-aanged using
Vee
RD
Vd
VcasoId
Vg
. �
a
Vee
RD
Vd
RdsId
Vg
. �
(b)
Thevenin theorem into a fo that is more suitable for Fig. 5 Cascode amplifer schematic used with the analytical model insimplied calculations and intuitive analysis (see Fig. 2(b)). saturation region (a) and in linear region .
III. ANLYTICL MODEL
A simplied analytical model of the cascode CirCUt S proposed in this section. The main goal is to obtain an
analytical expression of the drain cuent I as a function of
asc. It is assumed that the switch transistor operates as an
ideal switch with the ON-resistance Rsw (Fig. 5). RD and V represent generic load resistance and supply voltage seen by
the cascode circuit respectively.
The cascode transistor M operates in two states. For low
asc voltages M is in saturation and if
4
it enters and remains in the linear region. VT is the cascode
transistor threshold voltage. The equivalent circuits for thesaturation and linear regions are shown in Fig. 5(a) and 5(b)
respectively. The following analysis is based on a simplied
model of the MOFET transistor.
A. Saturation region
The drain cuent of the cascode device in saturation is [8]
1 W2I = -C OX L (V gs VT)2
(5)
where and Cx are the eective mobilit of the carriers
and the gate oxide capacity, respectively. W is the chanel
width and L is the eective chanel length. The gate-source
voltage V gs of the M transistor can be written as
6
The surface mobilit of the carriers in the transistor channel
depends on various process parameters and also on the gate
and bulk voltages. The eective mobilit can be expressed
using an empirical relation [9]
(7)
where the is a tecnological constant, E = 09 MYcm
and v = 18 for electrons [9]. The average electrical eld
E experienced by the carriers in the inversion layer is
approximated according to [9] as
E � V
gs + V T asc + V T
ef - 6T ox� 6T ox
(8)
where x is the oxide thickness. For simplicit, V gs = ascis assumed in further calculations of E .
By substituting of 6 - (8) into (5) and solving for I
the
following result is obtained
where
I =
L + ,yLef
2
,+ L)CxR;w W
V : = asc VT.
(9)
10
Equation (9) represents the analytical form of the ain
current as a function of asc voltage in the saturation region.
B Linear region
In the linear region the cascode transistor can be substituted by the equivalent drain-source resistor Rds (Fig. 5(b)).
The drain current is given by the ah equation as [8]
I = Cxf
[(V gS VT)V ds V
f
s
]
11
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0
0
0
�04
-" 0
02
0
004 0 08 2
[]4 8
Fig. 6. Simulated (empirical model) and calculated (analytical model) draincurrents of cascode connected transistors versus casc voltage.
The drain-source voltage can be found using
(12)
Substituting of (12) into (11) and solving for Id yields (13).
The coecients a and ( are dened as
w( = eCOX .e
(14)
Equation (13) represents the analytical fo of the drain
current as a nction of asc voltage in the linear region .
IV. ODEL VERIFICATION
Combining (9) and (13) the ain cuent can be calculated
as a nction of asc. The verication of the analytical model
is based on the comparison with the empirical model assuming
RD = R The supply voltage used in the analytical model
is given as Vee = VEQ = IrefR = 53 V The values of
the tecnological constants are taken om the 0.13 m UMC
CMOS process.
The comparison of the calculated and simulated drain cur
rents through the cascode connected transistors is depicted in
Fig. 6. The discrepancy is largest in the transition area where
the cascode transistor operating point changes from the linear
region into saturation.
The perfoance of both the empirical and analytical models can be evaluated om Fig. 7 where the output power of the
cascode PA is plotted as a dependence on the Vasc voltage.
In the case of the empirical model the cascode transistor
drain current is simulated rst and then the output power is
calculated using (2). In the case of the analytical model the
drain cuent is calculated using (9) and (13) and the output
power is calculated using (2). It can be seen that both models
shows a good t to the circuit level simulation excluding
the sub-treshold region where Vasc is below 0.55
0
20
0E 0c
�. -0:0
Q
-20
-0
-4004 0 08
RF imultion
2 []
4 8
Fig. 7. Fundamental average output power delivered to L load versuscasc voltage. Cascode PA models and simulation (Harmonic balance).
V. ONCLUSION
In this aricle two modeling approaches of the cascode modulated PA are presented. The baseband empirical and
analytical models, that track the AM-AM characteristic of the
cascode modulated PA, have been proposed. A good t of
both models with the domain based simulations has been
demonstrated. The empirical model can be easily implemented
in CMOS technology. This model is potentially suitable for
analog predistorion or compensation of imperfections in the
stage e.g. process, voltage and temperature variation. It
can be utilized to monitor the PA output power.
CKNOWLEDGMENT
This work was supported by the Danish National Advanced
Technology Foundation through the 4GMCT project.E FERENCES
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