Download - Adder Verification
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Kogge Stone Adder Logic
Verification
D. W. Parent
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This is a very efficient 1 bit full adder.
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Carry Look Ahead
generate
propagate
carry
sum
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Derive the schematic.
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It is easier to manage the design if you partition items into
blocks
The Generate PropagateBlock (4 bits seemed
easier to do.)
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The look ahead carry generate block
Ver similar
to 4 bit CLA
but note ther
P and
G
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term.
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The sums are broken up into 4 bits each. This will help with
LVS later.
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WN/WP for a 16 bit CLA Adder in Static
wiring capacitance.
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WN/WP for a 16 bit CLA Adder in dynamic
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Higher order adders are too complex to draw at the circuit
level
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4 input 3 input
Note: Twoi:j
Buffer
Gray
Cell
:Black
Cell
:output vectors
i:ji:j,
i:j
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Higher order diagrams can be made as well
i:k k-1:l l-1:m m-1:j
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The Manchester Carry Chain can be greatly simplifies in
multiple output domino logic
123:0 2:0 1:0 0:0
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MCC PG Group
an or ac ne ns e
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
G=C
13Final Sum XOR inside
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Example: Find the Delay of the 16bit MCC adder.
Assume the MCC domino vs Static
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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This example shows how the logic was
ver e o a ogge tone er
Convert grey and black cells to schematics
Create a trusted adder
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When doing a completely new logic just
use e g a par s n e
Schematic
Make sure to
Symboledit the labelsso that they can be
seen in a large
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Once could use AOI or NAND NAND to implement these cells.
Schematic
A Grey cell is a Black cell
Symbolwithout the grouppropagate
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Tree Diagram of KS adder from
David Harris
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8 bit KS adder schematic with carry in and carry out
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try and show the equivalence of a ripple,
Not my strong suit.
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Create and verify a 1 bit full adder
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Create a 8bit trusted adder
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This will be used to compare the carry out
and sum signals of both adders.
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ADDER
Create a test bench that will
feed the same test
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and compare their outputs.
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Run KS adder against Trusted
adder Search for 1. If signals are different then XOR will give
one.
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Can not really see if there is a 1 value at this time scale.
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Export Data Into Text
NC verilog tracks the changes only. WE
can see that no signal was a 1 and since
we did all test vectors the adders are
logically equivalent.
This is all the data.
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KS adder structure.
adder3
verification
Pro ram adder!
Use Boolean logic!
It still worked.
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