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Behavioural synthesis of asynchronous controllers: a case study with a self-timed
communication channel
Alex Yakovlev, Frank Burns, Alex Bystrov, Albert Koelmans, Delong Shang
University of Newcastle upon Tyne
Rene Krenz
Royal Institute of Technology, Stockholm
ACiD-WG Workshop, München, Jan.2002
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Outline
Motivation• Design flow• Two-level behavioural synthesis• Direct translation from LPNs and STGs• Communication channel case study
– Specification, verification, controller synthesis, optimisation and performance
• Conclusion
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Motivation
• Complex asynchronous controllers still cannot be designed fully automatically
• Existing logic synthesis tools (cf. Petrify and Minimalist) can only cope with small-scale low level designs (state-space explosion, limited optimisation heuristics)
• Logic synthesis produces circuits whose structure does not correspond to their behaviour structure (bad for analysis and testing)
• Syntax-direct translation techniques may be a way forward but applied at what level?
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Motivation• Applying directly at front-end (cf. Tangram) guarantees
design productivity but may produce slow circuits (control flow is driven by program syntax, not by natural operation sequencing)
• Ideally, front-end (HDLs) needs efficient simulation support and flexible and rigorous interface with behavioural back-end (labelled Petri nets, STGs) used for synthesis
• The back-end must support compositionality and hierarchy (of HDLs) but offer sequencing paradigms (causality and concurrency) for high performance
• Optimisations can be applied to back-end models• Direct translation of LPNs and STGs helps structural
transparency between specification and implementation
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Motivation• Implications to new research targets on:
– Translation between HDLs and LPNs, FSMs, STGs, particularly formal underpinning of semantic links between front-end and back-end formats
– New composition and decomposition techniques (incl. various forms of refinement and transformations) applied to LPNs/STGs/FSMs
– New circuit mapping and optimisation techniques for different types of models (under various delay-dependence or relative time assumptions and different signalling schemes)
– Combination of direct mapping with logic synthesis (eg. circuits with predictable latency)
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Design flow
Control/data splitting
Hierarchical control spec
HDL specification
Datapath spec
LPN to circuit synthesis(direct mapping)
HDL implementation
Data logic synthesis
Control&data interfacing
Hierarchical control logic
STG to circuit synthesis(Petrify & direct mapping)
LPNSTG
Data logic
Our present focus
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Design flow
• What is now being developed at Newcastle?• translation from ‘subset VHDL’ (and other
languages) to LPNs and STGs• direct synthesis from LPNs and STGs• combined direct and logic (Petrify)
synthesis • optimisation at LPN/STG level (eg. for low
latency)
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HDL syntax directed mapping
doif (X=A) then
parOP1;OP2;
rapelse
seqOP3;OP4;
qesifod
do
par seq
OP2OP1 OP3 OP4
(X=A) ifthen else
Control flow is transferred between HDL syntax constructs rather than
between operations
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Two-level behavioural synthesis
doif (X=A) then
parOP1;OP2;
rapelse
seqOP3;OP4;
qesifod
(X=A) (X<>A)
OP1 OP2 OP3
OP4
dum dum
dum
High level control: Labelled Petri net (LPN)
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Two-level behavioural synthesis
Data path 1
OP1rOP3r
OP1a
OP4rOP3aOP4a
req1 ack1
Data path 2OP2r OP2a
ack2 req2
OP1r OP1a
OP3r OP3a
OP4r OP4a
req1 ack1
dum
OP2r+
req2+
ack2+
OP2a+
req2-
OP2r-
OP2a+
ack2-
Low level control: Signal Transition Graphs (STG)
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Two-level behavioural synthesis
(X=A) (X<>A)
OP1 OP2 OP3
OP4
dum dum
dum
DC1
DC2
DC3
DC4
DC5
High-level control logic directly mapped from LPN
Basic David cell (DC)
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Direct mapping of LPNs and STGs to David Cell netlist
p1 p2OperationControlled
p2(0) (1)
p1(1) (0)
1*(1)
To Operation
Operation can be interpreted as access to datapath (LPN) or as switching a binary (input or output) signal (STG)
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Direct mapping of LPNs and STGs
LPN-to-DC mapping elements
linear
join
fork
controlled choice
arbitrated choice
merge
input test
Gate-level DC implementations
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Communication channel example
• A duplex delay-insensitive channel for low power and pin-efficiency proposed by Steve Furber (AINT’2002)
• Relatively simple data path (with handshake access via push and pull protocols)
• Sophisticated control (involves arbitration, choice and concurrency)
• Natural two-level control decomposition• Requires low-latency (existing STG and BM
solutions produce too heavy logic)
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Channel Structure
Master Slave
N-of-M code
N-of-M code
N-of-M codes: dual-rail, 3-of-6,2-of-7
Key Protocol Symbols (e.g. in dual rail):
Start (01), Ack (10), Slave-Ack (11), Data (01 or 10)
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Protocol Specification
Master SlaveProtocol
Automaton
The protocol can be defined on an imaginary Protocol Automaton receiving symbols from both sides (it will hide all activity internal to Master and Slave)
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Protocol Specification
Master SlaveProtocol
Automaton
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Protocol Refined (for Dual Rail encoding)
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Protocol Verification
Master Slave
Properties to be verified:
absence of deadlock and delay-insensitivity (w.r.t. delays in the channel wires)
m01m
m10m
s01s
m01s
m10s
s10ss10m
s01m
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Protocol VerificationPetri net model of the protocol for verification
Fragment of the master subnet for verification
These places must be 1-safe to have freedom from communication interference (delay-insensitivity)
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Protocol Verification
The Petri net unfolding prefix was constructed by tool PUNT and checked:
There are no deadlocks
The net is 1-safe w.r.t. channel places (which proves delay-insensitivity)
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Controller Overview
push push
pull pull
High
Level
control
Data path
and low level
control
push
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Low-level logic
Tx controller
Sending interface
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LPN model for high level control (master)
Calls to local arbiters Slave-Ack pull
Three-way pulls
Three-way pushes
pushes
pulls
dummies inserted for direct DC mapping
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High level control (master) mapped directly from LPN
arbiter1
arbiter2
push
pull
dummies
pull
pullpush push
push
push
push
pull
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Towards synthesis for higher performance
dummypull
push
pull
Is the dummy in the right place?
It is on the cycle of (output) push and (input) pull:
pull->dummy->push->pull-dummy->push -> …
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Towards synthesis for higher performance
pull
push
Critical path
Non-critical path Synthesis rule:
Don’t insert dummies on critical paths
dummy
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Synthesis for lower I/O latency LPN level
pull logic
Environment (channel)
pull push internal actions
pull
High-level control
… …
push logic
input output input…
pull logic
Low latency shortcut
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Channel Cycle Time
Controller Implementation
Simplex mode Duplex mode
Direct mapping from LPN
7.6 ns 8.3 ns
Logic synthesis from STG
12.7 ns 16.5 ns
• These results were obtained for 0.6 micro CMOS
• Further improvement can be achieved by more use of low latency techniques (at the gate level) and introducing aggressive relative timing, in David cells and low level logic
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Conclusion
• Hierarchical (eg. Protocol) controller synthesis can go via back-end LPN/STG models
• Direct mapping from LPNs/STGs yields fast circuits that are easy to analyse and test
• Translation from PNs to David cell netlists implemented in tool pn2dc
• Translation from FSM VHDL specs to LPNs and STGs implemented in tools fsm2lpn and fsm2stg
• Further work needed on:• Formal link between HDLs and PNs (semantics and
equivalence), leading to better synthesis of PNs from HDLs • Optimisation techniques at LPN/STG and circuit levels
• See our papers in Async’02 and 11th UK Async Forum