Download - Lec-6 Pipeline Introduction
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Ajit Pal, IIT Kharagpur
Outline
IntroductionWhat is pipelining?
How is it implemented?
Performance Parameters Speedup, Throughput
Optimal number of stages
Examples of pipelining
Fixed Point Multiplier
Floating point adder
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Another Example
Consider two alternate ways in which anengineering college can work:
Approach-1. Admit a batch of students andnext batch admitted only after already admittedbatch completes (i.e. admit once every 4
years).
1st Year 2nd Year 3rd Year 4th Year 1st Year 2nd Year
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Approach-2. Admit students every year In the second approach admit a new batch
of students every year
Average number of students graduating per
year increases four times
Another Example
1st Year 2nd Year 3rd Year 4th Year
1st Year 2nd Year 3rd Year 4th Year
1st Year 2nd Year 3rd Year 4th Year
1st Year 2nd Year 3rd Year 4th Year
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Basic Concepts
What is pipelining?
It is an implementation technique wheremultiple tasks are performed in an
overlapped manner.
When can it be implemented?
It can be implemented when a task can be
divided into two or subtasks, which can beperformed independently.
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Example: A task takes time t
time
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Example: A task takes time t
time
1 2 k
The task is divided in k subtasks
time
. . .
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Synchronous Pipeline
How is it implemented?
Different subtasks are performed bydifferent hardware blocks known as stages
The result produced by each stage is
temporarily buffered in latches and thenpassed on to the next stage
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Synchronous Pipeline
S1 S2 Sk
LL LLL
Input Output
d m
Clock
Transfers between stages are simultaneous One task or operation enters the pipeline percycle
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How the tasks are executed?
Synchronous Pipeline
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Asynchronous Pipeline
S1 S2 Sk
Output
Ready
Ack
Ready
Ack
Ready
Ac
k
Ready
Ack
Input
Transfers performed when individual stages are ready Handshaking protocol between processors
Different amounts of delay may be experienced atdifferent stages
Can display variable throughput rate
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A Few Pipeline Concepts
Pipeline cycle :
Latch delay : d= max { m } + dPipeline frequency : f
f = 1 /
S1 S2 Sk
LL LLL
Input Output
d m
Clock
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Ideal Pipeline Speedup
k-stagepipeline processes n tasks ink + (n-1) clock cycles:
kcycles for the first task and n-1
cycles for the remaining n-1 tasks.Total time to process ntasks
Tk= [ k + (n-1)]
For the non-pipelined processor
T1 = n k
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Pipeline Speedup Expression
Speedup =
Observe that the memory bandwidth mustincrease by a factor of Sk
Otherwise, the processor would stallwaiting for data to arrive from memory
Sk=T1
Tk = n k [ k + (n-1)]
= n kk + (n-1)
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Pipeline Applications Historically, there are two different types of
pipelines: Arithmetic pipelines
Instruction pipelines
Arithmetic pipelines (e.g. FP multiplication) are notpopular in general purpose computers:
Needs a continuous stream of arithmeticoperations
e.g. Vector processors operating on an array
On the other had instruction pipelines being used
in almost every modern processor Computers execute billions of instructions, so
instruction throughput is what matters
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Pipelined Fixed Point Multiplier
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Pipelined Fixed Point Multiplier
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PipelinedFixed Point
Multiplier
S Cout
A B
nn
n+1
CPA
C S(b)
X Y
nn
n+1
CSA
Z
n
n+1
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Pipelined FloatingPoint Adder
Floating point number is representedby N = (-1)S FX2E
Addition is performed in four steps
Step 1: Adjustment of the significand
of the number with lesser exponentto match the larger exponent:8.96X101 + 48.6X10-1 8.96X101 +.486X101Step 2: Add the significands
8.96 + 0.486 9.246Step 3: Normalize the sum9.246 101 .9246 102
Step 4: Round off the sum
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Conclusion Introduced the basic concepts of pipelining What is pipelining?
It is an implementation technique where multiple tasksare performed in an overlapped manner
When can it be implemented?
It can be implemented when a task can be divided intotwo or subtasks, which can be performed independently
Observed that the time required to perform anindividual task does not decrease, but throughputincreases
Examples of pipelining considered
Fixed point multiplier Floating point adder
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Pipeline Performance Parameters Clock Period
= Max { time delay of a stage }1k + other delays
Frequency Reciprocal of the clock period
Speedup k stage pipeline, n tasks
k when n >> k.
Efficiency Ratio of its actual speedup to the ideal speedup
Throughput Number of instructions that can be completed per
cycle
)1(.
nkknSk
1f
kSk
w
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Thanks!