Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-1
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Lecture 190 – All Digital Frequency Synthesizer for BluetoothWhat is bluetooth?• A short-range technology for integration into mobile and handheld devices that is
targeted to replace cables.• Radio specification
- Frequency range: 2400 ~ 2483.5 MHz- Spectrum spreading: FHSS (Frequency Hopping Spectrum Spreading)
• fk = 2.402 + k MHz, k = 0, …, 78 (dwell time: .625 ms)• Channel bandwidth: 1 MHz
- Modulation: GFSK (BT = 0.5; 0.28 < h < 0.35)- Receiver sensitivity: -70 dBm @ 0.1% BER- Coverage area: Up to 10 m- Transmit power: 0 dbm (up to 20 dbm with power control)
Lower Guard Band Upper Guard BandRF Channel
2.400 2.48352.4802.402
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-2
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Frequency synthesizer specification for bluetooth application• Frequency range: 2.402 ~ 2.480 GHz• Settling time ≤ 220 usec• Phase noise ≤ - 89 dBc/Hz @ 500 KHz offset
≤ - 121 dBc/Hz @ 2 MHz offset• Channel bandwidth: 1 MHz, Error tolerance: ± 20 ppm (96 KHz)
Architecture selection• Direct digital frequency synthesizer: limit of speed by Nyquist sampling theorem• Integer-N frequency synthesizer (Channel spacing = reference freq.)
- Channel spacing Divide ratio In-band phase noise- Channel spacing Loop bandwidth Switching time
• Fractional-N frequency synthesizer (Channel spacing « reference freq.)- Lower in-band noise- Faster lock- Fractional spurs eliminated by modulating divide ratio using high-order ∑∆
modulator
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-3
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
System level design using linear model• When PLL is in lock state, the linear model can be used to analyze it.• Reference signal frequency » Loop bandwidth ⇒ Continuous model
Referenceinputθi
Referencenoiseθnr
Kd
PFDnoiseθnp
LPFnoiseθnl
F(s)
FMnoiseθnf
KV/s
VCOnoiseθnv
Outputθo
Outputnoiseθno1 / N
Divider noiseθnd
θo/N
( ) ( )( )
( )( ) ( ) ( ) ( ) ( ) 1 and where,
1 NsH
ssFKK
sGsHsG
sGss
sB vd
i
o ==+
==θθ
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-4
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
• Output noise power, θno
• Reference noise and VCO inherent noise are the two major sources of phase noise in a PLL
( ) ( )( ) ( )
22
22,
222
11
1
+
+
+
⋅+=sOsO
sON nveqnnrno θθθθ
Low-pass transfer function High-pass transfer function
( )( )
( ) ( ) ( ) ( ). and 11 where 22
2222
22, sN
sFKKsHsGsOsFKK
vdndnf
dnlnp
deqn =⋅=+++= θθθθθ
θθ0
ref
θθo
nv
θθo
nd
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-5
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Direct Digital Frequency Synthesizer• Direct Digital Frequency Synthesizer (DDFS)
- Advantage: high frequency resolution, fast switching time- Disadvantage: high power consumption, limitation of highest frequency by
Nyquist sampling theorem, discrete narrow band spurious signals• The DDFS methods are combined with PLLs to achieve fine frequency steps with
reasonable phase noise
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-6
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
PLL Based Frequency Synthesizer• PLL is negative feedback system whose output frequency is locked onto an input
signal- PD: error amplifier - LPF: suppress high frequency component of PD - VCO: Voltage Controlled Oscillator
• Low cost and good spurious suppression• Coarse frequency resolution or frequency step and bad phase noise• Slow switching speed for negative feedback loop
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-7
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
PLL Based Frequency Synthesizer (continued)• Closed loop transfer function
22
2
2)(1
)(
)()(1)()(
nn
n
VCOPD
VCOPD
ssN
sNsGKK
ssGKK
ssAsAsB
ωζωω
β ++=
⋅⋅⋅+
⋅⋅=
⋅+=
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-8
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Charge-Pump Frequency Synthesizer• Charge-pump phase locked loop (type 2, 3rd order PLL)
- Advantage: low phase noise- Disadvantage: process dependency, slow locking speed, large passive
external elements (Rs and Cs)
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-9
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Integer-N Frequency Synthesizer• Integer-N Frequency Synthesizer
- fout=N.fref, N: integer number- Frequency step size= reference frequency- Inverse relationship between step size and phase noise- To achieve a small channel spacing → a low fref → narrow loop BW →
increasing the settling time, and reducing VCO noise suppression- Low reference → large integer N → increasing in-band phase noise
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-10
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Dual Loop Frequency Synthesizer• Dual Loop Frequency Synthesizer
- Mixer is incorporated into the PLL → alter the relationship between the channel spacing and the reference frequency of integer N synthesizer
- 2 dual loop types: combination of 2 PLLs by a single side band mixer in parallel and in series
- Adding fixed high offset frequency and low variable frequency
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-11
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Dual Loop Frequency Synthesizer• Dual Loop Frequency Synthesizer
- Parallel configuration: (a fixed frequency + changeable frequency) @the output → large spurs during mixing
- Series configuration: changeable frequency is added inside the loop →longer time to settle, small sideband from the mixer
- The loop BW of the high frequency loop can be large→ more reduction of phase noise close to the carrier
- The division number of the divider can be reduced ← fixed offset frequency
- The sidebands produced from non-ideal SSB mixing and larger power consumption
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-12
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Fractional-N Frequency Synthesizer• Fractional-N Frequency Synthesizer
- Doesn’t require more current, complexity or bigger dies- The reference fref >> frequency step time, fstep- fVCO= fref(N+(K/F))
0,)1()(≥≥+=
⋅++−⋅= KF
FKN
FKNKFNN ityfractional
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-13
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
All Digital Frequency Synthesizer• Apply digital filter to achieve a single-chip freq. synthesizer
- Fully-integrated freq. synthesizer- Easy to implement Multi-mode application (ex. W-CDMA/GPRS/GSM)- Increase design robustness
• Apply MASH- Reduced spurs- Fast locking time
• Apply switched-current Oscillator- Wide locking range- Fast locking time
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-14
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block diagram
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-15
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Linear model of the proposed freq. syn.
ref
aVCODA
ref
feedback KKKKzFKz
zzFKzHωω
ω ⋅⋅=
⋅−−⋅⋅
== −
−
,))(1(1
)()( 1
1
N/ ωref Z-1
Ka
Kvco
1/N
KDA1/(1-Z-1) F(z)ωref
ωout
F(z)=FIR filter
ωfeedback
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-16
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
System level unit step response and pole-zero plot
System level locking time simulation (Bluetooth application)
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-17
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
System level noise simulation (Bluetooth application)
== DenNumFractional 32/64 0/64
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-18
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block design: High-order ∑∆ Modulator• Used to eliminate fractional spurs by modulating divide ratio• Higher-order modulator is used to meet higher spurs specification• First-order ∑∆ modulator
F(z) + +
z -1
+
-
2m
z -1
Y(z)
2m
0
+
-
+
+
A(z)
+ Y(z)
Q(z)
A(z)
Modeling
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-19
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Q(z)
+
z -1
Y(z)F(z)
+- 1- z -1
1 +
+
+
-
+
- Q(z)
+
• Third-order ∑∆ modulator system-level simulation result
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-20
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
y z x z z q zy z x z H z q zn o is e
( ) ( ) ( ) ( )( ) ( ) ( ) ( )
= + −= +
−1 1 33
3
Block Design (continued): • 3rd order MASH system level simulation
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-21
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block Design (continued)• Conventional CMOS static logic
- Wide noise margins- High packaging density - Zero static-power-dissipation- Coupling between the analog
blocks and the digital blocks - Susceptible to power-supply noise
• Current Mode Logic- Constant current source- Differential input & output
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-22
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block Design (continued)• 8-bit Digital-to-Analog Converter
- Symmetric 2-stage current-cell matrix architecture
- A 4-MSB current-cell matrix and a 4-LSB current-cell matrix
- Use thermometer-code- Monotonic conversion characteristic
)2222()2222(
00
11
22
33
40
51
62
73
BBBBIBBBBI
ILSB
MSBout +++
++++=
LSBMSB II ⋅=16
LOADoutout RIV ⋅=
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-23
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block Design (continued)• Prescaler: high operating frequency, low power
dissipation, low phase-noise contribution• Feedback CML: Transistors, MF1 and MF2
))0(1
1)((1
1)0(1
)0()(1
)()(
dbp
db
d
db
d
AFjAF
AfAF
fAfA
+−
⋅⋅+
=⋅+
=
ωω
- Fb: the gain of the feedback transistors- The BW of the feedback CML is wider than the BW
of the conventional CML
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-24
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block Design (Continued)• Feedback Current Mode Logic in D Flip-Flop
Lecture 190 – All Digital Frequency Synthesizer (07/16/03) Page 190-25
ECE6440 – Frequency Synthesizers © P.E. Allen - 2003
Block Design (Continued)• FIR digital filter
(a) Single flow graph of nth order (b) Linear Phase transpose direct form
Floating point coefficient