Transcript

LSIEDA Linux

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SFLsource

VHDLbehaviour

sfl2vh

xsch

adder.sfl

adder.vhdl

LSI structureVHDL

sxlibdataflow lib

vasy VHDLdata flow

adder.vbe

boom

boog

VHDLstructure

adder.vst

dataflow optimizer

logic synthesizer

behaviour converter

ocp

nero

coresymbolic layout

adder.ap

circuit view

cell placer

router

ring lsi symboliclayout

chip.ap

s2r

lsi physicallayout

chip.cifchip.vstchip.rin

sxlibcell library

Alliance tools

Alliance library

cmosdesign rule

Verilog - C++ ù�ú ¾Tû�ü#ý � î �p��þ � �(� ���ÿ � è�� � �(��è �bØ�Â������ ü Verilator� � Ã(Ä SFL � ������º���� è�� � �;��è �2Ø��ÿ � Â��*Þ�� ü�� ������ Ì

SFL SourceC++ basetest script

TranslatedVerilog source

TranslatedC++ source

Executable

sfl2vl

verilator

gcc

gcc

Logic and Simulation entry

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1KHz

10KHz

100KHz

1MHz

10MHz

100MHz

Speed

Turn Around Time0.1Hz

1Hz

10Hz � ��������

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HDL level

Cycle level

Emulator

Prototype

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al

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116 Ï3.2 Ð

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FreeDOS ÀÂÁ�ÃÅÄÇÆÉÈÉÊËÁÇÄ�ÌÎÍÐÏÒÑÔÓÂÕ Icarus VerilogÖÇ×ÎØ4 ÙÒÚÔÛ 1.1KHz ÜÒÝ ÖÇÞàßÎáÔâ ÏÐã�äËÛ Verilator

ÖÇ×Ø8 åàÛ 25KHz ÜÒÝ Öçæ�èÉéÂèÉêÔáçë

Case1:8086

8hz-mp3 MP3 Encoder

main( ){

}

L3_compress( ){

}

Vfilter *filter = new Vfilterextern "C" filtertest( ){

}

ììì

ììì

Hardware Simulation

filtertest( )

C++ Code

íïîÐðÎñóòÅôÂõÅöÂ÷ËøúùÎûÎüÂýÿþ������������ �� � ��������������������� û��� �� � ���� ð� �!ËûÎüÂý ñ�"��#�$�%'&�(*)�+ ��, û8hz-mp3 MP3 Encoder

main( ){

}

L3_compress( ){

}

filtertest( ){

}

---

---

Hardware Simulation

filtertest( )

C program

command_to_seconds( )

command_to_seconds( )

command_to_seconds( )

command_to_seconds( )

SECONDS

method simulation time[h:m:s]

runseconds

Verilator

18:43:41

00:02:45

.0/2143652.87:9<;>=2?A@ABDC>EFHG4 I ? WAV J4KMLON2P 9RQS5UTWV

340~446 XIntel Cereron 2.2GHz, 512MB RAM, Redhat Linux 8 Y @AB

Case2:MP3

i8086

MP3

i8086 Z\[^] g`_^acb ,MP3 d hkj+efehgji flkph]dmhnpo20 qsrstvu HDL w\[vxlyfzlu|{~}p��j�\�����f��� h ��� f o ^��E\ HDL w\[��s� Qh�� u�{j�l����� Xp���

main()

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Software Side(UI)

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C++ code C++ code

GCC(compile)

object object

G++(link)

SFL code

Verilog code

executablebinary

GCC(compile)sfl2vl

Verilator

simulation nvironment

hardwaresource code

Simulation

Emulation

C â¶ã�äÁå�æèçléhêìë~íïîéfðÁñ¼ò`ó�ä~ôöõ runseconds ÷�øèù|ôöõ�úUûcü¿ý 100 þjÿ����Uÿ � î��¶å¿éhêìëíïîìé�ð���¿ú­õ���� ����� ÷���ôïý��¶ù����­øèùü���ô����©û��

FPGA etc..PC

HWC++

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²´³¶µ¸·º¹¼»sfl2vl

(SFL-Verilog)

Verilator(Verilog-C++)

gcc(C++-Executable)

½¿¾ÁÀâĞÁÀÃÂ2718 3667

ÆÈÇÊɸË[s]

0.15

3667 11048 3.42

11048 --- 15.33

Ì´ÍÊθϺмÑsfl2vl

(SFL-Verilog)

Verilator(Verilog-C++)

gcc(C++-Executable)

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×ÈØÊÙ¸Ú[s]

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6176 20708 4.402

20708 --- 18.67

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