lsi verilator eda linux hdl verilator - shimizu lab./tokai...

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LSI EDA Linux RTL EDA Linux SFL Verilog VHDL EDA Linux VDEC TEG 31 100MHz ROHM0.35 m EDA Linux CD Live Linux FPGA LSI SFL RTL VHDL SFL TEG 14,000 14 (AND,OR,NOT, etc) 4 ( ) 31 AES SBOX ( ) RS-232C 2 t FPGA ASIC SFL source VHDL behaviour sfl2vh xsch adder.sfl adder.vhdl LSI structure VHDL sxlib dataflow lib vasy VHDL data flow adder.vbe boom boog VHDL structure adder.vst dataflow optimizer logic synthesizer behaviour converter ocp nero core symbolic layout adder.ap circuit view cell placer router ring lsi symbolic layout chip.ap s2r lsi physical layout chip.cif chip.vst chip.rin sxlib cell library Alliance tools Alliance library cmos design rule Verilog - C++ Verilator SFL SFL Source C++ base test script Translated Verilog source Translated C++ source Executable sfl2vl verilator gcc gcc Logic and Simulation entry sfl2vl Verilator HDL Verilator / Verilator Verilog sfl2vl IP MP3 i8086 100Hz 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz Speed Turn Around Time 0.1Hz 1Hz 10Hz Gate level HDL level Cycle level Emulator Prototype (C/C++ ) Real Virtual 1 10 100 17 2.8 28 11.6 116 3.2 "2002 LSI - (2)-" SFL Verilog Verilog C++ SystemC EDA Linux http://www.ip-arch.jp/ HDL FreeDOS i8086 IcarusVerilog [S] Verilator [S] for 295.030 76.01 1079.36 2.860 3.31 48.76 103.2 22.9 22.1 FreeDOS 14400 500 28.8 FreeDOS Icarus Verilog 4 1.1KHz Verilator 8 25KHz Case1:8086 8hz-mp3 MP3 Encoder main( ) { } L3_compress( ) { } Vfilter *filter = new Vfilter extern "C" filtertest( ) { } Hardware Simulation filtertest( ) C++ Code 8hz-mp3 MP3 Encoder main( ) { } L3_compress( ) { } filtertest( ) { } Hardware Simulation filtertest( ) C program command_to_seconds( ) command_to_seconds( ) command_to_seconds( ) command_to_seconds( ) SECONDS method simulation time[h:m:s] runseconds Verilator 18:43:41 00:02:45 4 WAV 340~446 Intel Cereron 2.2GHz, 512MB RAM, Redhat Linux 8 Case2:MP3 i8086 MP3 i8086 ,MP3 20 HDL HDL main() SCE_MI Hardware Side SCE_MI Software Side (UI) Verilator HW C++ code C++ code GCC (compile) object object G++ (link) SFL code Verilog code executable binary GCC (compile) sfl2vl Verilator simulation nvironment hardware source code Simulation Emulation C runseco nds 10 0 FPGA etc.. PC HW C++ SFL Verilog Icarus Verilog 22 SFL SECONDS 300 C++ SCE-MI UI C++API sfl2vl (SFL-Verilog) Verilator (Verilog-C++) gcc (C++-Executable) 2718 3667 [s] 0.15 3667 11048 3.42 11048 --- 15.33 sfl2vl (SFL-Verilog) Verilator (Verilog-C++) gcc (C++-Executable) 3909 6176 [s] 0.500 6176 20708 4.402 20708 --- 18.67 & 4.402 24 S 4.402 19

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LSIEDA Linux

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adder.vhdl

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sxlibdataflow lib

vasy VHDLdata flow

adder.vbe

boom

boog

VHDLstructure

adder.vst

dataflow optimizer

logic synthesizer

behaviour converter

ocp

nero

coresymbolic layout

adder.ap

circuit view

cell placer

router

ring lsi symboliclayout

chip.ap

s2r

lsi physicallayout

chip.cifchip.vstchip.rin

sxlibcell library

Alliance tools

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cmosdesign rule

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verilator

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Case1:8086

8hz-mp3 MP3 Encoder

main( ){

}

L3_compress( ){

}

Vfilter *filter = new Vfilterextern "C" filtertest( ){

}

ììì

ììì

Hardware Simulation

filtertest( )

C++ Code

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main( ){

}

L3_compress( ){

}

filtertest( ){

}

---

---

Hardware Simulation

filtertest( )

C program

command_to_seconds( )

command_to_seconds( )

command_to_seconds( )

command_to_seconds( )

SECONDS

method simulation time[h:m:s]

runseconds

Verilator

18:43:41

00:02:45

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Case2:MP3

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gcc(C++-Executable)

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3667 11048 3.42

11048 --- 15.33

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gcc(C++-Executable)

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