Download - Manufac Overview
-
8/11/2019 Manufac Overview
1/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
1
Semiconductor ManufacturingTechnology:Semiconductor Manufacturing Processes
Conrad T. SorensonPraxair, Inc.
1999 Arizona Board of Regents for The University of Arizona
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
-
8/11/2019 Manufac Overview
2/34
-
8/11/2019 Manufac Overview
3/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
3
Design
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Establish Design Rules Circuit Element Design Interconnect Routing Device Simulation Pattern Preparation
-
8/11/2019 Manufac Overview
4/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
4
Pattern Preparation Reticle
Chrome Pattern
Quartz Substrate
Pellicle
-
8/11/2019 Manufac Overview
5/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
5
Wafer Preparation
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Polysilicon Refining
Crystal Pulling Wafer Slicing & Polishing Epitaxial Silicon Deposition
-
8/11/2019 Manufac Overview
6/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
6
Polysilicon Refining
Chemical Reactions Silicon Refining: SiO 2 + 2 C Si + 2 COSilicon Purification: Si + 3 HCl HSiCl 3 + H 2 Silicon Deposition: HSiCl 3 + H 2 Si + 3 HCl
Reactants H2
Silicon Intermediates H2SiCl 2 HSiCl 3
-
8/11/2019 Manufac Overview
7/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
7
Crystal Pulling Quartz Tube
Rotating Chuck
Seed Crystal
Growing Crystal(boule)
RF or ResistanceHeating Coils
Molten Silicon
(Melt)Crucible
Materials Polysilicon Nodules * Ar * H2
* High proportion of the total product use
Process Conditions Flow Rate: 20 to 50 liters/minTime: 18 to 24 hoursTemperature: >1,300 degrees C
Pressure: 20 Torr
-
8/11/2019 Manufac Overview
8/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
83/15/98 PRAX01C.PPT Rev. 1.0
Wafer Slicing & Polishing
The silicon ingot is sliced intoindividual wafers, polished, andcleaned.
silicon wafer
p+ silicon substrate
-
8/11/2019 Manufac Overview
9/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
9
Epitaxial Silicon Deposition
GasInput Lamp
Module
QuartzLamps
Wafers
Susceptor
Exhaust
* High proportion of the total product use
Chemical Reactions Silicon Deposition: HSiCl 3 + H 2 Si + 3 HCl
Process Conditions Flow Rates: 5 to 50 liters/minTemperature: 900 to 1,100 degrees C.Pressure: 100 Torr to Atmospheric
silicon wafer
p- silicon epi layer
p+ s ilicon substrate
Dopants AsH 3 B2H6 PH 3
Etchant HCl
Carriers ArH2 *
N2
Silicon Sources SiH 4 H2SiCl 2 HSiCl 3 * SiCl 4 *
-
8/11/2019 Manufac Overview
10/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
10
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIon
Implantation
Planarization
Test &Assembly
DesignWaferPreparation Thermal Oxidation
Silicon Nitride Deposition- Low Pressure Chemical Vapor
Deposition (LPCVD) Polysilicon Deposition
- Low Pressure Chemical VaporDeposition (LPCVD)
Annealing
Front-End Processes
-
8/11/2019 Manufac Overview
11/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
11
Front-End Processes
* High proportion of the total product use
Polysilicon H2
N2 SiH 4 * AsH 3 B2H6 PH 3
Exhaust ViaVacuum Pumpsand Scrubber
3 ZoneTemperatureControl
Gas Inlet
Vertical LPCVD Furnace
Quartz TubeChemical Reactions Thermal Oxidation: Si + O 2 SiO 2
Nitride Deposition: 3 SiH4 + 4 NH
3 Si
3 N
4 + 12 H
2
Polysilicon Deposition: SiH 4 Si + 2 H 2Process Conditions (Silicon Nitride LPCVD)
Flow Rates: 10 - 300 sccmTemperature: 600 degrees C.Pressure: 100 mTorr
silicon dioxide (oxide)
p- silicon epi layer
p+ silicon substrate
Nitride NH 3 * H2SiCl 2 *
N2 SiH 4 * SiCl 4
Oxidation Ar N2H2OCl2 H2 HCl * O2 * Dichloroethene *
Annealing ArHeH2
N2
-
8/11/2019 Manufac Overview
12/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
12
Photolithography
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Photoresist Coating Processes Exposure Processes
-
8/11/2019 Manufac Overview
13/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
13
Photoresist Coating Processes
p- epi
p+ substrate
field oxidephotoresist
Photoresists Negative Photoresist * Positive Photoresist *
Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials *
Developers TMAH * Specialty Developers *
Inert Gases Ar N2
-
8/11/2019 Manufac Overview
14/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
14
Exposure Processes
p- epi
p+ substrate
field oxidephotoresist
Expose Kr + F 2 (gas) *
Inert Gases N2
-
8/11/2019 Manufac Overview
15/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
15
Ion Implantation
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Well Implants Channel Implants Source/Drain Implants
-
8/11/2019 Manufac Overview
16/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
16
Ion Implantation
180 kVResolvingAperture
Ion Source
Equipment Ground
Acceleration Tube
90 Analyzing Magnet
Terminal Ground
20 kV
Focus Neutral beam andbeam path gated
Beam trap andgate plate
Wafer in waferprocess chamber
X - axisscanner
Y - axisscanner
Neutral beam trapand beam gate
GasesArAsH 3
B11
F3 * He N2 PH 3 SiH 4 SiF 4GeH 4
Solids GaIn
SbLiquids
Al(CH 3)3
* High proportion of the total product use
junctiondepth
p- epi
p+ substrate
field oxidephotoresist mask
n-w ellp-channel transistor
phosphorus
(-) ions
Process Conditions Flow Rate: 5 sccmPressure: 10 -5 TorrAccelerating Voltage: 5 to 200 keV
-
8/11/2019 Manufac Overview
17/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
17
Etch
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Conductor Etch- Poly Etch and Silicon Trench
Etch- Metal Etch
Dielectric Etch
-
8/11/2019 Manufac Overview
18/34
-
8/11/2019 Manufac Overview
19/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
19
Dielectric Etch
* High proportion of the total product use
EtchChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
RIE Chamber
Transfer
Chamber
Gas Inlet
Exhaust
RF Power
Wafer
Contact locations
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Chemical Reactions Oxide Etch: SiO 2 + C 2F6 SiF 4 + CO 2 + CF 4 + 2 CO
Process Conditions Flow Rates: 10 to 300 sccmPressure: 5 to 10 mTorrRF Power: 100 to 200 Watts
Plasma Dielectric Etches CHF 3 * CF 4 C2F6 C3F8 CO *
Diluents ArHe
N2
CO 2 O2SF6 SiF 4
-
8/11/2019 Manufac Overview
20/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
20
Cleaning
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Critical Cleaning Photoresist Strips Pre-Deposition Cleans
-
8/11/2019 Manufac Overview
21/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
21
Critical Cleaning
11 22 33 44 55
1 Organics 2 Oxides 3 Particles 4 Metals 5 DryH 2 SO 4 + HF + NH 4 OH + HCl + H 2 O or IPA +
H 2 O 2 H 2 O H 2 O 2 + H 2 O H 2 O 2 + H 2 O N 2H 2 O Rinse H 2 O Rinse H 2 O Rinse H 2 O Rinse
Contact locations
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
RCA Clean SC1 Clean (H 2O + NH 4OH + H 2O2) *
* SC2 Clean (H 2O + HCl + H 2O2) * Piranha Strip * H 2SO 4 + H 2O2 *
Nitride Strip H3PO 4 *
Oxide Strip HF + H 2O *
Solvent Cleans NMPProprietary Amines (liquid)
Dry Cleans HFO2 PlasmaAlcohol + O 3
Dry Strip N2OO2 CF 4 + O 2 O3
Process Conditions
Temperature: Piranha Strip is 180 degrees C.
-
8/11/2019 Manufac Overview
22/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
22
Thin Films
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation Chemical Vapor Deposition
(CVD) Dielectric CVD Tungsten
Physical Vapor Deposition(PVD)
Chamber Cleaning
-
8/11/2019 Manufac Overview
23/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
23
Chemical Vapor Deposition (CVD) Dielectric
* High proportion of the total product use
CVD Dielectric O2 O
3TEOS * TMP *
TEOSSource
LPCVDChamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
Metering
Pump
Inert Mixing
Gas
Process Gas
Vaporizer
DirectLiquid
Injection
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Metal 1insulator layer 2
Chemical Reactions Si(OC 2H5)4 + 9 O 3 SiO 2 + 5 CO + 3 CO 2 + 10 H 2O
Process Conditions (ILD) Flow Rate: 100 to 300 sccmPressure: 50 Torr to Atmospheric
-
8/11/2019 Manufac Overview
24/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
24
Chemical Vapor Deposition (CVD) Tungsten
* High proportion of the total product use
CVD Dielectric WF
6 *
ArH2
N2
OutputCassette
InputCassette
WaferHander Wafers
Water-cooledShowerheads
Multistation SequentialDeposition Chamber
ResistivelyHeated Pedestal
n-w ellp-channel transistor
p-welln-channel transistor
p+ substrate
titanium tungsten
Chemical Reactions
WF 6 + 3 H 2 W + 6 HFProcess Conditions
Flow Rate: 100 to 300 sccmPressure: 100 mTorrTemperature: 400 degrees C.
-
8/11/2019 Manufac Overview
25/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
25
Physical Vapor Deposition (PVD)
Barrier Metals SiH 4 Ar N2 N2Ti PVD Targets *
Physical
VaporDepositionChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
PVD Chamber
TransferChamber
Cryo Pump
Wafer
N S N
+
e -
BacksideHe Cooling
Argon &Nitrogen
ReactiveGases
DC PowerSupply (+)
* High proportion of the total product use
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Process Conditions Pressure: < 5 mTorrTemperature: 200 degrees C.RF Power:
-
8/11/2019 Manufac Overview
26/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
26
Chamber Cleaning
* High proportion of the total product use
Chamber Cleaning C2F6 *
NF 3 ClF 3
Water-cooledShowerheads
Multistation SequentialDeposition Chamber
ResistivelyHeated Pedestal
Chemical Reactions Oxide Etch: SiO 2 + C 2F6 SiF 4 + CO 2 + CF 4 + 2 CO
Process Conditions Flow Rates: 10 to 300 sccmPressure: 10 to 100 mTorrRF Power: 100 to 200 Watts
Aluminum
Surface Coating
Process Material Residue
Chamber Wall Cross-Section
-
8/11/2019 Manufac Overview
27/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
27
Planarization
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Oxide Planarization Metal Planarization
-
8/11/2019 Manufac Overview
28/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
28
Chemical Mechanical Planarization (CMP)
* High proportion of the total product use.
Platen
PolishingHead
PadConditioner
Carousel
HeadSweep Slide
Load/UnloadStation
Wafer Handling
Robot & I/O
Polishing PadSlurry
Delivery
Platen
WaferCarrier
Wafer
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Backing (Carrier) Film Polyurethane
Pad Polyurethane
Pad Conditioner Abrasive
CMP (Oxide) Silica SlurryKOH *
NH 4OHH2O
CMP (Metal) Alumina * FeNO 3
Process Conditions (Oxide) Flow: 250 to 1000 ml/min
Particle Size: 100 to 250 nmConcentration: 10 to 15%, 10.5 to 11.3 pHProcess Conditions (Metal)
Flow: 50 to 100 ml/minParticle Size: 180 to 280 nmConcentration: 3 to 7%, 4.1 - 4.4 pH
*
-
8/11/2019 Manufac Overview
29/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
29
Test and Assembly
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
Electrical Test Probe Die Cut and Assembly Die Attach and Wire Bonding Final Test
-
8/11/2019 Manufac Overview
30/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
30
Electrical Test Probe
Defective IC
Individual integrated circuitsare tested to distinguish good
die from bad ones.
n-wellp-channel transistor
p-welln-channel transistor
p+ substrate
bonding pad
nitrideMetal 2
-
8/11/2019 Manufac Overview
31/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
31
Die Cut and Assembly
Good chips are attachedto a lead frame package.
-
8/11/2019 Manufac Overview
32/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
32
Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
-
8/11/2019 Manufac Overview
33/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
33
Final Test
Chips are electricallytested under varyingenvironmental conditions.
-
8/11/2019 Manufac Overview
34/34
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Sorenson
34
References
1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT,Austin Community College, January 2, 1997.
2. Semiconductor Processing with MKS Instruments, Inc.3. Worthington, Eric. New CMP architecture addresses key process issues, Solid State
Technology , January 1996.
4. Leskonic, Sharon. Overview of CMP Processing, SEMATECH Presentation, 1996. 5. Gwozdz, Peter. Semiconductor Processing Technology SEMI, 1997. 6. CVD Tungsten, Novellus Sales Brochure, 7/96.7. Fullman Company website. Fullman Company - The Semiconductor Manufacturing
Process, http://www.fullman.com/semiconductors/index.html, 1997. 8. Barrett, Craig R. From Sand to Silicon: Manufacturing an Integrated Circuit, Scientific
American Special Issue: The Solid State Century , January 22, 1998.