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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson

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Semiconductor ManufacturingTechnology:Semiconductor Manufacturing Processes

Conrad T. SorensonPraxair, Inc.

1999 Arizona Board of Regents for The University of Arizona

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing


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Design

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly

DesignWaferPreparation

Establish Design Rules Circuit Element Design Interconnect Routing Device Simulation Pattern Preparation


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Pattern Preparation Reticle

Chrome Pattern

Quartz Substrate

Pellicle


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Wafer Preparation

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Polysilicon Refining

Crystal Pulling Wafer Slicing & Polishing Epitaxial Silicon Deposition


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Polysilicon Refining

Chemical Reactions Silicon Refining: SiO 2 + 2 C Si + 2 COSilicon Purification: Si + 3 HCl HSiCl 3 + H 2 Silicon Deposition: HSiCl 3 + H 2 Si + 3 HCl

Reactants H2

Silicon Intermediates H2SiCl 2 HSiCl 3


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Crystal Pulling Quartz Tube

Rotating Chuck

Seed Crystal

Growing Crystal(boule)

RF or ResistanceHeating Coils

Molten Silicon

(Melt)Crucible

Materials Polysilicon Nodules * Ar * H2

* High proportion of the total product use

Process Conditions Flow Rate: 20 to 50 liters/minTime: 18 to 24 hoursTemperature: >1,300 degrees C

Pressure: 20 Torr


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83/15/98 PRAX01C.PPT Rev. 1.0

Wafer Slicing & Polishing

The silicon ingot is sliced intoindividual wafers, polished, andcleaned.

silicon wafer

p+ silicon substrate


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Epitaxial Silicon Deposition

GasInput Lamp

Module

QuartzLamps

Wafers

Susceptor

Exhaust


Chemical Reactions Silicon Deposition: HSiCl 3 + H 2 Si + 3 HCl

Process Conditions Flow Rates: 5 to 50 liters/minTemperature: 900 to 1,100 degrees C.Pressure: 100 Torr to Atmospheric

silicon wafer

p- silicon epi layer

p+ s ilicon substrate

Dopants AsH 3 B2H6 PH 3

Etchant HCl

Carriers ArH2 *

N2

Silicon Sources SiH 4 H2SiCl 2 HSiCl 3 * SiCl 4 *


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Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIon

Implantation

Planarization

Test &Assembly

DesignWaferPreparation Thermal Oxidation

Silicon Nitride Deposition- Low Pressure Chemical Vapor

Deposition (LPCVD) Polysilicon Deposition

- Low Pressure Chemical VaporDeposition (LPCVD)

Annealing

Front-End Processes


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Front-End Processes


Polysilicon H2

N2 SiH 4 * AsH 3 B2H6 PH 3

Exhaust ViaVacuum Pumpsand Scrubber

3 ZoneTemperatureControl

Gas Inlet

Vertical LPCVD Furnace

Quartz TubeChemical Reactions Thermal Oxidation: Si + O 2 SiO 2

Nitride Deposition: 3 SiH4 + 4 NH

3 Si

3 N

4 + 12 H

2

Polysilicon Deposition: SiH 4 Si + 2 H 2Process Conditions (Silicon Nitride LPCVD)

Flow Rates: 10 - 300 sccmTemperature: 600 degrees C.Pressure: 100 mTorr

silicon dioxide (oxide)

p- silicon epi layer

p+ silicon substrate

Nitride NH 3 * H2SiCl 2 *

N2 SiH 4 * SiCl 4

Oxidation Ar N2H2OCl2 H2 HCl * O2 * Dichloroethene *

Annealing ArHeH2

N2


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Photolithography

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Photoresist Coating Processes Exposure Processes


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Photoresist Coating Processes

p- epi

p+ substrate

field oxidephotoresist

Photoresists Negative Photoresist * Positive Photoresist *

Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials *

Developers TMAH * Specialty Developers *

Inert Gases Ar N2


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Exposure Processes

p- epi

p+ substrate

field oxidephotoresist

Expose Kr + F 2 (gas) *

Inert Gases N2


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Ion Implantation

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Well Implants Channel Implants Source/Drain Implants


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Ion Implantation

180 kVResolvingAperture

Ion Source

Equipment Ground

Acceleration Tube

90 Analyzing Magnet

Terminal Ground

20 kV

Focus Neutral beam andbeam path gated

Beam trap andgate plate

Wafer in waferprocess chamber

X - axisscanner

Y - axisscanner

Neutral beam trapand beam gate

GasesArAsH 3

B11

F3 * He N2 PH 3 SiH 4 SiF 4GeH 4

Solids GaIn

SbLiquids

Al(CH 3)3


junctiondepth

p- epi

p+ substrate

field oxidephotoresist mask

n-w ellp-channel transistor

phosphorus

(-) ions

Process Conditions Flow Rate: 5 sccmPressure: 10 -5 TorrAccelerating Voltage: 5 to 200 keV


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Etch

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Conductor Etch- Poly Etch and Silicon Trench

Etch- Metal Etch

Dielectric Etch


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Dielectric Etch


EtchChambers

Cluster ToolConfiguration

TransferChamber

Loadlock

Wafers

RIE Chamber

Transfer

Chamber

Gas Inlet

Exhaust

RF Power

Wafer

Contact locations


p-w elln-channel transistor

p+ substrate

Chemical Reactions Oxide Etch: SiO 2 + C 2F6 SiF 4 + CO 2 + CF 4 + 2 CO

Process Conditions Flow Rates: 10 to 300 sccmPressure: 5 to 10 mTorrRF Power: 100 to 200 Watts

Plasma Dielectric Etches CHF 3 * CF 4 C2F6 C3F8 CO *

Diluents ArHe

N2

CO 2 O2SF6 SiF 4


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Cleaning

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Critical Cleaning Photoresist Strips Pre-Deposition Cleans


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Critical Cleaning

11 22 33 44 55

1 Organics 2 Oxides 3 Particles 4 Metals 5 DryH 2 SO 4 + HF + NH 4 OH + HCl + H 2 O or IPA +

H 2 O 2 H 2 O H 2 O 2 + H 2 O H 2 O 2 + H 2 O N 2H 2 O Rinse H 2 O Rinse H 2 O Rinse H 2 O Rinse

Contact locations



p+ substrate

RCA Clean SC1 Clean (H 2O + NH 4OH + H 2O2) *

* SC2 Clean (H 2O + HCl + H 2O2) * Piranha Strip * H 2SO 4 + H 2O2 *

Nitride Strip H3PO 4 *

Oxide Strip HF + H 2O *

Solvent Cleans NMPProprietary Amines (liquid)

Dry Cleans HFO2 PlasmaAlcohol + O 3

Dry Strip N2OO2 CF 4 + O 2 O3

Process Conditions

Temperature: Piranha Strip is 180 degrees C.


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Thin Films

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly

DesignWaferPreparation Chemical Vapor Deposition

(CVD) Dielectric CVD Tungsten

Physical Vapor Deposition(PVD)

Chamber Cleaning


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Chemical Vapor Deposition (CVD) Dielectric


CVD Dielectric O2 O

3TEOS * TMP *

TEOSSource

LPCVDChamber

TransferChamber

Gas Inlet

Exhaust

RF Power

Wafer

Metering

Pump

Inert Mixing

Gas

Process Gas

Vaporizer

DirectLiquid

Injection



p+ substrate

Metal 1insulator layer 2

Chemical Reactions Si(OC 2H5)4 + 9 O 3 SiO 2 + 5 CO + 3 CO 2 + 10 H 2O

Process Conditions (ILD) Flow Rate: 100 to 300 sccmPressure: 50 Torr to Atmospheric


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Chemical Vapor Deposition (CVD) Tungsten


CVD Dielectric WF

6 *

ArH2

N2

OutputCassette

InputCassette

WaferHander Wafers

Water-cooledShowerheads

Multistation SequentialDeposition Chamber

ResistivelyHeated Pedestal


p-welln-channel transistor

p+ substrate

titanium tungsten

Chemical Reactions

WF 6 + 3 H 2 W + 6 HFProcess Conditions

Flow Rate: 100 to 300 sccmPressure: 100 mTorrTemperature: 400 degrees C.


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Physical Vapor Deposition (PVD)

Barrier Metals SiH 4 Ar N2 N2Ti PVD Targets *

Physical

VaporDepositionChambers

Cluster ToolConfiguration

TransferChamber

Loadlock

Wafers

PVD Chamber

TransferChamber

Cryo Pump

Wafer

N S N

+

e -

BacksideHe Cooling

Argon &Nitrogen

ReactiveGases

DC PowerSupply (+)




p+ substrate

Process Conditions Pressure: < 5 mTorrTemperature: 200 degrees C.RF Power:


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Chamber Cleaning


Chamber Cleaning C2F6 *

NF 3 ClF 3

Water-cooledShowerheads

Multistation SequentialDeposition Chamber

ResistivelyHeated Pedestal

Chemical Reactions Oxide Etch: SiO 2 + C 2F6 SiF 4 + CO 2 + CF 4 + 2 CO

Process Conditions Flow Rates: 10 to 300 sccmPressure: 10 to 100 mTorrRF Power: 100 to 200 Watts

Aluminum

Surface Coating

Process Material Residue

Chamber Wall Cross-Section


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Planarization

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Oxide Planarization Metal Planarization


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Chemical Mechanical Planarization (CMP)

* High proportion of the total product use.

Platen

PolishingHead

PadConditioner

Carousel

HeadSweep Slide

Load/UnloadStation

Wafer Handling

Robot & I/O

Polishing PadSlurry

Delivery

Platen

WaferCarrier

Wafer



p+ substrate

Backing (Carrier) Film Polyurethane

Pad Polyurethane

Pad Conditioner Abrasive

CMP (Oxide) Silica SlurryKOH *

NH 4OHH2O

CMP (Metal) Alumina * FeNO 3

Process Conditions (Oxide) Flow: 250 to 1000 ml/min

Particle Size: 100 to 250 nmConcentration: 10 to 15%, 10.5 to 11.3 pHProcess Conditions (Metal)

Flow: 50 to 100 ml/minParticle Size: 180 to 280 nmConcentration: 3 to 7%, 4.1 - 4.4 pH

*


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Test and Assembly

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


Electrical Test Probe Die Cut and Assembly Die Attach and Wire Bonding Final Test


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Electrical Test Probe

Defective IC

Individual integrated circuitsare tested to distinguish good

die from bad ones.

n-wellp-channel transistor

p-welln-channel transistor

p+ substrate

bonding pad

nitrideMetal 2


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Die Cut and Assembly

Good chips are attachedto a lead frame package.


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Die Attach and Wire Bonding

lead frame gold wire

bonding pad

connecting pin


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Final Test

Chips are electricallytested under varyingenvironmental conditions.


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References

1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT,Austin Community College, January 2, 1997.

2. Semiconductor Processing with MKS Instruments, Inc.3. Worthington, Eric. New CMP architecture addresses key process issues, Solid State

Technology , January 1996.

4. Leskonic, Sharon. Overview of CMP Processing, SEMATECH Presentation, 1996. 5. Gwozdz, Peter. Semiconductor Processing Technology SEMI, 1997. 6. CVD Tungsten, Novellus Sales Brochure, 7/96.7. Fullman Company website. Fullman Company - The Semiconductor Manufacturing

Process, http://www.fullman.com/semiconductors/index.html, 1997. 8. Barrett, Craig R. From Sand to Silicon: Manufacturing an Integrated Circuit, Scientific

American Special Issue: The Solid State Century , January 22, 1998.

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