Approved by the Senate in its 70th meeting held on May 25,2009
Page 1
SCHEME OF COURSES FOR
MTech (VLSI Design and CAD)
First Semester
S. No. Course No. Course Name L T P Cr
1. PVL101 Physics of Semiconductor Devices 3 1 0 3.5
2. PVL102 IC Fabrication Technology 3 0 0 3.0
3. PVL103 Digital VLSI Design 3 1 2 4.5
4. PVL104 CAD Systems Environment 3 1 2 4.5
5. PVL105 Logic Synthesis using HDLs 3 1 2 4.5
Total 15 4 6 20.0
Second Semester
S. No. Course No. Course Name L T P Cr
1. PVL201 Analog IC Design 3 1 4 5.5
2. PVL202 Embedded Systems 3 0 2 4.0
3. PVL203 VLSI Signal Processing 3 0 0 3.0
4. Elective – I 3 0 0 3.0
5 Elective – II 3 1 2 4.5
Total 15 2 8 20.0
Third Semester
S. No. Course No. Course Name L T P Cr
1. Elective – III 3 0 0 3.0
2. Elective – IV 3 0 0 3.0
3. PVL391 Seminar 4.0
4. PVL091 Thesis (starts) -
Total 6 0 0 10.0
Fourth Semester
S. No. Course No. Course Name L T P Cr
1. PVL091 Thesis (Contd …) -
Total Credits – 50
Approved by the Senate in its 70th meeting held on May 25,2009
Page 2
List of Electives
Elective–I
S. No. Course No. Course Name L T P Cr
1. PVL211 VLSI Architectures 3 0 0 3.0
2. PVL212 Physical Design Automation 3 0 0 3.0
3. PVL213 Nanoelectronics 3 0 0 3.0
4. PVL214 Process and Devices Characterization 3 0 0 3.0
5. PVL215 Real Time Software and Systems 3 0 0 3.0
6. PEC212 Audio and Speech Processing 3 0 0 3.0
Elective–II
S. No. Course No. Course Name L T P Cr
1. PVL221 VLSI Subsystem Design 3 1 2 4.5
2. PVL222 ASICs and FPGAs 3 1 2 4.5
3. PVL223 VLSI Testing and Verification 3 1 2 4.5
4. PVL224 MOS Device Modeling 3 1 2 4.5
5. PCS203 Soft Computing 3 1 2 4.5
6. PEC202
Advanced Wireless Communication
Systems 3 1 2 4.5
Electives–III
S. No. Course No. Course Name L T P Cr
1. PVL331 Memory Design and Testing 3 0 0 3.0
2. PVL332 Mixed Signal Circuit Design 3 0 0 3.0
3. PVL333 System on Chip 3 0 0 3.0
4. PVL334 High Speed VLSI Design 3 0 0 3.0
5. PVL335 Fault Tolerance in VLSI 3 0 0 3.0
Electives–IV
S. No. Course No. Course Name L T P Cr
1. PVL341 Low Power Design Techniques 3 0 0 3.0
2. PVL342 RF IC Design 3 0 0 3.0
3. PVL343 Sensor Technology and MEMS 3 0 0 3.0
4. PVL344
Hardware Algorithms for Computer
Arithmetic 3 0 0 3.0
5. PVL345 Optical VLSI 3 0 0 3.0
6. PEC322 Video and Image Processing 3 0 0 3.0
Approved by the Senate in its 70th meeting held on May 25,2009
Page 3
PVL101 PHYSICS OF SEMICONDUCTOR DEVICES
L T P Cr
3 1 0 3.5
Prerequisite(s): None
Semiconductor Electronics: Physics of Semiconductor Materials, Drift Velocity, Mobility,
Scattering, Diffusion current Band Model.
Metal Semiconductor Contacts: Metal-Semiconductor System, (V-I) and (C-V) Equations for a
Shottky - Barrier - Diode, Diode Construction, Device Analysis using Surface States,
Applications as Mixer and Detectors in Microwave Region, Ohmic Contacts, Surface Effects.
PN Junctions: Step Junction, Linearly Graded Junction, (V-I) and (C-V) Characteristics,
Junction Break-down, Tunneling Effect, Avalanche Multiplication, Transient Behaviour and
Noise, Use of Junction Diode as a Rectifier, Voltage Regulator, Resistor Varactor and Fast
Recovery Diode.
Bipolar Junction Transistors: Transistor Action, Current-Voltage Equation, Output
Characteristics, Breakdown Voltage, Ebers-Moll and Gummel-Poon Model, Early Effect, Charge
Control Model, Small-Signal Transistor Model, Simulation Model.
Metal-Oxide-Silicon System: MOS structure, Energy Band Diagrams, Interface Charges,
Surface Effects, MOS Capacitors.
MOS Transistors: Basic Theory, Structure and Operation, MOSFET Parameters, Threshold
Voltage and its Control, Geometric Effects on Threshold, Ion-Implanted MOSFETs,
Complementary MOSFET, Sub-threshold Conduction, Velocity Saturation, Hot carriers, Small
Geometry Considerations.
Recommended Books 1. Sze, S.M., Physics of Semiconductor Devices, John Wiley and Sons (2008) 2nd
ed. 2. Millman, J. and Halkias, C., Integrated Electronics, Tata McGraw Hill (1972). 3. Muller, R.S. and Kamins, T.I., Device Electronics for Integrated Circuits, Wiley
2007) 3rd ed. 4. Richman P., MOS Field Effect Transistor and Integrated Circuits, John Wiley
(1973).
Approved by the Senate in its 70th meeting held on May 25,2009
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PVL102 IC FABRICATION TECHNOLOGY
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Crystal Growth and Wafer Preparation: Electronic Grade Silicon, Czochralski Crystal
Growing, Silicon Shaping, Processing Considerations.
Epitaxy: Vapour Phase Epitaxy - Basic Transport Processes and Reaction Kinetics, Doping and
Auto-Doping, Equipments and Safety Considerations, Buried Layers, Epitaxial Defects,
Molecular Beam Epitaxy - Equipment Used, Film Characteristics, SOI Structures.
Diffusion: Models of Diffusion in Solids, Fick’s laws for Diffusion, Measurement Techniques,
Fast Diffusion in Silicon, Diffusion in Polycrystalline Silicon and SiO2.
Oxidation: Growth Mechanism and Kinetics, Silicon Oxidation Model, Interface Considerations,
Orientation Dependence of Oxidation Rates Thin Oxides. Oxidation Technique and Systems -
Dry and Wet Oxidation, Plasma Oxidation, Masking Properties of SiO2.
Lithography: Optical Lithography - Optical Resists, Contact and Proximity Printing, Projection
Printing, Electron Lithography - Resists, Mask generation, Electron Optics - Roaster Scan and
Vector Scan, variable beam shape, X-ray lithography - Resists and Printing, X-ray sources and
masks, Ion-Lithography.
Etching: Reactive plasma etching, AC and DC plasma excitation, plasma properties, chemistry
and surface interactions, feature size control and an isotropic etching, ion enhanced and induced
etching, properties of etch processes. Reactive - Ion - Beam – Etching, Specific etch processes:
PolySi/Polycide, Trench etching, SiO2 and Si3N4.
Sub-micron Process Techniques; ULSI Technology; Nano-Fabrication.
Recommended Books 1. Sze, S.M., VLSI Technology, Tata McGraw Hill (2008). 2. Plummer, J.D., Deal M.D. and Griffin P.B., VLSI Technology: Fundamentals,
Practice, and Modeling, Prentice Hall (2000). 3. Nagchodhari, D., Principles of Microelectronics Technology, A H Wheeler 998). 4. Gandhi, S.K., VLSI Fabrication Principles, John Wiley (2003) 2nd ed.
Approved by the Senate in its 70th meeting held on May 25,2009
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PVL103 DIGITAL VLSI DESIGN
L T P Cr
3 1 2 4.5
Prerequisite(s): None
Physics and Modeling of MOSFETs: Basic MOSFET Characteristics – Threshold Voltage,
Body Bias concept, Current-Voltage Characteristics – Square-Law Model, MOSFET Modeling –
Drain-Source Resistance, MOSFET Capacitances, Geometric Scaling Theory – Full-Voltage
Scaling, Constant-Voltage Scaling.
Fabrication and Layout of CMOS Integrated Circuits: Overview of Integrated Circuit
Processing – Oxidation, Photolithography, Self-Aligned MOSFET, Isolation and Wells –
LOCOS, Trench Isolation, CMOS Process flow, Mask design and Layout – MOSFET
Dimensions, Design Rules, Latch-up.
CMOS Inverter: Basic Circuit and DC Operation – DC Characteristics, Noise Margins, Layout
considerations, Inverter Switching Characteristics – Switching Intervals, High-to-Low time, Low-
to-High time, Maximum Switching Frequency, Transient Effects on the VTC, RC Delay
Modeling, Elmore Delay, Output Capacitance, Inverter Design – DC Design, Transient Design,
Driving Large Capacitive Loads.
Switching Properties of MOSFETs: nMOSFET/ pMOSFET Pass Transistors, Transmission
Gate Characteristics, MOSFET Switch Logic, TG-based Switch Logic, D-type Flip-Flop.
Static CMOS Logic Elements: Complex Logic Functions, CMOS NAND Gate, CMOS NOR
Gate, Complex Logic Gates, Exclusive OR and Equivalence Gates, Adder Circuits, Pseudo-
nMOS Logic Gates, Schmitt Trigger Circuits, SR and D-type Latch, CMOS SRAM Cell, Tri-state
Output Circuits.
Power Dissipation in CMOS Digital Circuits: Dynamic Power Dissipation – Switching Power
Dissipation, Short Circuit Power Dissipation, Glitching Power Dissipation, Static Power
Dissipation – Diode Leakage Current, Subthreshold Leakage Current.
Dynamic Logic Circuit Concepts and CMOS Dynamic Logic Families: Charge Leakage,
Charge Sharing, Dynamic RAM Cell, Bootstrapping, Clocked-CMOS, Pre-Charge/ Evaluate
Logic, Domino Logic, Multiple-Output Domino Logic, NORA Logic, Single-Phase Logic.
Effects of Technology Scaling on CMOS Logic Styles: Trends and Limitations of CMOS
Technology Scaling – MOSFET Scaling Trends, Challenges of MOSFET Scaling – Short-
Channel Effects, Subthreshold Leakage Currents, Dielectric Breakdown, Hot Carrier effects, Soft
Errors, Velocity Saturation and Mobility Degradation, DIBL, Scaling down Vdd/Vth ratio.
CMOS Differential Logic Styles: Dual-Rail Logic, CVSL, CPL, DPL, DCVS, MCML.
Issues in Chip Design: ESD Protection, On-Chip Interconnects – Line Parasitics, Modeling of
the Interconnect Line, Clock Distribution, Input-Output circuits.
Approved by the Senate in its 70th meeting held on May 25,2009
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Laboratory Work Familiarization with schematic and layout entry using Mentor/ Cadence/ Tanner Tools, circuit
simulation using SPICE; DC transfer Characteristics of Inverters, Transient response, Calculating
propagation delays, rise and fall times, Circuit design of inverters, complex gates with given
constraints; Circuit Simulation and Performance Estimation using SPICE; Layouts of Inverters
and Complex gates, Layout Optimization, Design Rule Check (DRC), Electrical Rule Check
(ERC), Comparison of Layout Vs. Schematics, Circuit Extraction.
Recommended Books
1. Kang, S. and Leblebici, Y., CMOS Digital Integrated Circuits – Analysis and Design, Tata McGraw Hill (2008) 3rd ed.
2. Weste, N.H.E. and Eshraghian, K., CMOS VLSI Design: A Circuits and Systems Perspective, Addision Wesley (1998) 2nd ed.
3. Rabaey, J.M., Chandrakasen, A.P. and Nikolic, B., Digital Integrated Circuits – A Design Perspective, Pearson Education (2007) 2nd ed.
4. aker, R.J., Lee, H. W. and Boyce, D. E., CMOS Circuit Design, Layout and Simulation, Wiley - IEEE Press (2004) 2nd ed.
5. Weste, N.H.E., Harris, D. and Banerjee, A., CMOS VLSI Design, Dorling Kindersley (2006) 3rd ed.
Approved by the Senate in its 70th meeting held on May 25,2009
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PVL104 CAD SYSTEMS ENVIRONMENT
L T P Cr
3 1 2 4.5
Prerequisite(s): None
Introduction: Familiarity with UNIX/LINUX operating systems.
Operating System: Basic Concept of Operating System: Evolution of operating system,
fundamental of operating system functions, multiprogramming, multiprocessing, time sharing
systems and real time systems.
Linux: About Linux, Brief History, Linux, Distributions, Using the Emacs Editor, Using the vi
Editor, Using the Pico Editor, Introduction to Users and Groups Essentials of Effective User,
Group, and Password Management, Introduction to the Linux Kernel, Using Kernel Modules,
Compiling the Linux Kernel, Installing the Linux Kernel, File System, Disk Geometry.
Shell Programming: Familiarity with different shells, UNIX Utilities like tar, make, yacc, lex,
lint, debugger etc.
Scripting Languages: Brief Introduction and overview of Perl, Tcl/tk.
SystemC: Introduction to SystemC, Fundamentals of SystemC, Models of Computation,
Classical Hardware Modeling in SystemC, Functional Modeling, Parameterized Modules and
Channels, Interface and Channel Design, Transaction-Level Modeling, Communication
Refinement, Test benches, Tracing and Debugging, Future of SystemC.
Laboratory Work UNIX/LINUX - Familiarity with different shells, UNIX/LINUX Utilities like tar, make, lex, lint,
etc. Exercises of Perl and Tcl/tk, File Formats - .tgz, .tar; Programming exercises using SystemC.
Recommended Books 1. Kernighan, B.W. and Pike, R., UNIX Programming Environment, Dorling
Kingersley Hall (2006). 2. Lidie, S.O. and Walsh, N., Mastering Perl/Tk, O'Reilly Media Inc. (2002). 3. Grötker, T., Liao, S., Martin, G. and Swan, S., System Design with SystemC,
Springer (2002). 4. Silberschatz, A., Galvin, P.B. and Gagne, G., Operating System Concepts, Wiley
(2008) 8th ed. 5. Flynt, C., Tcl/Tk A Developer's Guide, Morgan Kaufmann (2003). 6. Stallings, W., Operating Systems: Internals and Design Principles, Prentice
Hall (2008) 6th ed.
Approved by the Senate in its 70th meeting held on May 25,2009
Page 8
PVL105 LOGIC SYNTHESIS USING HDLS
L T P Cr
3 1 2 4.5
Prerequisite(s): None
Introduction: Concepts of Hardware Description Languages and logic synthesis.
Logic synthesis: Design cycle, types of synthesizers, design testing and verification, design
optimization techniques, technology mapping, VHDL design hierarchy, objects, types and
subtypes, design organization, VHDL design cycle.
RTL Level Design: RTL design stages, VHDL description of the RTL design.
Combinational Logic: Design units, entities and architectures, simulation and synthesis model,
signals and ports, simple signal assignments, conditional signal assignments, selected signal
assignment.
Types: Synthesizable types, standard types, standard operators, scalar types, records, arrays,
attributes.
Operators: standard operators, operator precedence, Boolean operators, comparison operators,
arithmetic operators, concatenation operators.
Package std_logic_arith: std_logic_arith package, making the package visible, contents of
std_logic_arith, resize functions, operators, shift functions, type conversions, constant values,
mixing types in expressions, numeric packages.
Sequential VHDL: Processes, signal assignments, variables, if statements, case statements.
Registers: Simulation and synthesis model of register, register templates, clock types, gated
registers, resettable registers, simulation model of asynchronous reset, asynchronous reset
templates, registered variables.
Hierarchy: Role of components, using components, component instances, component
declaration, Configuration specifications, default binding, binding process, component packages,
generate statements.
Sub programs: Functions, type conversions, procedures, declaring subprograms.
Test Benches: Test benches, verifying responses, clocks and resets, printing response values,
reading data files, reading standard types, error handling.
Libraries: Standard libraries, organising files, library names, library work, incremental
compilation.
Basic principles of Combinational logic design, sequential logic design, arithmetic circuit design
and control logic design.
Approved by the Senate in its 70th meeting held on May 25,2009
Page 9
Laboratory Work Modeling and simulation of all VHDL constructs using ModelSim, their testing by modeling and
simulating test benches, Logic Synthesis using FPGA Advantage, Mapping on FPGA Boards.
Recommended Books 1. Naylor, D. and Jones, S., VHDL: A Logic Synthesis Approach, Springer (1997). 2. Rushton, A., VHDL for Logic Synthesis, Wiley (1998) 2nd Ed. 3. Ashenden, P., The Designer’s Guide To VHDL, Elsevier (2008) 3rd Ed. 4. Bhaskar, J., A VHDL Primer, Pearson Education/ Prentice Hall (2006)3rd Ed.
Approved by the Senate in its 70th meeting held on May 25,2009
Page 10
PVL201 ANALOG IC DESIGN
L T P Cr
3 1 4 5.5
Prerequisite(s): None
Basic MOS Device Physics: MOS IV Characteristics, Second order effects, Short-Channel
Effects, MOS Device Models, Review of Small Signal MOS Transistor Models, MOSFET
Noise.
Analog MOS Process: Analog CMOS Process (Double Poly Process), Digital CMOS Process
tailored to Analog IC fabrication, Fabrication of active devices, passive devices and
interconnects, Analog Layout Techniques, Symmetry, Multi-finger transistors, Passive devices:
Capacitors and Resistors, Substrate Coupling, Ground Bounce.
Single Stage Amplifiers: Common Source Stage, Source Follower, Common Gate Stage,
Cascode, Folded Cascode.
Differential Amplifier: Single ended and Differential Operation, Qualitative and Quantitative
Analysis of Differential pair, Common Mode response, Gilbert Cell.
Current Sources and Mirrors: Current Sources, Basic Current Mirrors, Cascode Current
Mirrors, Wilson Current Mirror, Large Signal and Small-Signal analysis.
Frequency Response of Amplifiers: Miller Effect, Association of Poles with nodes,
Frequency Response of all single stage amplifiers.
Voltage References: Different Configurations of Voltage References, Major Issues, Supply
Independent Biasing, Temperature-Independent References.
Feedback: General Considerations, Topologies, Effect of Loading.
Operational Amplifier: General Considerations, Theory and Design, Performance Parameters,
Single-Stage Op Amps, Two-Stage Op Amps, Design of 2-stage MOS Operational Amplifier,
Gain Boosting, Comparison of various topologies, slew rate, Offset effects, PSRR.
Stability and Frequency Compensation: General Considerations, Multi-pole systems, Phase
Margin, Frequency Compensation, Compensation Techniques.
Noise: Noise Spectrum, Sources, Types, Thermal and Flicker noise, Representation in circuits,
Noise Bandwidth, Noise Figure.
Switched-Capacitor Circuits: Sampling Switches, Speed Considerations, Precision
Considerations, Charge Injection Cancellation, Switched-Capacitor Amplifiers, Switched-
Capacitor Integrator, Switched-Capacitor Common-Mode Feedback.
Non Linearity and Mismatch: Nonlinearity of Differential Circuits, Effect of Negative
Feedback, Capacitor Nonlinearity, Linearization Techniques, Offset Cancellation Techniques,
Reduction of Noise by Offset Cancellation.
Laboratory Work
Approved by the Senate in its 70th meeting held on May 25,2009
Page 11
Review of Mentor Tools; Analysis of Various Analog Building Blocks such as, Current and
Voltage References/Sources, Current Mirrors, Differential Amplifier, Output Stages; Design
and Analysis of Op-Amp (Closed loop and open loop) and its Characterization, Switched-
Capacitor Integrator; Analog Layout Constraints, Layout Designs
and Analysis.
Recommended Books 1. Razavi, B., Design of Analog CMOS Integrated Circuits, Tata McGraw Hill
(2008). 2. Gregorian, R. and Temes, G.C., Analog MOS Integrated Circuits for Signal
Processing, John Wiley (2004). 3. Allen, P.E. and Holberg, D.R., CMOS Analog Circuit Design, Oxford
University Press (2002) 2nd ed. 4. Johns, D.A. and Martin, K., Analog Integrated Circuit Design, John Wiley
(2008). 5. Gray, P.R., Hurst, P.J., Lewis, S.H., and Meyer, R.G., Analysis and Design of
Analog Integrated Circuits, John Wiley (2001) 5th ed. 6. Hastings, A., The Art of Analog Layout, Prentice Hall (2005).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 12
PVL202 EMBEDDED SYSTEMS
L T P Cr
3 0 2 4.0
Prerequisite(s): None
Embedded Processing: Introduction to Embedded Computing, Difference between Embedded
and General-Purpose Computing, Characterizing Embedded Computing, Design Philosophies,
RISC, CISC, VLIW versus superscalar, VLIW versus DSP Processors, Role of the Compiler,
Architectural structures, The datapath, Registers and Clusters, Memory Architecture, Branch
architecture, Speculation and prediction, Prediction in the embedded domain, Register File
Design, Pipeline Design, the control unit, control registers.
Embedded Processors: Microprocessor versus Microcontroller architecture, ARM architecture,
Embedded Cores, Soft and Hard Cores, Architecture of Configurable Microblaze soft core,
Instruction set, Stacks and Subroutines, Microblaze Assembly Programming, Input-Output
interfacing, GPIO, LCD interfacing, Peripherals, DDR Memory, SDRAM, Microblaze interrupts,
Timers, Exceptions, Bus Interfacing, DMA, On-chip Peripheral bus (OPB), OPB Arbitration,
OPB DMA.
RTOS and Application design: Programming language choices, Traditional C and ANSI C,
C++ and Embedded C++, matlab, Embedded JAVA, Embedded C extensions, Real time
operating systems, Embedded RTOS, Real time process scheduling, structure of real time
operating system, Memory management in Embedded operating system, operating system
overhead, interprocess communication mechanisms, File systems in Embedded devices, Different
types of locks, Semaphores, Application studies with Vxworks, Montavista Linux etc.
System Design and Simulation: System-on-a-Chip (SoC), IP Blocks and Design Reuse,
Processor Cores and SoC, Non-programmable accelerators, reconfigurable logic, multiprocessing
on a chip, symmetric multiprocessing, heterogeneous multiprocessing, use of simulators,
Compilers, Loaders, Linkers, locators, assemblers, Libraries, post run optimizer, debuggers,
profiling techniques, binary utilities, linker script, system simulation, In Circuit Emulation,
Validation and verification, Hardware Software partitioning, Co-design.
Laboratory Work Embedded System design using Embedded Development Kit Software and implementation on
FPGA hardware, Practicals on Xilkernel, Vxworks and montavista Linux Real Time Operating
Platforms.
Recommended Books 1. Wolf, W., High-Performance Embedded Computing Architectures, Applications,
and Methodologies, Morgan Kaufman Publishers (2007). 2. Heath, S., Embedded Systems Design, Elsevier Science (2003). 3. Fisher, J.A., Faraboschi, P. and Young, C., Embedded Computing - A VLIW
Approach to Architecture, Compilers and Tools, Morgan Kaufman (2005). 4. Simon, D.E., An Embedded Software Primer, Dorling Kindersley (2005).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 13
PVL203 VLSI SIGNAL PROCESSING
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Introduction: Introduction to DSP Systems, Terminating and Non-Terminating, Representation
of DSP programs, Data Flow graphs (DFGs), Single rate and multi rate DFGs, Iteration bound,
Loop, Loop Bound, Iteration rate, Critical loop, Critical path, Area-Speed-Power trade-offs,
Precedence constraints, Acyclic Precedence graph, Longest Path Matrix (LPM) and Minimum
Cycle Mean (MCM) Algorithms, Pipelining and parallel processing of DSP Systems, Low Power
Consumption.
Algorithmic Transformations: Retiming, Cut-set retiming, Feed-Forward and Feed-Backward,
Clock period minimization, register minimization, Unfolding, Sample period reduction, Parallel
processing, Bit-serial, Digit-serial and Parallel Architectures of DSP Systems, Folding, Folding
order, Folding Factor, Folding Bi-quad filters, Retiming for folding, Register Minimization
technique, Forward Backward Register Allocation technique.
Systolic Architecture Design and Fast Convoltuion: Systolic architecture design methodology,
Projection vector, Processor Space vector, Scheduling vector, Hardware Utilization efficiency,
Edge mapping, Design examples of systolic architectures, Cook-Toom Algorithm and Modified
Cook-Toom Algorithm, Wniograd Algorithm and Modified Winograd Algorithm, Iterated
Convolution, Cyclic Convolution.
Algorithm Strength Reduction: Introduction, Parallel FIR filters, Polyphase decomposition,
Fast FIR filters Algorithms, Discrete Cosine Transform and Inverse Discrete Cosine Transform,
Algorithm-Architecture Transformation, DIT Fast DCT, Pipelined and Parallel Recursive and
Adaptive Filters, Look-Ahead Computation, Look-Ahead Pipelining, Decompositions, Clustered
Look-Ahead Pipelining, Scattered Look-Ahead pipelining, Parallel processing in IIR Filters,
Combining Pipelining and Parallelism.
Scaling and Round-off Noise: Introduction, State variable description of Digital Systems,
Scaling and Round-off Noise Computation, Slow-Down Approach, Fixed-point digital filter
implementation.
Recommended Books: 1. Parhi, K.K., VLSI Digital Signal Processing Systems: Design and
Implementation, John Wiley (2007). 2. Oppenheim, A.V. and Schafer, R.W., Discrete-Time Signal Processing, Prentice
Hall (2009) 2nd ed. 3. Mitra, S.K., Digital Signal Processing. A Computer Based Approach, McGraw
Hill (2007)3rd ed. 4. Wanhammar, L., DSP Integrated Circuits, Academic Press (1999).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 14
PVL211 VLSI ARCHITECTURES
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Complex Instruction Set Computers (CISC): Instruction Set, Characteristics and Functions,
Addressing Modes, Instruction Formats, Architectural Overview, Processor Organization,
Register Organization, Instruction Cycle, Instruction Pipelining, Pentium Processor, PowerPC
Processor.
Reduced Instruction Set Computers (RISC): Instruction execution Characteristics, Register
Organization, Reduced Instruction Set, Addressing Modes, Instruction Formats, Architectural
Overview, RISC Pipelining, Motorola 88510, MIPS R4650, RISC Vs. CISC.
Pipeline Processing: Basic Concepts, Classification of Pipeline Processors, Instruction and
Arithmetic Pipelining: Design of Pipelined Instruction Units, Pipelining Hazards and Scheduling,
Principles of Designing Pipelined Processors.
Memory Architectures: Memory hierarchy design, Multiprocessors, thread level parallelism and
multi-core architectures, I/O buses. Arithmetic: Fixed point, Floating point and residue
arithmetic, Multiply and Divide Algorithms.
Issues in arithmetic system design, Issues in the applications (optimizing the hardware – software
interface), ASIP, reconfigurable computing, Future microprocessor architectures.
Superscaler Processors: Overview, Design Issues, PowerPC, Pentium.
Recommended Books 1. Patterson, D.A. and Hennessy, J., Computer Architecture: A Quantitative
Approach, Morgan Kaufmann (2003)3rd ed. 2. Stallings, W., Computer Organization and Architecture: Designing for
Performance, Prentice Hall (2003) 7th ed. 3. Patterson, D.A. and Hennessy,J., Computer Organization and Design,
Elsevier(2004) 3rd ed. 4. Flynn, M.J. and Oberman, S.F., Advanced Computer Arithmetic Design, Wiley
(2001). 5. Parhami, B., Computer Arithmetic Algorithms and Hardware Design, Oxford
(2000).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 15
PVL212 PHYSICAL DESIGN AUTOMATION
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Introduction to VLSI Physical Design Automation, use of VLSI CAD tools, Algorithmic Graph
Theory, computational Complexity and ROBDD; Partitioning and placement: KL algorithm, FM
algorithm etc.
Floor planning and Pin Assignment, Placement, Layout styles, Discrete methods in global
placement, Timing-driven placement, Routing: Global routing, detailed routing, graph models,
Line Search, Maze Routing, Channel routing.
Performance issues in circuit layout, delay models, timing driven placement, timing driven
routing, Via Minimization, Over the Cell Routing - Single layer and two-layer routing, Clock and
Power Routing.
Compaction, compaction algorithms, Physical Design Automation of FPGAs.
High Level Synthesis: Introduction to HDL, HDL to DFG, operation scheduling: constrained and
unconstrained scheduling, ASAP, ALAP, List scheduling, Force directed scheduling, operator
binding; Static Timing Analysis: Delay models, setup time, hold time, cycle time, critical paths,
Topological vs. logical timing analysis, False paths, Arrival time (AT), Required arrival Time
(RAT), Slacks.
Recommended Books 1. Sherwani, N., Algorithms for VLSI Physical Design Automation, Springer
(2005) 3rd ed. 2. Gerez S.H., Algorithms for VLSI Design Automation, John Wiley (1998). 3. Sarrafzadeh, M. and Wong, C.K., An Introduction to VLSI Physical Design,
McGraw Hill (1996). 4. Trimberger, S.M., An Introduction to CAD for VLSI, Kluwer (1987).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 16
PVL213 NANOELECTRONICS
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Shrink-down approaches: Introduction to Nanoscale Systems, Length energy and time scales,
Top down approach to Nanolithography, CMOS Scaling, Limits to Scaling, System Integration
Limits - Interconnect issues, etc.
Overview of Nanoelectronics and Devices: The Nano-scale MOSFET, FinFETs, Vertical
MOSFETs, Resonant Tunneling Transistors, Single Electron Transistors, New Storage devices,
Optoelectronic and Spin electronics Devices.
Basics of Quantum Mechanics: History of Quantum Mechanics, Schrödinger Equation,
Quantum confinement of electrons in semiconductor nano structures, 2D confinement (Quantum
Wells), Density of States, Ballistic Electron Transport, Coulomb Blockade, NEGF Formalism,
Scattering.
Leakage in Nanometer CMOS Technologies: Taxonomy of Leakage: Introduction, Sources,
Impact and Solutions. Leakage dependence on Input Vector: Introduction, Stack Effect, Leakage
reduction using Natural Stacks, Leakage reduction using Forced Stacks. Power Gating and
Dynamic Voltage Scaling: Introduction, Power Gating, Dynamic Voltage Scaling, Power Gating
methodologies.
Nano-Fabrication and Characterization: Fabrication: Photolithography, Electron-beam
Lithography, Advanced Nano-Lithography, Thin-Film Technology, MBE, CVD, PECVD.
Characterization: Scanning Probe Microscopy, Electron Microscopy (TEM, SEM), Photon
Spectroscopy, Nano Manipulators.
Future Aspects of Nanoelectronics: Molecular Electronics: Molecular Semiconductors and
Metals, Electronic conduction in molecules, Molecular Logic Gates, Quantum point contacts,
Quantum dots and Bottom up approach, Carbon Nano-tube and its applications, Quantum
Computation and DNA Computation.
Overview of Organic Electronics: OLEDs, OLETs, Organic Solar Cells.
Recommended Books
1. Lundstorm, M. and Guo, J., Nanoscale Transistors – Device Physics, Modeling
and Simulation, Springer (2006).
2. Bhushan, B., Handbook of Nanotechnology, Springer (2007) 2nd
ed.
3. Beenaker, C.W.J., and Houten, V., Quantum Transport in Semiconductor
Nanostructures in Solid State Physics, Ehernreich and Turnbell, Academic Press
(1991).
4. Fahrner, W.R., Nanotechnology and Nanoelectronics: Materials, Devices and
Measurement Techniques, Springer (2006).
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Page 17
5. Ferry, D., Transport in Nanostructures, Cambridge University Press (2008).
6. Mitin, V.V. and Kochelap, V.A., Introduction to Nanoelectronics: Science,
Nanotechnology, Engineering and Application, Cambridge Press (2008).
7. Draoman, M. and Dragoman, D., Nanoelectronics: Principles and Devices,
Artech House (2008).
8. Goddard, W., Brenner, D., Lyshevski, S.E. and Iafrate, G., Handbook of
Nanoscience, Engineering and Technology, CRC Press (2007) 2nd
ed.
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PVL214 PROCESS AND DEVICE CHARACTERIZATION
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Physical Characterization: Thin Film Thickness- Measurements-ellipsometry, surface profiling,
spectrophotometry, FTIR.
Critical Dimension Measurements: Optical microscope, Scanning Electron Microscope,
Transmission Electron Microscope.
Material and Impurity Characterization: SIMS, XRD, EDAX.
Electrical Characterization: Four-probe technique, Hall Effect, sheet resistance C-V
measurements, DLTS, Carrier lifetime, impurity profiling, I-V measurements.
Process and SPICE model parameter Extraction: SPICE BSIM3 model parameter extraction
and optimization, Intrinsic Most and extrinsic, parasitic element, EKV model, Gummel-Poon
model, BSIM model.
Test Structures for Process Characterization: Contact Resistors, Split Cross Bridge Resistors,
Self-aligned n+ Bridges.
Test Structures for Device Characterization: Individual MOSFETs, 4x4 MOSFET Arrays,
Capacitors.
Test Structures for Faults and Reliability Analysis: Contact Chains, Serpentine/Comb
Resistors.
Recommended Books 1. Runyan, W.R. and Shaffner, T.J., Semiconductor Measurements and
Instrumentation, McGraw-Hill (2006) 3rd ed. 2. Schroder, D.K., Semiconductor Material and Device Characterization, Wiley
(1998) 2nd ed. 3. Kane, P.F. and Larrabee, G.B., Characterization of Semiconductor Materials,
McGraw Hill (1970). 4. Ravi, K.V., Imperfections and Impurities in Semiconductor Silicon, John Wiley
(1981).
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PVL345 REAL TIME SOFTWARE AND SYSTEMS
L T P Cr
3 0 0 3.0
Prerequisite(s): Exposure to PVL104 CAD System Environment
Introduction to Real-Time System: Definition of a real-time system, Examples of real-time
system, Characteristics of real-time system, Embedded Systems Components, Fundamentals of
embedded system hardware and firmware design, Hard versus Soft Real-Time systems,
Embedded processor selection, Embedded System Revolution, Reference Model of Real-Time
Systems.
Real-Time Scheduling and Schedulability Analysis: Clock-driven scheduling, Priority-driven
scheduling of periodic tasks, Scheduling a periodic and sporadic jobs in priority-driven systems,
Function Queue Scheduling and Date Shard and Reentrancy.
Embedded Software Examples of embedded system, Characteristic and Typical Hardware Components, Embedded
Software Architectures, Round Robin, and Interrupts, Memory Architecture and Devices,
Memory Interface.
Fault Tolerance: Reliability, Failure and Faults, Failure modes, Fault prevention and Fault
tolerance, N-version programming, Software dynamic redundancy, The recovery block approach
to Software Fault Tolerance, A comparison between N-version programming and Recovery
Blocks, Dynamic Redundancy and Exceptions, Measuring and Predicting the Reliability of
software, Safety, Reliability and Dependability.
Application of Real-Time Systems: Real-Time Embedded Systems, Safety-Critical Systems,
Real-time system requirements, Real-time system design, The Real-Time System production
process, Performance estimation and optimization.
Recommended Books 1. Shaw, A.C., Real Time Systems and Software, John Wiley (2001). 2. Liu, J.W.S., Real Time Systems, Dorling Kindersley (2008). 3. Khrisna, C.M., Real Time Systems, McGraw Hill (1997). 4. Cheng, A.M.K, Real- Time Systems: Scheduling, Analysis and Verification, John
Wiley (2002).
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PVL221 VLSI SUBSYSTEM DESIGN
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3 1 2 4.5
Prerequisite(s): Exposure to PVL103 Digital VLSI Design
Introduction: Review of Transistor, Inverter Analysis, CMOS Process and Masking Sequence,
Layer Properties and Parasitic Estimation.
VLSI Design Flow, Design Methodologies, Abstraction Levels.
Design of Data Processing Elements: Adder Architectures, Multiplier Architectures, Counter
Architectures, ALU Architectures, Design of Storage Elements: Latches, Flip-Flops, Registers,
Register Files.
Design of Control Part: Moore and Mealy Machines, PLA Based Implementation, Random
Logic Implementation, Micro-programmed Implementation.
Structuring of Logic Design: PLA Design, PLA Architectures, Gates Array Cell Design,
Concept of Standard Cell Based Design, Cell Library Design.
Memory Design: SRAM cell, Various DRAM cells, RAM Architectures, Address Decoding,
Read/Write Circuitry, Sense Amplifier and their Design, ROM Design.
Clocking Issues: Clocking Strategies, Clock Skew, Clock Distribution and Routing, Clock
Buffering, Clock Domains, Gated Clock, Clock Tree.
Synchronization Failure and Meta-stability.
Laboratory Work Review of schematic and layout tools using Cadence Univ. tools, circuit design and simulation
using SPICE. Use of Design Rule Check (DRC), Electrical Rule Check (ERC), Comparison of
Layout Vs. Schematic, Schematic and Layouts design of Sub-system blocks, their
characterization, and optimization.
Recommended Books 1. Weste, N.H.E. and Eshragian, K., Principles of CMOS VLSI Design - A
Systems Prespective, Addison Wesley (1994) 3rd ed. 2. Rabaey, J.M., Chandrakasan, A., and Nikolic, B., Digital Integrated Circuits - A
Design Perspective, Pearson Education (2008) 3rd ed. 3. Wolf, W., Modern VLSI Design, Prentice Hall (2008) 3rd ed. 4. Mead, C. and Conway, L., Introduction to VLSI Systems, B.S. Publisher (1980)
2nd ed. 5. Uyemura, J.P., Circuit design for CMOS VLSI, Springer (2005) 2nd ed.
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PVL222 ASICS AND FPGAS
L T P Cr
3 1 2 4.5
Prerequisite(s): None
Overview: Digital system design options and tradeoffs, Design methodology and technology
overview, High Level System Architecture and Specification: Behavioral modeling and
simulation.
Review HDLs: Hardware description languages, combinational and sequential design, state
machine design, synthesis issues, test benches.
FPGA Architectures And Technologies: FPGA Architectural options, granularity of function
and wiring resources, coarse vs. fine grained, vendor specific issues (emphasis on Xilinx).
Logic Block Architecture: FPGA logic cells, timing models, power dissipation.
I/O block architecture: Input and Output cell characteristics, clock input, Timing, Power
dissipation. Programmable interconnect - Partitioning and Placement, Routing resources, delays.
Applications: Embedded system design using FPGAs, DSP using FPGAs, Dynamic architecture
using FPGAs, reconfigurable systems, application case studies.
ASICs: Types of ASICs, ASIC design flow, Programmable ASICs, Anti-fuse, SRAM, EPROM,
EEPROM based ASICs, Programmable ASIC logic cells and I/O cells, Programmable
interconnects.
ASIC Methodologies (classical) and ASIC Methodologies (aggressive).
Laboratory Work Simulation/implementation exercises of combinational, sequential and DSP kernels on
Xilinx/FPGA boards.
Recommended Books 1. Smith, M.J.S., Application Specific Integrated Circuits, Pearson Education
(2006). 2. Wolf, W., FPGA Based System Design, Morgan Kaufmann (2007). 3. Ashenden, P., Digital Design using VHDL, Prentice Hall (2008). 4. Maxfield, C., The Design Warriors’s Guide to FPGAs, Elsevier (2004).
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PVL223 VLSI TESTING AND VERIFICATION
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3 1 2 4.5
Prerequisite(s): None
Faults: Physical Faults and their modeling; Stuck-at faults; Bridging Faults; Fault collapsing,
Fault Simulation; Deductive, Parallel and Concurrent Fault Simulation; Critical Path Tracing.
ATPG for Combinational Circuits: D-Algorithm, Boolean Difference, PODEM; Random,
Exhaustive and Weighted Random Test Pattern Generation; Aliasing and its effect on Fault
Coverage.
PLA Testing: Cross Point Fault Model and Test Generation.
Memory Testing: Permanent, Intermittent and Pattern Sensitive Faults; Marching Tests; Delay
Faults;
ATPG for Sequential Circuits; Time Frame Expansion; Controllability and Observability Scan
Design, BILBO, Boundary Scan for Board level Testing; BIST and Totally Self Checking
Circuits; System Level diagnosis.
Introduction: Concept of Redundancy, Spatial Redundancy, Time Redundancy, Error Correction
Codes; Reconfiguration Techniques; Yield Modeling Reliability and effective area utilization.
Scope of testing and verification in VLSI design process, Issues in test and verification of
complex chips, embedded cores and SoCs.
Verification: Design verification techniques based on simulation, analytical and formal
approaches, Functional verification, Timing verification, Formal verification, Basics of
equivalence checking and model checking, Hardware emulation.
Laboratory Work Logic Simulation, Logic level diagnosis, ATPG, Implementation of BIST for a given module and
system level diagnosis using DFT tools.
Recommended Books 1. Abramovici, M., Breuer, M. A. and Friedman, A.D., Digital Systems Testing
and Testable Design, Jaico Publishing House (2001). 2. Rashinkar, P., Paterson and Singh, L., System-on-a-Chip Verification-
Methodology and Techniques, Kluwer Academic (2001). 3. Bushnell, M. and Agrawal, V.D., Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits, Kluwer Academic (2000). 4. Kropf, T., Introduction to Formal Hardware Verification, Springer Verlag
(1999).
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Approved by the Senate in its 70th meeting held on May 25,2009
Page 24
PVL224 MOS DEVICE MODELING
L T P Cr
3 1 2 4.5
Prerequisite(s): Exposure to PVL101 Physics of Semiconductor Devices
Semiconductor Fundamentals: Poisson and Continuity Equations, Recombination, Equilibrium
carrier concentrations (electron statistics, density of states, effective mass, bandgap narrowing),
Review of PN and MS diodes.
Quantum Mechanics Fundamentals: Basic Quantum Mechanics, Crystal symmetry and band
structure, 2D/1D density of states, Tunneling.
Modeling and Simulation of Carrier Transport: Carrier Scattering (impurity, phonon, carrier-
carrier, remote/interface), Boltzmann Transport Equation, Drift-diffusion.
MOS Capacitors: Modes of operation (accumulation, depletion, strong/weak inversion),
Capacitance versus voltage, Gated diode, Non-ideal effects (poly depletion, surface charges),
High field effects (tunneling, breakdown).
MOSFET Modeling: Introduction Interior Layer, MOS Transistor Current, Threshold Voltage,
Temperature Short Channel and Narrow Width Effect, Models for Enhancement, Depletion Type
MOSFET, CMOS Models in SPICE, Long Channel MOSFET Devices, Short Channel MOSFET
Devices.
Parameter Measurement: General Methods, Specific Bipolar Measurement, Depletion
Capacitance, Series Resistances, Early Effect, Gummel Plots, MOSFET: Long and Short Channel
Parameters, Statistical Modeling of Bipolar and MOS Transistors.
Advanced Device Technology: SOI, SiGe, strained Si, Alternative oxide/gate materials,
Alternative geometries (raised source/drain, dual gate, vertical, FinFET), Memory Devices
(DRAM, Flash).
Sub-micron and Deep sub-micron Device Modeling.
Laboratory Work SPICE simulations, Study of SPICE Models, Extraction of Model Parameters for various devices
in different technologies.
Recommended Books 1. Tsividis, Y., Operation and Modeling of the MOS Transistor, Oxford University
Press, (2008) 2nd ed. 2. Sze, S.M., Physics of Semiconductor Devices, Wiley (2008). 3. Muller, R.S., Kamins, T.I., and Chan, M., Device Electronics for Integrated
Circuits, John Wiley (2007) 3rd ed. 4. Taur, Y. and Ning, T.H., Fundamentals of Modern VLSI Devices, Cambridge University
Press (2009).
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Page 25
5. Massobrio, G. and Antognetti, P., Semiconductor Device Modeling, McGraw Hill (1998).
6. Dieter, K.S., Semiconductor Material and Device Characterization, John Wiley (2006) 3rd ed.
7. Tor, A., Fjeldly, T.Y., and Michael, S., Introduction to Device Modeling and Circuit Simulation, John Wiley (1998).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 26
PVL331 MEMORY DESIGN AND TESTING
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3 0 0 3.0
Prerequisite(s): None
Introduction to Memory Chip Design: Basics of Semiconductor Memory, Internal Organization
of Memory Chips, Memory Cell Array, Peripheral Circuit, I/O Interface Categories of Memory
Chip, History of Memory-Cell Development, Architectures of memory cell: SRAM Cell, DRAM
Cell Trends in Non-Volatile Memory Design and Technology, Ferroelectric memory, Basic
Operation of Flash Memory Cells, Advances in Flash-Memory Design and Technology.
Basics of RAM Design and Technology: Devices, NMOS Static Circuits, NMOS Dynamic
Circuits, CMOS Circuits, Basic Memory Circuits, Scaling Law.
DRAM Circuits: High-Density Technology, High-Performance Circuits, Catalog Specifications
of the Standard DRAM, Basic Configuration and Operation of the DRAM Chip, Chip
Configuration, Address Multiplexing, Fundamental Chip, Multi-divided Data Line and Word
Line, Read and Relevant Circuits, Write and Relevant Circuits, Refresh-Relevant Circuits,
Redundancy Techniques, On-Chip Testing Circuits, High Signal-to-Noise Ratio DRAM Design
and Technology, Trends in High S/N Ratio Design, Data-Line Noise Reduction, Noise Sources.
On-Chip Voltage Generators: Substrate-Bias Voltage (VBB) Generator, Voltage Up-Converter,
Voltage Down-Converter, Half-VDD Generator, Examples of Advanced On-Chip Voltage
Generators.
High-Performance Subsystem Memories: Hierarchical Memory Systems, Memory-Subsystem
Technologies, High-Performance Standard DRAMs, Embedded Memories.
Low-Power Memory Circuits: Sources and Reduction of Power Dissipation in a RAM
Subsystem and Chip, Low-Power DRAM Circuits, Low-Power SRAM Circuits.
Ultra-Low-Voltage Memory Circuits: Design Issues for Ultra-Low-Voltage RAM Circuits,
Reduction of the Subthreshold Current, Stable Memory-Cell Operation, Suppression of, or
Compensation for, Design Parameter Variations, Power-Supply Standardization, Ultra-Low-
Voltage DRAM Circuits, Ultra-Low-Voltage SRAM Circuits, Ultra-Low-Voltage SOI Circuits.
Radiation Effects in semiconductor memories.
Recommended Books
1. Itoh, K., VLSI Memory Chip Design, Springer (2006). 2. Sharma, A. K., Semiconductor Memories: Technology, Testing and Reliability,
Wiley- IEEE press (2002). 3. Adams, R. D., High performance Memory Testing: Design Principles, Fault
Modeling and Self-Test, Springer (2002). 4. Sharma, A. K., Advanced Semiconductor Memories: Architecture, Design and
Applications, John Wiley (2002).
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Page 27
5. Prince, B., Semiconductor Memories: A handbook of Design, Manufacture and Application, John Wiley (1996) 2nd ed.
6. Scot, J., Ferroelectric Memories, Springer (2000).
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PVL332 MIXED SIGNAL CIRCUIT DESIGN
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3 0 0 3.0
Prerequisite(s): Exposure to PVL-201 Analog IC Design
Introduction: Device Models, IC Process for Mixed Signal, Concepts of MOS Theory.
Comparators: Circuit Modeling, Auto Zeroing Comparators, Differential Comparators,
Regenerative Comparators, Fully Differential Comparators, Latched Comparator.
Data Converters: Requirements, Static and Dynamic Performance, SNR and BER, DNL, INL.
High Speed A/D Converter Architectures: Flash, Folding, Interpolating, Piplelined.
High Speed D/A Converter Architectures: Nyquist-Rate D/A Converters, Thermometer Coded
D/A Converters, Binary Weighted D/A Converters.
Design of multi channel low level and high level data acquisition systems using ADC/DAC, SHA
and Analog multiplexers, Designing of low power circuits for transducers.
Sigma-Delta Data Converter Architectures: Programmable Capacitor Arrays (PCA), Switched
Capacitor converters, Noise Spectrum, Sigma-Delta Modulation Method, Sigma-Delta A/D and
D/A Converters, Non Idealities.
Key Analog Circuit Design: Analog VLSI building blocks, Operational Amplifiers for
converters, advanced op-amp design techniques, Voltage Comparators, Sample-and-Hold
Circuits.
Implementation and Design of High Performance A/D and D/A Converters: System Design,
Digital Compensation, Noise, and Mismatch, Layout and Simulation Technologies for Data
Converters.
Design Challenges: Low Voltage Design, Ultra-High Speed Design, High Accuracy Design.
Advanced Topics: Multipliers, Oscillators, Mixers, Passive Filter Design, Active filter design,
Switched Capacitor Filters, Frequency Scaling, Phase-Locked Loops, Device Modeling for AMS
IC Design, Concept of AMS Modeling and Simulation.
Recommended Books 1. Plassche, Rudy J.Van De, Integrated A-D and D-A Converters, Springer (2007)
2nd ed. 2. Gregorian, R. and Temes, G.C., Analog MOS Integrated Circuits for Signal
Processing, Wiley (2002). 3. Baker, R.J., Li, H.W. and Boyce, D.E., CMOS: Circuit Design, Layout and
Simulation, IEEE Press (2007) 2nd ed.
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Page 29
4. Gregorian, R., Introduction to CMOS Op-Amps and Comparators, Wiley (1999).
5. Jespers, P.G. A., Integrated Converters: D-A and A-D Architectures, Analysis and Simulation, Oxford University Press (2001).
Approved by the Senate in its 70th meeting held on May 25,2009
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PVL333 SYSTEM ON CHIP
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Overview of SOC Design Process:
Introduction, Top-down SoC design flow, Metrics of SoC design, Techniques to improve a
specific design metric, ASIC Design flow and EDA tools.
SOC Architecture Design: Introduction, Front-end chip design, Back-end chip design, Integration platforms and SoC
Design, Function Architecture Co-design, Designing Communication Networks, System Level
Power Estimation and Modeling, Transaction Level Modeling, Design Space Exploration,
Software design in SoCs.
SOC Design and Test Optimization:
Design methodologies for SoC, Noise and signal integrity analysis, System Integration issues for
SoC, SoC Test Scheduling and Test Integration, SoC Test Resource partition.
Recommended Books 1. Wolf, W., Modern VLSI Design: System-on-chip Design, Prentice Hall (2002)
3rd ed. 2. Nekoogar, F. and Nekoogar, F., From ASICs to SOCs: A Practical Approach,
Prentice Hall (2003). 3. Uyemura, J.P., Modern VLSI Design – SOC Design, Prentice Hall (2001). 4. Lin, S. Y.L., Essential Issues in SOC Design: Designing Complex Systems-On-
Chip, Springer (2004). 5. Rajsuman, R., System-on-a-chip: Design and Test, Artech House (2000). 6. Nurmi, J., Tenhunen, H., Isoaho, J. and Jantsch, A., Interconnect-Centric Design
for advanced SoC and NoC, Kluwe (2008). 7. Asheden, P.J. and Mermet J., System-on-Chip Methodologies and Design
Languages, Kluwer Academic (2002). 8. Erbas, C., System-Level Modeling and Design Space Exploration for
Multiprocessor Embedded System-on-Chip Architectures, Amsterdam University Press (2007).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 31
PVL334 HIGH SPEED VLSI DESIGN
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Introduction of High Speed VLSI Circuits Design.
Back-End-Of -Line Variability Considerations: Ideal and non ideal interconnect issues,
Dielectric Thickness and Permittivity.
The Method of Logical Effort: Delay in a logic gate, Multi-stage logic networks, Choosing the
best number of stages.
Deriving the Method of Logical Effort: Model of a logic, Delay in a logic gate, Minimizing
delay along a path, Choosing the length of a path, Using the wrong number of stages, Using the
wrong gate size.
Non-Clocked Logic Styles: Static CMOS, DCVS Logic, Non-Clocked Pass Gate Families.
Clocked Logic Styles: Single-Rail Domino Logic Styles, Dual-Rail Domino Structures, Latched
Domino Structures, Clocked Pass Gate Logic.
Circuit Design Margining: Process Induced Variations, Design Induced Variations, Application
Induced Variations, Noise.
Latching Strategies: Basic Latch Design, Latching single-ended logic, Latching Differential
Logic, Race Free Latches for Pre-charged Logic Asynchronous Latch Techniques.
Interface Techniques: Signaling Standards, Chip-to-Chip Communication Networks, ESD
Protection.
Clocking Styles: Clock Jitter, Clock Skew, Clock Generation, Clock Distribution, Asynchronous
Clocking Techniques.
Skew Tolerant Design.
Recommended Books 1. Bernstein, K., Carrig, K.M., Durham, Hansen, C.M., Hogenmiller, E. J., Nowak
and Rohrer, N.J., High Speed CMOS Design Styles, Kluwer (2007). 2. Sutherland, I.E., Sproull, B.F. and Harris, D.L., Logical Effort: Designing Fast
CMOS Circuits, Elsevier/MK (1999).
3. Jhonson, H.W., High Speed Digital Design, Prentice Hall PTR (2008).
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PVL335 FAULT TOLERANCE IN VLSI
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Motivation of fault tolerance in arithmetic systems, Fault and error models in VLSI arithmetic
units, Reliability and fault tolerance definitions, Reliability and availability modeling.
Estimation of the reliability and availability of fault tolerant systems, Fault diagnosis, Fault
tolerance measurement.
Fault tolerance strategies: detection, correction, localization, reconfiguration, Error recovery,
Error detecting and correcting codes.
Detection/correction techniques: modular redundancy, time redundancy (e.g., RESO, RERO,
REDWC, RETWV, REXO), datacoding (e.g., AN codes, residue codes, GAN codes, RBR codes,
Berger codes, residue number systems), algorithm-based techniques, Reconfiguration techniques.
Applications to arithmetic units and systems (e.g., convolvers, inner product units, FFT units,
neural networks), Application levels: unit, processing element, subsystem, system. Cost/benefit
analysis Fault-tolerant transaction processing systems; Fault-tolerant Networks; Redundant disks
(RAID).
Software reliability models, Software fault-tolerance methods: N-version programming, recovery
blocks, rollback and recovery.
Architecture and design of fault – tolerant computer systems using protective redundancy.
Recommended Books 1. Pradhan, D.K., Fault Tolerant Computer System Design, Prentice Hall (1996). 2. Johnson, B.W., Design and Analysis of Fault Tolerant Digital Systems, Addison
Wesley (1989). 3. Nelson, V.P. and Carroll, B. D., Tutorial: Fault Tolerant Computing, IEEE
Computer Society Press (1990). 4. Slewiorek, D.P., Swarz, R. S. and Peters A.K., Reliable Computer Systems:
Design and Evaluation, A K Peters (1998) 3rd ed.
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PVL341 LOW POWER DESIGN TECHNIQUES
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Low Power Microelectronics: Retrospect and Prospect, Fundamentals of power dissipation in
microelectronic devices, Estimation of power dissipation due to switching, short circuit, sub-
threshold leakage, and diode leakage currents.
CMOS Scaling: Scaling for High Performance and Low-Power,
Low Voltage Technologies and Circuits: Threshold Voltage Scaling and Control, Multiple
Threshold CMOS (MTCMOS), Substrate Bias Controlled Variable Threshold CMOS, Testing
Issues: Design and test of low-voltage CMOS circuits.
Circuit and Logic Styles: Power-conscious logic Styles, Adiabatic Logic Circuits. Power
Analysis and optimization: Power Analysis Techniques, Power Optimization Techniques, Energy
recovery techniques, Software power estimation and optimization Low-Power Memory Circuits
and architectures.
Power Conscious High-Level Synthesis.
Silicon-On-Insulator Based Technologies.
Recommended Books 1. Roy, K. and Prasad, Sharat C., Low Power CMOS VLSI: Circuit Design, John
Wiley (2009). 2. Chandrakasan, A.P. and Broderson, R.W., Low Power Digital CMOS Design,
Kluwer (1995). 3. Rabaey, J.M. and Pedram, M., Low Power Design Methodologies, Springer
(1996). 4. Yeo, K.S. and Roy K., Low Voltage, Low Power VLSI Subsystems, McGraw Hill
(2004). 5. Sanchez-Sinencio, E. and Andreou, A.G., Low-Voltage/Low-Power Integrated
Circuits and Systems: Low-Voltage Mixed-Signal Circuits, IEEE Press (1999). 6. Bellaouar, A. and Elmasry, M.I., Low-Power Digital VLSI Design: Circuits and
Systems, Kluwer (1995).
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PVL342 RF IC DESIGN
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Introduction to RF and Wireless Technology: Complexity comparison, Design bottleneck,
Applications, Analog and Digital systems and choice of technology.
Basic Concepts in RF Design: Non linearity and time variance - Effects of non linearity and
cascaded nonlinear stages, Inter symbol interference, Random Processes and noise, Sensitivity
and dynamic range, Passive Impedance Transformation.
Modulation and Detection: General considerations, Analog Modulation: Amplitude
modulation, phase and frequency modulation, Digital modulation - basic concepts, binary
modulation and quadrature modulation, Power efficiency of modulation schemes - constant and
variable envelope signals and spectral regrowth, Noncoherent detection.
Multiple Access Techniques and Wireless Standards: Multiple RF communications, Multiple
Access Techniques Time and frequency division duplexing, Frequency division multiple access,
Time division multiple access and Code division multiple access. Wireless Standards - Advanced
mobile phone services, North American Digital Standard, Global system for mobile
communication, Qualcomm CDMA and Digital European Cordless Telephone.
Transceiver Architectures: General consideration, Receiver Architectures, Heterodyne and
Homodyne receivers, Image reject receivers, Digital IF receivers and Subsampling receivers;
Transmitter Architectures, Direct conversion transmitters and two step transmitters, Transceiver
performance tests.
Low Noise Amplifiers and Mixers: Low noise amplifiers - General considerations, Input
matching, Bipolar LNAs and CMOS LNAs; Down conversion mixers - General considerations,
Bipolar mixers, CMOS mixers and noise in mixers, Cascaded stages.
Oscillators: General considerations, Basic LC Oscillator Topologies, Voltage-Controlled
Oscillators, Phase Noise - Effect of phase noise in RF communications, Q of an oscillator, Phase
noise mechanisms, noise power trade-off, effect of frequency division and multiplication on
phase noise, oscillator pulling and pushing, Bipolar and CMOS LC Oscillators, Negative Gm
oscillators and interpolative oscillators, Monolithic inductors, Resonator-less VCOs, Quadrature
Signal Generations, RC-CR network, Havens technique, frequency division, Single sideband
generation.
Frequency Synthesizers: General considerations, Phase lock loops - basic concepts, basic PLL,
Charge pump PLLs, Types I and II PLLs, noise in PLLs, phase noise at input, phase noise of
VCO and frequency multiplication, RF synthesizer architectures, Integer N architecture,
fractional N architecture, Dual loop architecture and direct digital synthesis, Frequency dividers
divide by two circuits and dual modulus dividers.
Power Amplifiers: General considerations, linear and nonlinear PAs, Classification of power
Approved by the Senate in its 70th meeting held on May 25,2009
Page 35
Amplifiers, Class A, B, and C PAs, High efficiency power amplifiers, Large signal impedance
matching, Linearization techniques, feedforward, feedback, envelope elimination and restoration
and LINC, Design examples.
Recommended Books 1. Razavi, B., RF Microelectronics, John Wiley (2008). 2. Lee, T.H., The Design of CMOS Radio-Frequency Integrated Circuits,
Cambridge University Press (2003) 2nd ed. 3. Tsividis, Y.P., Mixed Analog and Digital VLSI Devices and Technology, World
Scientific (2002). 4. Baker, R. Jacob, Li, H.W. and Boyce, D.E., CMOS Circuit Design, Layout and
Simulation, Prentice-Hall of India (2004) 2nd ed .
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Page 36
PVL343 SENSOR TECHNOLOGY AND MEMS
L T P Cr
3 0 0 3.0
Prerequisite(s): None
Introduction to MEMS: Overview of CMOS process in IC fabrication, MEMS system-level
design methodology, Equivalent circuit representation of MEMS, Signal-conditioning circuits
and Sensor Noise calculation.
Principles of Physical and Chemical Sensors: Sensor classification, Sensing mechanism of
Mechanical, Electrical, Thermal, Magnetic, Optical, Chemical and Biological Sensors.
Sensor Characterization and Calibration: Study of Static and Dynamic Characteristics, Sensor
Reliability, Aging Test, Failure Mechanisms and their evaluation and stability study.
Sensor Modeling: Numerical modeling techniques, Model equations, different effects on
modeling (mechanical, electrical, thermal, magnetic, optical, chemical and biological) and
examples of modeling.
Sensor Technology: Thick and Thin Films fabrication process, Micro machining, IOC
(Integrated Optical Circuit) fabrication process, Wire Bonding and Packaging.
Sensor Applications: Pressure Sensors with embedded electronics, accelerometer with
transducer, gyroscope, RF MEMS Switch with electronics, Process engineering, medical
diagnostic and patient monitoring, environmental monitoring.
Future Aspects of MEMS: RF MEMS, Optical MEMS, NEMS, MOEMS,
Recommended Books 1. Gad-el-Hak, Mohamed, MEMS: Introduction and Fundamentals, 2nd Edition,
CRC Press (2005) 2nd ed. 2. Maluf, N., An Introduction to Micro-Electro-Mechanical Systems Engineering,
Artech House (2000). 3. Ristic, L. (Editor), Sensor Technology and Devices, Artech House (1994). 4. Leondes, T.C., MEMS/ NEMS Handbook: Techniques and Application, Springer
Press (2007). 5. Lyshevski, S.E., Nano- and Micro-Electromechanical Systems: Fundamentals of
Nano and Micro Engineering, CRC Press (2005) 2nd ed. 6. Los, Introduction to Micro-Electro-Mechanical Microwave Systems, Artech
House (2004) 2nd ed. 7. D.S. Ballantine, Robert M. White, S.J. Martin, Antonio J. Ricco, E.T. Zellers, G. C. Frye,
H. Wohltjen., Acoustic Wave Sensors, Academic Press (1997). 8. Masoos, Tabib-Azar, Microactuators, Kluwer (1998). 9. Allen, J., Micro Electro Mechanical System Design, CRC Press (2005). 10. Senturia, S.D., Microsystem Design, Springer (2004).
Approved by the Senate in its 70th meeting held on May 25,2009
Page 37
PVL344 HARDWARE ALGORITHMS FOR COMPUTER ARITHMETIC
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3 0 0 3.0
Prerequisite(s): None
Numbers and Arithmetic: Review of Number systems, their encoding and basic arithmetic
operations, Class of Fixed-Radix Number Systems, Unconventional fixed-point number systems,
Representing Signed Numbers, Negative-radix number Systems, Redundant Number Systems,
Residue Number Systems.
Algorithms for Fast Addition: Basic Addition and Counting, Bit-serial and ripple-carry adders,
Addition of a constant: counters, Manchester carry chains and adders, Carry-Look-ahead Adders,
Carry determination as prefix computation, Alternative parallel prefix networks, VLSI
implementation aspects, Variations in Fast Adders, Simple carry-skip and Carry-select adders,
Hybrid adder designs, Optimizations in fast adders, Multi-Operand Addition, Wallace and Dadda
trees, Parallel counters, Generalized parallel counters, Adding multiple signed numbers.
High-Speed Multiplication: Basic Multiplication Schemes, Shift/add multiplication algorithms,
Programmed multiplication, Basic hardware multipliers, Multiplication of signed numbers,
Multiplication by constants, Preview of fast multipliers, High-Radix Multipliers, Modified
Booth's recoding, Tree and Array Multipliers, Variations in Multipliers, VLSI layout
considerations.
Fast Division and Division Through Multiplication: Basic Division Schemes, Shift/subtract
division algorithms, Programmed division, Restoring hardware dividers, Non-restoring and
signed division, Division by constants, Preview of fast dividers, High-Radix Dividers, Variations
in Dividers, Combined multiply/divide units, Division by Convergence, Hardware
implementation.
Real Arithmetic: Representing the Real Numbers, Floating-point arithmetic, The ANSI/IEEE
floating-point standard, Exceptions and other features, Floating-point arithmetic operations,
Rounding schemes, Logarithmic number systems, Floating-point adders, Barrel-shifter design,
Leading-zeros/ones counting, Floating-point multipliers, Floating-point dividers, Arithmetic
Errors and Error Control.
Function Evaluation: Square-Rooting Methods, The CORDIC Algorithms, Computing
logarithms, Exponentiation, Approximating functions, Merged arithmetic, Arithmetic by Table
Lookup, Tradeoffs in cost, speed, and accuracy.
Implementation Topics: High-Throughput Arithmetic, Low-Power Arithmetic, Fault-Tolerant
Arithmetic, Emerging Trends, Impact of Hardware Technology.
Recommended Books 1. Parhami, B., Computer Arithmetic: Algorithms and Hardware Design, Oxford
University Press (2000). 2. Koren, I., Computer Arithmetic Algorithms, 2nd Edition, Uni Press (2005) 2nd
ed. 3. Ercegovac, M. and Lang, T., Digital Arithmetic, Elsevier (2005).
Approved by the Senate in its 70th meeting held on May 25,2009
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PVL345 OPTICAL VLSI
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3 0 0 3.0
Prerequisite(s): None
Introduction: Optical communication: An historical overview, Optical fiber versus copper
wire, Integration of Optical communication systems, Optical communication link.
The CMOS Optical Receiver: Simple Resistor Optical Receiver, Transimpedance amplifier,
Comparison of transimpedance amplifiers, Multiple-Stages feedback amplifiers, Noise aspects of
the transimpedance amplifier, Post amplifier.
Integrated CMOS Optical Receivers: DC-Coupled 0.8µm Digital CMOS 155 Mb/s Optical
receiver; 240 Mb/s 18 THz Optical receiver with rail to rail output swing; 1 Gb/s 0.7µm standard
CMOS optical receiver; Performance evaluation.
Full Integration of a Standard CMOS Optical Transmitter: LED driver, Integrated CMOS
optical fiber link, Integrated CMOS photodiodes, Integrated Photodiodes in sub-micron CMOS.
Electrical Interference in Mixed-Mode Integrated Circuits: Aspects of the electrical
Interference Problem, Switching Noise Generation Reduction, On chip Power supply Decoupling,
Noise propagation limitation in integrated circuits, The Generalized use of differential structures
in integrated circuits, Practical implementation.
Recommended Books 1. Ingels, M. and Steyaert, M., Integrated CMOS Circuits for Optical
Communications, Springer (2008). 2. Radovanoic, S., Anne-Johan, Annema and Bram, Nauta, High Speed
Photodiodes in Standard CMOS Technology, Springer (2006). 3. Muller, P., CMOS Multi-channel Single-Chip Receivers for Multi-Gigabit
Optical Data Communications, Springer (2007).