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My Second FPGA for
Altera DE2-115 Board
數位電路實驗
TA: 吳柏辰
Author: Trumen
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Outline
• DE2-115 System Builder
• ModelSim-Altera
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DE2-115 System Builder
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Introduction to DE2-115
System Builder (1/2)
• This section describes how users can create a
custom design project on the DE2-115 board
by using DE2-115 Software Tool DE2-115
System Builder.
• The DE2-115 System Builder is a Windows
based software utility, designed to assist users
to create a Quartus II project for the DE2-115
board withim minutes.
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Introduction to DE2-115
System Builder (2/2)
• The generated Quartus II projects files include:
• Quartus II Project File (.qpf)
• Quartus II Setting File (.qsf)
• Top-Level Design File (.v)
• Synopsis Design Constraints file (.sdc)
• Pin Assignment Document (.htm)
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General Design Flow
6
Start
Launch DE2-115 System Builder
.qpf .qsf
.v .sdc
.htm
Create New
DE2-115 System Builder Project
Generate
Quartus II Projectand Document
Launch
Quartus II and
Open Project
Add User Design/Logic
Compile to generate .SOF
Configure FPGA
End
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• DE2_115_tools\DE2_115_system_builder.exe
Launch DE2-115 System Builder
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Input Project Name
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1
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System Configuration
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GPIO Expansion
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HSMC Expansion
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Project Setting Management
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1
Users can save the current board
configuration information into a .cfg file and
load it to the DE2-115 System Builder
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Project Generation
• When users press the Generation buttion, the
DE2-115 System Builder will generate the
corresponding Quartus II files and documents.
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No. Filename Description
1 exp2_rsa.v Top level verilog HDL file for Quartus II
2 exp2_rsa.qpf Quartus II Project File
3 exp2_rsa.qsf Quartus II Setting File
4 exp2_rsa.sdc Synopsis Design Constraints file for Quartus II
5 exp2_rsa.htm Pin Assignment Document
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THDB-HTG Board
• This figure illustrates how the THDB-HTG
board is connected to the DE2-115 board.
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Be sure to turn off the
power whenever you
connect or disconnect
the THDB-HTG board!!
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exp2_rsa.htm (1/2)
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DE2_115_User_manual.pdf4.8 Usiing the Expansiion Header
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exp2_rsa.htm (2/2)
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THDB-HTG_V1.0.3.pdf1-6 Expansion Prototype Connectors
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exp2_rsa.sdc
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• Remember to modify the .sdc file.
• clock, i/o delay, etc.
create_clock -period 1000 [get_ports clk]derive_clock_uncertaintyset_input_delay 0 -clock clk [all_inputs]set_output_delay 0 -clock clk [all_outputs]
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Can't place multiple pins…?
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• If you try to assign pins by yourself, this error
message may occur.
• How to fix it?
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ModelSim-Altera
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Introduction to ModelSim (1/5)
• ModelSim is a simulation and verification tool
for VHDL, Verilog, SystemVerilog, and mixed
language designs.
• The following diagram shows the basic steps
for simulating a design in ModelSim.
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Create a
working
library
Compile
design
files
Load and
Run
simulation
Debug
results
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Introduction to ModelSim (2/5)
• Creating the Working Library
• In ModelSim, all designs are compiled into
a library.
• You typically start a new simulation in
ModelSim by creating a working library
called "work," which is the default library
name used by the compiler as the default
destination for compiled design units.
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Introduction to ModelSim (3/5)
• Compiling Your Design
• After creating the working library, you compile your design units into it.
• The ModelSim library format is compatible across all supported platforms.
• You can simulate your design on any platform without having to recompile your design.
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Introduction to ModelSim (4/5)
• Loading the Simulator with Your Design
and Running the Simulation
• With the design compiled, you load the
simulator with your design by invoking the
simulator on a top-level module (Verilog) or
a configuration or entity/architecture pair
(VHDL).
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Introduction to ModelSim (5/5)
• Debugging Your Results
• If you don’t get the results you expect, you
can use ModelSim’s robust debugging
environment to track down the cause of the
problem.
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ModelSim-Altera
• Altera Quartus II software allows the user to
launch Modelsim-Altera simulator from within
the software using the Quartus II feature called
NativeLink.
• It facilitates the process of simulation by
providing an easy to use mechanism and
precompiled libraries for simulation.
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Setting up EDA Tool Options
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1
2
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Setting Up the Simulation
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1
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Before Simulation…
• We should compile our design before
simulation to generate a simulation snapshot.
• "Start Analysis & Elaboration" is enough, and it
takes much less time than "Start Compilation".
• And then we can run the simulation.
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Issues of Working Directory
• The working directory of ModelSim-Altera is
under "(project directory)/simulation/modelsim",
so be careful of setting the directory of input
data in the testbench.
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Congratulation!
Be sure ModelSim-Altera has found the input data!!
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If There are Something Wrong…
• Your simulation takes a long time and seems it
will not stop.
• The calculated result is incorrect.
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If the Input Date are not Found…
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It is a fake "PASS"…
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Change the Time Unit of the
Timeline
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1
2
3
4
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Check the Waveform (1/2)
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1
2
3
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Check the Waveform (2/2)
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Zoom full Zoom Mode
How to see the signals in the design? Just try it!
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The End.
Any question?
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Reference
1. "DE2-115 User manual" by Terasic.
2. "THDB-HTG User Manual" by Terasic.
3. ModelSim® Tutorial by Mentor Graphics
Corporation.
4. "Getting Started with Quartus II Simulation
Using the ModelSim-Altera Software User
Guide" by Altera.
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