-
B. Dynamic Simulation Results
At slow switching (trise = 20μs), the dynamic current without Dit increasesaccording to the applied gate bias. With Dit, a surge of current becomesvisible at the beginning due to carriers being trapped. The current decaysuntil it reaches the static value.At fast switching (trise = 200ns), the dynamic current without Dit exhibitsa delay in reaching the static value.
Carriers exhibit a delay to build-up the channel and allow current flow,which is referred to as the nonquasi-static (NQS effect).
With Dit, the surge of current that is observed in slow switching is boundedby the current without Dit. This means that the effects on the current due totrapping are limited by the NQS current without Dit.
For different switching times, the initial surges are all bounded by the NQScurrent without Dit. The current decay occurs much later for fasterswitching due to the stronger NQS effect.
In quasi-static (QS) approximation, the current follows the applied bias without any delay. Due to the traps, the QS current exhibits an initial surge then it decays to reach the static value.
In NQS case, the current flow is delayed because carriers do not respond instantaneously to the abrupt change of applied bias. The current withtrapping effects is bounded by the NQS current.
Trapping effect is concealed by NQS itself. Therefore, any calculation ofcurrent with carrier trapping in the static case does not necessarily appearas degradation in the transient current during switching.In compact modeling, the INQS = IQS + dQ/dt. Therefore, a first-orderapproximation of the maximum current difference ΔI is dQ/dt.
IV. SummaryThe effect on the device characteristics of a 4H-SiC IGBT device isinvestigated by including measurements of the density of interface statesin a consistent Poisson solver.In the static case, threshold voltage shift and current magnitude degradationare observed.At nonquasi-static switching, the surge of current due to trapping is concealedby the NQS current without defects. The NQS behavior itself limits the effectof trapping of carriers.
Reference1. V. V. Afanasev, et al, Phys. Stat. Sol. (a) 162, 321 (1997).
3. Atlas Manual, SILVACO, Inc. (2013).2. I. Pesic, et al, Int. Semiconductor Device Research Symp. (2013).
・
V0
SiC-IGBT
GND
Ic
g
Vc
Extension to Transient SimulationExtension of investigation from static todynamic is not straightforward becausethe dynamics of carriers is governed by:- the time to charge/discharge the channel- the time for trapping/detrapping of carriers
Time
Input Current (QS)
Current (NQS)
(QS + trapping effect)
(NQS + trapping effect)
ΔI
・
・
・
・
・
・
C. Trapping Effects and NQS Interplay
・
・
・
・
・
・
trise
Time (10 s)
1.0e-05
Cur
rent
(A
)
0.4e-05
0.8e-05
0.6e-05
0.2e-05
0
0 1.0 2.0 3.0 4.0-6
5.0 6.0
Without D it
rt = 200nst = 500nst = 1000ns
With D + D 1a 2a
rr
rise 0 1.0 2.0 3.0
Time (Normalized to 1 / t )
0
25.0
Gate voltage (V
)
Time (10 s)
1.0e-05
Cur
rent
(A
)
0.4e-05
0.8e-05
0.6e-05
0.2e-05
0
Without D
With D only
With D only
it
1a
2a
With D + D 1a 2a
0 1.0 2.0 3.0 4.0-5
5.0
trise = 20μs
0 1.0 2.0 3.0 4.0Time (10 s)-6
5.0
Without D
With D only
With D only
it
1a
2a
With D + D 1a 2a 0
25.0
Gate voltage (V
)
trise = 200ns
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Cur
rent
(mA
)
Device Simulator
0 5 10 15 20 2530 35Time (ps)
Quasi-static-based Model
Vds = 5V
0
4.0
Gate voltage (V
)
Gate voltage
Ele
ctro
n co
ncen
tratio
n
source channel drain
t1 t2
Vgs
Quasi-static ApproximationNonquasi-static
t2
t1
Switch-on
・
Parameters are extracted from measurements.
15 20 25 30 35Gate Voltage (V)
(Linear plot) 1.0e-05
0.4e-05
0.8e-05
0.6e-05
0.2e-05
0
0 5 10
(Log plot)
With D onlyWith D only
it1a1a
2a
2a
1.0e-30
1.0e-25
1.0e-20
1.0e-15
1.0e-10
1.0e-05
1.0
Cur
rent
(A
)
0 5 10 15 20 25 30 35Gate Voltage (V)
Vc = 15V
Without DWith D + D
1.0e-35
D1a : Modeled as a Gaussian distribution
D2a : Modeled as an Exponential distribution
Poisson’s Equation:・
Continuity Equations:・
QT Modeling:・
Probability of Trap Occupation for Exponential Distribution:・
Shockley-Read-Hall Recombination/Generation Rate:・
Additional Rate Equations with Transient Probability of Trap Occupation:・
Similar forms of equation are used for Gaussian distribution.・
Oxide Thickness : 0.1μmChannel Doping : 4 x 1017 cm-3
Base Doping : 6 x 1014 cm-3
Simulation is perfomed in2D device simulator ATLAS.
・
・
・
・
・
1Hiroshima University, 2Silvaco Japan
Two degradation characteristics are observed:・
・
1.0e+12
1.0e+13
Den
sity
(cm
-2 eV
-1) D2a
D1a
0 0.5 1.0 1.5 2.0 2.5 3.0Energy (eV)Ev Ec
Total Interface Defect Density
Afanasev, et al. Phys. Stat. Sol. 1997
1.0e+11
D2a(D1a+ )
SiC, a wide-band semiconductor material with high thermal conductivity andhigh thermal stability, has become widely employed in power semiconductordevices.
I. Background and Motivation
4H-SiC has been given focus because of its substantially higher carrier mobility,shallower dopant ionization energies, and lower intrinsic carrier concentration.However, reported measurements of the 4H-SiC/SiO2 interface show a highinterface trap density Dit, characterized by distinct deep and shallow traps.The impact of traps on the device electrical characteristics should be investigated.
II. Simulation-Based InvestigationReported measurements of the defect densities are included as interfacedefect states in the SiC bandgap.The effects on the device electrical characteristics are investigated.
A. Reported Measurements of Defect Density at the 4H-SiC/SiO2 interface
B. Device Simulation with Defects
C. Trench 4H-SiC IGBT Device Structure
III. Results and DiscussionA. Static Simulation Results
2. The collector current magnitude is decreased. This is due to shallow traps defined by the D2a defect distribution.
1. The onset of the conduction current is shifted towards a higher gate voltage. This is due to deep traps defined by the D1a defect distribution.
Switching Characteristics of a 4H-SiC IGBT with Interface DefectsUp to the Nonquasi-Static Regime
Iliya Pesic1,2, Dondee Navarro2, Masato Fujinaga2, Yoshiharu Furui2, and Mitiko Miura-Mattausch1
