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  • DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · [email protected] ABSTRACT Placement for very-large-scale
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DREAMPlace: D eep Lear ning Toolkit-E nabled GPU A cceleration for M odern VLSI Place ment Yibo Lin ECE Department, UT Austin [email protected] Shounak Dhar ECE Department, UT Austin [email protected] Wuxi Li ECE Department, UT Austin [email protected] Haoxing Ren Nvidia, Inc., Austin [email protected] Brucek Khailany Nvidia, Inc., Austin [email protected] David Z. Pan ECE Department, UT Austin [email protected] ABSTRACT Placement for very-large-scale integrated (VLSI) circuits is one of the most important steps for design closure. This paper proposes a novel GPU-accelerated placement framework DREAMPlace, by casting the analytical placement problem equivalently to training a neural net- work. Implemented on top of a widely-adopted deep learning toolkit PyTorch, with customized key kernels for wirelength and density computations, DREAMPlace can achieve over 30× speedup in global placement without quality degradation compared to the state-of-the-art multi-threaded placer RePlAce. We believe this work shall open up new directions for revisiting classical EDA problems with advancement in AI hardware and software. 1 INTRODUCTION Placement is a critical but time-consuming step in the VLSI design flow. As it determines the locations of standard cells in the physical layout, its quality has significant impacts on the later stages in the flow such as routing and post-layout optimization. A placement solution also provides relatively accurate estimation to routed wirelength and congestion, which is very valuable in guiding the earlier stages like logic synthesis. The commercial design flows often run core placement engines many times to achieve design closure. As placement involves large-scale numerical optimization, current placement usually takes hours for large designs, thus, slowing down design iterations. Therefore, ultra-fast yet high quality placement is always in strong demand. Analytical placement is the current state-of-the-art for VLSI place- ment [1–7]. It essentially solves a nonlinear optimization problem. Although analytical placement can produce high-quality solutions, it is also known to be relatively slow [8–11]. Here we provide a brief introduction to the analytical placement problem. Suppose a circuit is described as a hypergraph H = ( V , E), where V denotes the set of vertices (cells) and E denotes the set of hyperedges (nets). Let x, y de- note the locations of cells. The objective of analytical placement is to determine the locations of cells with wirelength minimized and no overlap in the layout. To accelerate placement, existing parallelization efforts have mostly targeted multi-threaded CPUs using partitioning [11–13]. As the num- ber of threads increases, speedup quickly saturates at around 5× in global placement with typical quality degradation of 2-6%. Cong et al. ex- plored GPU acceleration for analytical placement [14]. They combined Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. DAC ’19, June 2–6, 2019, Las Vegas, NV, USA © 2019 Association for Computing Machinery. ACM ISBN 978-1-4503-6725-7/19/06. . . $15.00 https://doi.org/10.1145/3316781.3317803 clustering and declustering with nonlinear placement optimization. By parallelizing the nonlinear placement part, an average of 15× speedup in global placement was reported with less than 1% quality degradation. Lin et al. proposed GPU acceleration techniques for wirelength gradient computation and area accumulation [15], but their experiment failed to consider real operations such as density cost computation and it lacked the validation from real analytical placement flows. In addition, current research on placement is facing challenges in the lack of well- maintained public frameworks and the high development overhead, raising the bar to systematically validate new algorithms. In this work, we propose DREAMPlace, a GPU-accelerated analytical placer developed with deep learning toolkit PyTorch by casting an analytical placement problem to training a neural network. DREAM- Place is based on the state-of-the-art analytical placement algorithm ePlace/RePlAce family [4, 6], but the framework is designed in a generic way that is compatible with other analytical placers such as NTUplace [2]. The key contributions are summarized as follows. • We take a totally new perspective of making analogy between placement and deep learning, and build an open-source generic analytical placement framework that runs on both CPU and GPU platforms developed with modern deep learning toolkits. • We propose efficient GPU implementations of key kernels in analytical placement like wirelength and density computation. • We demonstrate over 30× speedup in global placement and le- galization without quality degradation of the entire placement flow over multi-threaded CPU implementations. More specifi- cally, a design with one million cells finishes in one minute. The framework maintains nearly linear scalability with industrial designs up to 10-million cells. The source code is released on Github 1 . To clarify, the casting of place- ment problem to deep learning problems aims at using the toolkit to solve placement, which is orthogonal to using deep learning models for placement. The rest of the paper is organized as follows. Section 2 describes the background and motivation; Section 3 explains the de- tailed implementation; Section 4 demonstrates the results; Section 5 concludes the paper. 2 PRELIMINARIES This section will review the background and motivation. 2.1 Analytical Placement Analytical placement usually consists of three steps: global placement (GP), legalization (LG), and detailed placement (DP). Global placement spreads out cells in the layout with a target cost minimized; legaliza- tion removes the remaining overlaps between cells and aligns cells to placement sites; detailed placement performs incremental refinement 1 https://github.com/limbo018/DREAMPlace

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Page 1: DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · dpan@ece.utexas.edu ABSTRACT Placement for very-large-scale

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration forModern VLSI Placement

Yibo LinECE Department, UT Austin

[email protected]

Shounak DharECE Department, UT [email protected]

Wuxi LiECE Department, UT Austin

[email protected]

Haoxing RenNvidia, Inc., Austin

[email protected]

Brucek KhailanyNvidia, Inc., Austin

[email protected]

David Z. PanECE Department, UT Austin

[email protected]

ABSTRACTPlacement for very-large-scale integrated (VLSI) circuits is one of themost important steps for design closure. This paper proposes a novelGPU-accelerated placement framework DREAMPlace, by casting theanalytical placement problem equivalently to training a neural net-work. Implemented on top of a widely-adopted deep learning toolkitPyTorch, with customized key kernels for wirelength and densitycomputations, DREAMPlace can achieve over 30× speedup in globalplacement without quality degradation compared to the state-of-the-artmulti-threaded placer RePlAce. We believe this work shall open up newdirections for revisiting classical EDA problems with advancement inAI hardware and software.

1 INTRODUCTIONPlacement is a critical but time-consuming step in the VLSI designflow. As it determines the locations of standard cells in the physicallayout, its quality has significant impacts on the later stages in the flowsuch as routing and post-layout optimization. A placement solutionalso provides relatively accurate estimation to routed wirelength andcongestion, which is very valuable in guiding the earlier stages likelogic synthesis. The commercial design flows often run core placementengines many times to achieve design closure. As placement involveslarge-scale numerical optimization, current placement usually takeshours for large designs, thus, slowing down design iterations. Therefore,ultra-fast yet high quality placement is always in strong demand.

Analytical placement is the current state-of-the-art for VLSI place-ment [1–7]. It essentially solves a nonlinear optimization problem.Although analytical placement can produce high-quality solutions, itis also known to be relatively slow [8–11]. Here we provide a briefintroduction to the analytical placement problem. Suppose a circuitis described as a hypergraph H = (V ,E), where V denotes the set ofvertices (cells) and E denotes the set of hyperedges (nets). Let x, y de-note the locations of cells. The objective of analytical placement is todetermine the locations of cells with wirelength minimized and nooverlap in the layout.

To accelerate placement, existing parallelization efforts have mostlytargeted multi-threaded CPUs using partitioning [11–13]. As the num-ber of threads increases, speedup quickly saturates at around 5× inglobal placementwith typical quality degradation of 2-6%. Cong et al. ex-plored GPU acceleration for analytical placement [14]. They combined

Permission to make digital or hard copies of all or part of this work for personal or classroomuse is granted without fee provided that copies are not made or distributed for profit orcommercial advantage and that copies bear this notice and the full citation on the first page.Copyrights for components of this work owned by others than ACM must be honored.Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers orto redistribute to lists, requires prior specific permission and/or a fee. Request permissionsfrom [email protected] ’19, June 2–6, 2019, Las Vegas, NV, USA© 2019 Association for Computing Machinery.ACM ISBN 978-1-4503-6725-7/19/06. . . $15.00https://doi.org/10.1145/3316781.3317803

clustering and declustering with nonlinear placement optimization. Byparallelizing the nonlinear placement part, an average of 15× speedupin global placement was reported with less than 1% quality degradation.Lin et al. proposed GPU acceleration techniques for wirelength gradientcomputation and area accumulation [15], but their experiment failedto consider real operations such as density cost computation and itlacked the validation from real analytical placement flows. In addition,current research on placement is facing challenges in the lack of well-maintained public frameworks and the high development overhead,raising the bar to systematically validate new algorithms.

In this work, we propose DREAMPlace, a GPU-accelerated analyticalplacer developed with deep learning toolkit PyTorch by casting ananalytical placement problem to training a neural network. DREAM-Place is based on the state-of-the-art analytical placement algorithmePlace/RePlAce family [4, 6], but the framework is designed in a genericway that is compatible with other analytical placers such as NTUplace[2]. The key contributions are summarized as follows.

• We take a totally new perspective of making analogy betweenplacement and deep learning, and build an open-source genericanalytical placement framework that runs on both CPU and GPUplatforms developed with modern deep learning toolkits.• We propose efficient GPU implementations of key kernels inanalytical placement like wirelength and density computation.• We demonstrate over 30× speedup in global placement and le-galization without quality degradation of the entire placementflow over multi-threaded CPU implementations. More specifi-cally, a design with one million cells finishes in one minute. Theframework maintains nearly linear scalability with industrialdesigns up to 10-million cells.

The source code is released on Github 1. To clarify, the casting of place-ment problem to deep learning problems aims at using the toolkit tosolve placement, which is orthogonal to using deep learning modelsfor placement. The rest of the paper is organized as follows. Section 2describes the background and motivation; Section 3 explains the de-tailed implementation; Section 4 demonstrates the results; Section 5concludes the paper.

2 PRELIMINARIESThis section will review the background and motivation.

2.1 Analytical PlacementAnalytical placement usually consists of three steps: global placement(GP), legalization (LG), and detailed placement (DP). Global placementspreads out cells in the layout with a target cost minimized; legaliza-tion removes the remaining overlaps between cells and aligns cells toplacement sites; detailed placement performs incremental refinement

1https://github.com/limbo018/DREAMPlace

https://doi.org/10.1145/3316781.3317803
https://github.com/limbo018/DREAMPlace
Page 2: DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · dpan@ece.utexas.edu ABSTRACT Placement for very-large-scale

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Forward Propagation(Compute obj)

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Backward Propagation(Compute Gradient @obj

@w )<latexit sha1_base64="eHt4RlacyTBkwSNbNglROd3M4wE=">AAAD1XicfZLBb9MwFMbdhcEIsHVw5GKRIY1L1bQHdpwYEhyLRNdJdVU5zktq6tiR46yrMt8QV/4+TvwrOFkrtd2YpUhP773Pvy+fHOWCF6bb/dPa857sP3128Nx/8fLV4VH7+PVloUrNYMiUUPoqogUILmFouBFwlWugWSRgFM0v6vnoGnTBlfxuljlMMppKnnBGjWtN20sSQcplxUAa0Nb/RNl8QXWMB1rlNG22CPFPL1SWlwbwF01j7nbxCUk0ZRXJqTacCkwM3BidVSr6Ye1GO6NmFiXVwtqTDz4BGa9R03bQ7XSbg+8X4aoI0OoMpsd7n0msWJk5PRO0KMZhNzeTqiYxAdYnZQG5809TGLtS0gyKSdVkZPF714lxorT7nP2mu6moaFYUyyxym7XlYndWNx+ajUuTnE0qLut4JLsDJaXARuE6cBxzDcyIpSso09x5xWxGXXYuhG2K4c6w9X2fSFgwlWXUpUUiTe04nFQuu6LUUBuoiIDEEEFlKiAIiebpzNxauy2cg3lYeLuWEN3csCt0RNaIe49RMbnOZ1QalVVBz6484Gang4Pe5ji0j/Lc5ZrfgLDj/v+BeIcY9C1eQ2ta82M46G9xnTG8i3bvLtx9ZfeLy14ndPW3XnB+tnqBB+gteodOUYg+onP0FQ3QEDH0t7XfOmwdeSPPej+9X3ere62V5g3aOt7vfz3aRs4=</latexit><latexit sha1_base64="eHt4RlacyTBkwSNbNglROd3M4wE=">AAAD1XicfZLBb9MwFMbdhcEIsHVw5GKRIY1L1bQHdpwYEhyLRNdJdVU5zktq6tiR46yrMt8QV/4+TvwrOFkrtd2YpUhP773Pvy+fHOWCF6bb/dPa857sP3128Nx/8fLV4VH7+PVloUrNYMiUUPoqogUILmFouBFwlWugWSRgFM0v6vnoGnTBlfxuljlMMppKnnBGjWtN20sSQcplxUAa0Nb/RNl8QXWMB1rlNG22CPFPL1SWlwbwF01j7nbxCUk0ZRXJqTacCkwM3BidVSr6Ye1GO6NmFiXVwtqTDz4BGa9R03bQ7XSbg+8X4aoI0OoMpsd7n0msWJk5PRO0KMZhNzeTqiYxAdYnZQG5809TGLtS0gyKSdVkZPF714lxorT7nP2mu6moaFYUyyxym7XlYndWNx+ajUuTnE0qLut4JLsDJaXARuE6cBxzDcyIpSso09x5xWxGXXYuhG2K4c6w9X2fSFgwlWXUpUUiTe04nFQuu6LUUBuoiIDEEEFlKiAIiebpzNxauy2cg3lYeLuWEN3csCt0RNaIe49RMbnOZ1QalVVBz6484Gang4Pe5ji0j/Lc5ZrfgLDj/v+BeIcY9C1eQ2ta82M46G9xnTG8i3bvLtx9ZfeLy14ndPW3XnB+tnqBB+gteodOUYg+onP0FQ3QEDH0t7XfOmwdeSPPej+9X3ere62V5g3aOt7vfz3aRs4=</latexit><latexit sha1_base64="eHt4RlacyTBkwSNbNglROd3M4wE=">AAAD1XicfZLBb9MwFMbdhcEIsHVw5GKRIY1L1bQHdpwYEhyLRNdJdVU5zktq6tiR46yrMt8QV/4+TvwrOFkrtd2YpUhP773Pvy+fHOWCF6bb/dPa857sP3128Nx/8fLV4VH7+PVloUrNYMiUUPoqogUILmFouBFwlWugWSRgFM0v6vnoGnTBlfxuljlMMppKnnBGjWtN20sSQcplxUAa0Nb/RNl8QXWMB1rlNG22CPFPL1SWlwbwF01j7nbxCUk0ZRXJqTacCkwM3BidVSr6Ye1GO6NmFiXVwtqTDz4BGa9R03bQ7XSbg+8X4aoI0OoMpsd7n0msWJk5PRO0KMZhNzeTqiYxAdYnZQG5809TGLtS0gyKSdVkZPF714lxorT7nP2mu6moaFYUyyxym7XlYndWNx+ajUuTnE0qLut4JLsDJaXARuE6cBxzDcyIpSso09x5xWxGXXYuhG2K4c6w9X2fSFgwlWXUpUUiTe04nFQuu6LUUBuoiIDEEEFlKiAIiebpzNxauy2cg3lYeLuWEN3csCt0RNaIe49RMbnOZ1QalVVBz6484Gang4Pe5ji0j/Lc5ZrfgLDj/v+BeIcY9C1eQ2ta82M46G9xnTG8i3bvLtx9ZfeLy14ndPW3XnB+tnqBB+gteodOUYg+onP0FQ3QEDH0t7XfOmwdeSPPej+9X3ere62V5g3aOt7vfz3aRs4=</latexit><latexit sha1_base64="eHt4RlacyTBkwSNbNglROd3M4wE=">AAAD1XicfZLBb9MwFMbdhcEIsHVw5GKRIY1L1bQHdpwYEhyLRNdJdVU5zktq6tiR46yrMt8QV/4+TvwrOFkrtd2YpUhP773Pvy+fHOWCF6bb/dPa857sP3128Nx/8fLV4VH7+PVloUrNYMiUUPoqogUILmFouBFwlWugWSRgFM0v6vnoGnTBlfxuljlMMppKnnBGjWtN20sSQcplxUAa0Nb/RNl8QXWMB1rlNG22CPFPL1SWlwbwF01j7nbxCUk0ZRXJqTacCkwM3BidVSr6Ye1GO6NmFiXVwtqTDz4BGa9R03bQ7XSbg+8X4aoI0OoMpsd7n0msWJk5PRO0KMZhNzeTqiYxAdYnZQG5809TGLtS0gyKSdVkZPF714lxorT7nP2mu6moaFYUyyxym7XlYndWNx+ajUuTnE0qLut4JLsDJaXARuE6cBxzDcyIpSso09x5xWxGXXYuhG2K4c6w9X2fSFgwlWXUpUUiTe04nFQuu6LUUBuoiIDEEEFlKiAIiebpzNxauy2cg3lYeLuWEN3csCt0RNaIe49RMbnOZ1QalVVBz6484Gang4Pe5ji0j/Lc5ZrfgLDj/v+BeIcY9C1eQ2ta82M46G9xnTG8i3bvLtx9ZfeLy14ndPW3XnB+tnqBB+gteodOUYg+onP0FQ3QEDH0t7XfOmwdeSPPej+9X3ere62V5g3aOt7vfz3aRs4=</latexit>

(a)

Net Instance

ErrorFunction

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minw

nX

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WL(ei;w) + �D(w)<latexit sha1_base64="CS7lVLxi+bEy0kkNJOyOP7cqWJs=">AAAD0nicfZLPb9MwFMfdhh8jG9DBkYtFhFSEVDXtgUlcJrEDBw5DWtdJdYkc96W1ZjvBdrqVLAfElX8QiT8GJwta241ZivT03vv68/XLizPBje33f7fa3oOHjx7vPPF3954+e97Zf3Fq0lwzGLFUpPospgYEVzCy3Ao4yzRQGQsYx+cfq/p4CdrwVJ3YVQZTSeeKJ5xR61JRZ0limHNVwLe8zpQ+kVxFBZHULuKkuChLTEwuI/5VYWLh0mpZjD+XXYj4B3zT9Ra/w0Q47ozio+56nqjU0rlPQM1uKFEn6Pf69cG3g7AJAtSc42i/fURmKcslKMsENWYS9jM7Lai2nAlwtnMDGWXndA4TFyoqwUyLekAlfuMyM5yk2n3K4jq7riioNGYlY9dZOTfbtSp5V22S2+RgWnCV5RYUuwYlucA2xdW08YxrYFasXECZ5s4rZguqKbPun2xQLHeGS9/3iYILlkpJ3bxIrGk5CaeFm57JNVQGCiIgsW7Wai4gCInm84W9KstN4TnYu4VX/yRE1zdsCx2R1eLBfVRMltmCKpvKIhiUjQdc9/RwMFgvh+W9PHe55pcgysnw/0C8RQyGbisbaEWrH4aD4QbXGcPbaLd34faW3Q5OB73QxV8GweFBs4E76BV6jbooRO/RIfqEjtEIMfSn1W7ttva8E++798P7ed3abjWal2jjeL/+AmFoRQA=</latexit><latexit sha1_base64="CS7lVLxi+bEy0kkNJOyOP7cqWJs=">AAAD0nicfZLPb9MwFMfdhh8jG9DBkYtFhFSEVDXtgUlcJrEDBw5DWtdJdYkc96W1ZjvBdrqVLAfElX8QiT8GJwta241ZivT03vv68/XLizPBje33f7fa3oOHjx7vPPF3954+e97Zf3Fq0lwzGLFUpPospgYEVzCy3Ao4yzRQGQsYx+cfq/p4CdrwVJ3YVQZTSeeKJ5xR61JRZ0limHNVwLe8zpQ+kVxFBZHULuKkuChLTEwuI/5VYWLh0mpZjD+XXYj4B3zT9Ra/w0Q47ozio+56nqjU0rlPQM1uKFEn6Pf69cG3g7AJAtSc42i/fURmKcslKMsENWYS9jM7Lai2nAlwtnMDGWXndA4TFyoqwUyLekAlfuMyM5yk2n3K4jq7riioNGYlY9dZOTfbtSp5V22S2+RgWnCV5RYUuwYlucA2xdW08YxrYFasXECZ5s4rZguqKbPun2xQLHeGS9/3iYILlkpJ3bxIrGk5CaeFm57JNVQGCiIgsW7Wai4gCInm84W9KstN4TnYu4VX/yRE1zdsCx2R1eLBfVRMltmCKpvKIhiUjQdc9/RwMFgvh+W9PHe55pcgysnw/0C8RQyGbisbaEWrH4aD4QbXGcPbaLd34faW3Q5OB73QxV8GweFBs4E76BV6jbooRO/RIfqEjtEIMfSn1W7ttva8E++798P7ed3abjWal2jjeL/+AmFoRQA=</latexit><latexit sha1_base64="CS7lVLxi+bEy0kkNJOyOP7cqWJs=">AAAD0nicfZLPb9MwFMfdhh8jG9DBkYtFhFSEVDXtgUlcJrEDBw5DWtdJdYkc96W1ZjvBdrqVLAfElX8QiT8GJwta241ZivT03vv68/XLizPBje33f7fa3oOHjx7vPPF3954+e97Zf3Fq0lwzGLFUpPospgYEVzCy3Ao4yzRQGQsYx+cfq/p4CdrwVJ3YVQZTSeeKJ5xR61JRZ0limHNVwLe8zpQ+kVxFBZHULuKkuChLTEwuI/5VYWLh0mpZjD+XXYj4B3zT9Ra/w0Q47ozio+56nqjU0rlPQM1uKFEn6Pf69cG3g7AJAtSc42i/fURmKcslKMsENWYS9jM7Lai2nAlwtnMDGWXndA4TFyoqwUyLekAlfuMyM5yk2n3K4jq7riioNGYlY9dZOTfbtSp5V22S2+RgWnCV5RYUuwYlucA2xdW08YxrYFasXECZ5s4rZguqKbPun2xQLHeGS9/3iYILlkpJ3bxIrGk5CaeFm57JNVQGCiIgsW7Wai4gCInm84W9KstN4TnYu4VX/yRE1zdsCx2R1eLBfVRMltmCKpvKIhiUjQdc9/RwMFgvh+W9PHe55pcgysnw/0C8RQyGbisbaEWrH4aD4QbXGcPbaLd34faW3Q5OB73QxV8GweFBs4E76BV6jbooRO/RIfqEjtEIMfSn1W7ttva8E++798P7ed3abjWal2jjeL/+AmFoRQA=</latexit><latexit sha1_base64="CS7lVLxi+bEy0kkNJOyOP7cqWJs=">AAAD0nicfZLPb9MwFMfdhh8jG9DBkYtFhFSEVDXtgUlcJrEDBw5DWtdJdYkc96W1ZjvBdrqVLAfElX8QiT8GJwta241ZivT03vv68/XLizPBje33f7fa3oOHjx7vPPF3954+e97Zf3Fq0lwzGLFUpPospgYEVzCy3Ao4yzRQGQsYx+cfq/p4CdrwVJ3YVQZTSeeKJ5xR61JRZ0limHNVwLe8zpQ+kVxFBZHULuKkuChLTEwuI/5VYWLh0mpZjD+XXYj4B3zT9Ra/w0Q47ozio+56nqjU0rlPQM1uKFEn6Pf69cG3g7AJAtSc42i/fURmKcslKMsENWYS9jM7Lai2nAlwtnMDGWXndA4TFyoqwUyLekAlfuMyM5yk2n3K4jq7riioNGYlY9dZOTfbtSp5V22S2+RgWnCV5RYUuwYlucA2xdW08YxrYFasXECZ5s4rZguqKbPun2xQLHeGS9/3iYILlkpJ3bxIrGk5CaeFm57JNVQGCiIgsW7Wai4gCInm84W9KstN4TnYu4VX/yRE1zdsCx2R1eLBfVRMltmCKpvKIhiUjQdc9/RwMFgvh+W9PHe55pcgysnw/0C8RQyGbisbaEWrH4aD4QbXGcPbaLd34faW3Q5OB73QxV8GweFBs4E76BV6jbooRO/RIfqEjtEIMfSn1W7ttva8E++798P7ed3abjWal2jjeL/+AmFoRQA=</latexit>

Neural NetworkWL(·;w)

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Backward Propagation(Compute Gradient @obj

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Forward Propagation(Compute obj)

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(b)

Figure 1: Analogy between neural network training and ana-lytical placement. (a) Train a network for weights w. (b) Solve aplacement for cell locations w = (x, y).

to further improve the quality. Usually, global placement is the mosttime-consuming portion in analytical placement.

Global placement aims at minimizing the wirelength cost subjectingto density constraints. A typical solving approach is to relax the densityconstraints to the objective as a density penalty [2, 4, 16],

min (∑e ∈E

WL(e; x, y)) + λD(x, y), (1)

where WL(·; ·) is the wirelength cost function that takes any net in-stance e and returns the wirelength, and D(·) is the density penalty tospread cells out in the layout. The density constraints can be satisfiedby gradually increasing the weight λ.

2.2 Analogy to Deep LearningAs both solving an analytical placement and training a neural networkare essentially solving a nonlinear optimization problem, we investigatethe underlying similarity between the two problems: the analogy of thewirelength cost to the error of misprediction and that of the density costto the regularization term. Figure 1 shows the objective functions ofthe two problems. In neural network training, each data instance witha feature vector xi and a label yi is fed to the network and the neuralnetwork predicts a label ϕ(xi ;w). The task for training is to minimizethe overall objective over weights w, where the objective consists ofthe prediction errors for all data instances, and a regularization termR(w) [17]. In the analogy of placement to neural network training,we combine cell locations (x, y) into w for brevity. Each data instanceis replaced with a net instance with a feature vector ei and a labelzero. The neural network then takes a net instance and computes thewirelength cost WL(ei ;w). Using the absolute error function f (y,y) =|y − y | and noting that wirelength is non-negative, the minimizationof prediction errors becomes

∑ni WL(ei ;w). The density cost D(w)

corresponds to the regularization term R(w), as it is not related to netinstances. With this construction, we find a one-to-one mapping ofeach component in analytical placement to neural network training,which makes it possible to take advantage of recent developmentsin deep learning toolkits for implementation. Then, we can solve theplacement problem following the neural network training procedure,with forward propagation to compute the objective and backwardpropagation to calculate the gradient.

Deep learning toolkits nowadays consist of three stacks, low-level op-erators (OPs), automatic gradient derivation, and optimization engines,as shown in Figure 2(a). Toolkits like TensorFlow and PyTorchoffer mature and efficient implementation of these three stacks withcompatibility to both CPU and GPU acceleration. The toolkits also pro-vide easy APIs to extend the existing set of low-level operators. Eachcustom operator requires well defined forward and backward functions

PlacementAPI

NonlinearOptimizer

AutomaticGradient

CONV

ReLU

WL

DensityOPs

C++/CUDA

Python

(a)

Random Initial Placement

WL Grad Density Grad

Optimization & Update

Converge?

Legalization

NTUplace DP

N

Y

GP

LG

DP

(b)

Figure 2: (a) Software architecture for placement implementa-tion using deep learning toolkits. (b) DREAMPlace flow.

for cost and gradient computation. To develop an analytical placementwith deep learning toolkits, we only need to implement the customoperators for wirelength and density cost in C++ and CUDA. Then wecan construct a placement framework in Python with very low develop-ment overhead and easily incorporate a variety of optimization enginesin the toolkit. The placement framework can run on both CPU andGPU platforms. Conventional development of placement engines takeshuge efforts in building the entire software stacks with C++. Thus, thebar of designing and validating a new placement algorithm is very highdue to the development overhead. Taking advantage of deep learningtoolkits, researchers can concentrate on the development of criticalparts like low-level operators and high-level optimization engines.

2.3 The ePlace/RePlAce AlgorithmePlace/RePlAce is a state-of-the-art family of global placement algo-rithms that model the layout and netlist as an electrostatic system[4–6]. It uses weighted-average wirelength (WA) for wirelength costoriginally proposed by [18, 19],

WAe =∑i∈e xie

xiγ∑

i∈e exiγ−

∑i∈e xie

−xiγ∑

i∈e e−xiγ

, (2)

where γ is a parameter to control the smoothness and accuracy of theapproximation to half-perimeter wirelength (HPWL). The smaller γ is,the more accurate it is to approximate HPWL, but the less smooth.

Its density penalty is quite different from other analytical placers[2, 16, 20]. With analogy to an electrostatic system, cells are modeledas charges, density penalty is modeled as potential energy, and densitygradient is modeled as the electric field. The numerical solution of theelectric potential and field distribution after solving a Poisson’s equationcan be obtained with spectral methods. Given anM×M grid of bins andwu =

2πuM andwv = 2πv

M with u = 0, 1, . . . ,M − 1,v = 0, 1, . . . ,M − 1,the solution can be computed as follows [4],

au,v =1M2

M−1∑x=0

M−1∑y=0

ρ(x, y) cos (wux ) cos (wvy), (3a)

ψDCT(x, y) =M−1∑u=0

M−1∑v=0

au,vw2u +w2

vcos (wux ) cos (wvy), (3b)

ξXDSCT(x, y) =M−1∑u=0

M−1∑v=0

au,vwu

w2u +w2

vsin (wux ) cos (wvy), (3c)

ξYDCST(x, y) =M−1∑u=0

M−1∑v=0

au,vwv

w2u +w2

vcos (wux ) sin (wvy), (3d)

where ψDCT denotes the potential function, and ξXDSCT and ξYDCSTdenote the electric field in horizontal and vertical directions respectively.Equation (3) requires Discrete Cosine Transform (DCT) and InverseDiscrete Cosine Transform (IDCT) routines to solve efficiently. Thedetailed computation is explained in Section 3. With the electric field

Page 3: DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · dpan@ece.utexas.edu ABSTRACT Placement for very-large-scale

Table 1: NotationsNotation Description Notation Description

V Set of cells E Set of netsP Set of pins B Set of binsx+e maxi ∈e xi ,∀e ∈ E x−e mini ∈e xi ,∀e ∈ Ea+i e

xi −x+e

γ ,∀i ∈ e, e ∈ E a−i e−xi −x

−e

γ ,∀i ∈ e, e ∈ Eb+e

∑i ∈e a

+i ,∀e ∈ E b−e

∑i ∈e a

−i ,∀e ∈ E

c+e∑i ∈e xia

+i ,∀e ∈ E c−e

∑i ∈e xia

−i ,∀e ∈ E

x+ {x+e },∀e ∈ E x− {x−e },∀e ∈ Ea+ {a+i },∀i ∈ P a− {a−i },∀i ∈ Pb+ {b+e },∀e ∈ E b− {b−e },∀e ∈ Ec+ {c+e },∀e ∈ E c− {c−e },∀e ∈ E

LG 1.1

DP5.9

GP-IP

21.1

GP-Nonlinear

71.9

(a)

LG 2.2

DP

11.7

GP-IP

21.1

GP-Nonlinear

65.0

(b)

Figure 3: RePlAce [6] runtime breakdown in percentages onbigblue4 (2 million cells). (a) 1 thread; (b) 10 threads.defined for each bin, the density gradient of each cell is the overallforce taken by the cell in the system.

After defining wirelength cost and density penalty, RePlAce adoptsgradient-descent optimizers, such as Nesterov’s method and conjugategradient method, to solve the optimization problem. RePlAce was im-plemented with multi-threading support [6]. The runtime breakdownfor RePlAce [6] is elaborated in Figure 3. GP including initial place-ment (GP-IP) and nonlinear optimization (GP-Nonlinear) takes about90% of the runtime with both single thread and 10 threads. Therefore,accelerating GP is the most effective in reducing the overall runtime.

3 THE DREAMPLACE ALGORITHMSOur overall placement flow is given in Figure 2(b). It is slightly differentfrom the typical one that starts from a bound-to-bound initial place-ment [2, 4]. We observe that starting from a random initial placementalso achieves the same quality (< 0.04% difference) with significantlyless runtime (21.1% in Figure 3). In initial placement, standard cells areplaced in the center of the layout with a small Gaussian noise. Thescales of the noise are set to 0.1% of the width and height of the place-ment region in the experiment. The kernel global placement iterationsrefer to the loop that involves the computation of wirelength and den-sity gradient, optimization engines, and cell location updating. Afterthe global placement converges, legalization is performed to removeremaining overlaps and align cells to placement sites. The last step be-fore the output is detailed placement to refine the placement solutionsrelying on NTUplace3 [2]. The rest of this section will focus on GPUacceleration to the ePlace/RePlAce algorithm [4, 6].

3.1 Wirelength Forward and BackwardAs RePlAce adopts WA wirelength, we use WA as an example for theGPU acceleration to wirelength forward and backward. Similar insightsalso apply to other wirelength costs like log-sum-exp (LSE) [21], whichis also implemented in the framework. For brevity, we only discuss theequations in the x direction, as those in the y direction are similar. Thereal implementation will separate the computation for x and y intodifferent GPU streams as they are independent.

Direct implementation of WA wirelength defined in Equation (2)

may result in numerical overflow, so we convert exiγ to e

xi −maxj∈e xjγ ,

Forward Backward

x+e

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@D@xi

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Forward Backward(b)

Figure 4: Forward and backward dependency graph for (a)weighted average wirelength and (b) density computation.

and e−xiγ to e−

xi −minj∈e xjγ in Equation (2), which is an equivalent trans-

formation. With the notations in Table 1, the gradient of WAwirelengthto a pin location can be written as,

∂WLe∂xi

=(1 + xi

γ )b+e −

1γ c+e

(b+e )2· a+i −

(1 − xiγ )b

−e +

1γ c−e

(b−e )2· a−i . (4)

A naive parallelization scheme is to allocate one thread for eachnet. This scheme has also been discussed in [15], which only demon-strated limited speedup because the maximum number of threads toallocate is |E | and the workload for each thread is ill-balanced due tothe heterogeneity of net degrees.

Noting that the total number of pins |P | is much larger than |E |, weconsider the possibility of pin-level parallelization. The dependencygraph for WA wirelength forward and backward is elaborated in Fig-ure 4(a). The computation can be completed in four steps: 1) computex±; 2) compute and store a±; 3) compute and store b±, c±; 4) computeWLe in forward or ∂WLe

∂xiin backward. Algorithm 1 illustrates the pin-

level parallel implementation of WA wirelength forward and backwardfunctions. We inline all the CUDA kernel functions, which should beseparate in practice, for brevity. Furthermore, although all the compu-tation for an array with different ± signs, e.g., x+ and x−, is writtentogether, they are separated into different CUDA streams in the im-plementation. In the algorithm, six kernels are needed. The x± kernelrequires atomic maximum and minimum operations, and the b±, c±kernels require atomic addition. At the end of the forward function,summation reduction is needed to compute the overall wirelength cost,which is provided by the deep learning toolkit.

Although [15] suggests to use sparse matrix-vector multiplicationprovided by CUDA for the b±, c± kernels (line 10-15 in Algorithm 1). wefind that the atomic addition is faster, as matrix-vector multiplicationis a more general task. A detailed comparison will be made in theexperimental results.

3.2 Density Forward and BackwardBackward and forward of density cost is another bulk computation.Figure 4(b) plots the dependency graph for density cost forward andbackward. The computation consists of four steps: 1) density mapcomputation; 2) au,v ; 3)ψ in forward or ξ in backward; 4) D in forwardor ∂D

∂xiin backwrad. Steps 2 and 3 are the bulk computation parts, since

DCT/IDCT is required for potential and field computation.

3.2.1 DCT/IDCT for Electric Potential and Field. The electric potentialand field computation in Equation (3) requires fast DCT/IDCT kernelsfor efficient calculation. The standard DCT/IDCT for one-dimensional

Page 4: DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · dpan@ece.utexas.edu ABSTRACT Placement for very-large-scale

Algorithm 1Wirelength Forward and Backward by PinInput: A set of nets E, a set of pins P , and pin locations x ;Output: Wirelength cost and gradient;1: function Forward(E, P ,x )2: x+ ← −∞, x− ←∞, b± ← 0, c± ← 0;3: for each thread 0 ≤ t < |P | do ▷ x± kernel4: Define e as the net that pin t belongs to;5: x+e

at .←−−− max(x+e ,xt ); ▷ atomic max

6: x−eat .←−−− min(x−e ,xt ); ▷ atomic min

7: for each thread 0 ≤ t < |P | do ▷ a± kernel8: Define e as the net that pin t belongs to;

9: a±t ← e±xt −x±e

γ ;10: for each thread 0 ≤ t < |P | do ▷ b± kernel11: Define e as the net that pin t belongs to;12: b±e

at .←−−− b±e + a

±t ; ▷ atomic add

13: for each thread 0 ≤ t < |P | do ▷ c± kernel14: Define e as the net that pin t belongs to;15: c±e

at .←−−− c±e + xta

±t ; ▷ atomic add

16: for each thread 0 ≤ t < |E | do ▷WLe kernel17: Define e as t th net in E;18: Compute WLe ←

c+eb+e−

c−eb−e

;

19: return reduce(∑e ∈E WLe ), a±, b±, c±;

20: function Backward(E, P ,x , a±, b±, c±)21: for each thread 0 ≤ t < |P | do ▷ ∂WLe

∂xtkernel

22: Define e as the net that pin t belongs to;23: Compute ∂WLe

∂xt;

24: return { ∂WLe∂xi},∀i ∈ P ;

(1D) length-N sequence x is,

DCT({xn })k =N−1∑n=0

xn cos (πN(n +

12)k ), (5a)

IDCT({xn })k =12x0 +

N−1∑n=1

xn cos (πNn(k +

12)), (5b)

where k = 0, 1, . . . ,N − 1. We further derive IDXST as,

IDXST({xn })k =N−1∑n=0

xn sin (πNn(k +

12)), (6a)

= (−1)k IDCT({xN−n })k , (6b)

where xN = 0. A detailed derivation is omitted due to page limit. GivenanM×M density map ρ, the electric potential and field can be computedusing DCT/IDCT, IDXST routines.

au,v = DCT(DCT(ρ)T )T , (7a)

ψDCT = IDCT(IDCT({au,v

w2u +w2

v})T )T , (7b)

ξXDSCT = IDXST(IDCT({au,vwu

w2u +w2

v})T )T , (7c)

ξYDCST = IDCT(IDXST({au,vwv

w2u +w2

v})T )T , (7d)

where (·)T denotes matrix transposition. The two-dimensional (2D)DCT/IDCT is computed by performing 1D DCT/IDCT to columns andthen rows. We can see all the computations break down to the 1DDCT/IDCT kernels with proper transformations. Thus, highly opti-mized DCT/IDCT kernels are critical to the performance.

Algorithm 2 DCT/IDCT with N -Point FFTInput: An even-length real sequence x ;Output: An even-length transformed real sequence y;1: function DCT(x )2: N ← |x |;3: for each thread 0 ≤ t < N do ▷ Reorder kernel4: if t < N

2 then5: x ′t ← x2t ;6: else7: x ′t ← x2(N−t )−1;8: x ′′ ← RFFT(x ′); ▷ One-sided real FFT kernel9: for each thread 0 ≤ t < N do ▷ e−

jπ t2N kernel

10: if t ≤ N2 then

11: yt ←2Nℜ(x

′′t e−jπ t2N ); ▷ get real part

12: else13: yt ←

2Nℜ(x

′′(N−t )e

−jπ t2N ); ▷ get real part

14: return y;15: function IDCT(x )16: N ← |x |;17: for each thread 0 ≤ t < N

2 + 1 do ▷ Complex kernel18: x ′t ← (xt − jx(N−t ))e

jπ t2N ; ▷ let xN ← 0

19: x ′′ ← IRFFT(x ′); ▷ One-sided real IFFT kernel;20: for each thread 0 ≤ t < N do ▷ Reverse kernel21: if t mod 2 == 0 then22: yt ←

N4 x′′t2;

23: else24: yt ←

N4 x′′

(N− t+12 );

25: return y;

As the highly optimized fast Fourier transform (FFT) is providedby many deep learning toolkits, we leverage FFT to compute DCT.There are multiple ways to compute DCT using FFT with linear timeadditional processing. For example, TensorFlow adopts the imple-mentation using 2N -point FFT. We choose the N -point FFT imple-mentation [22] and demonstrate better efficiency in the experiments.Algorithm 2 illustrates the FFT implementation with pre-processingand post-processing kernels. Due to the symmetric property of FFT forreal sequences, we utilize one-sided real FFT/IFFT to save almost halfof the sequence. With additional processing kernels like linear-timereordering and multiplication, DCT/IDCT can be computed with anN -point real FFT/IFFT.

3.3 Optimization EngineePlace/RePlAce [4, 6] uses Nesterov’s method as the gradient-descentsolver with a Lipschitz-constant approximation scheme for line search.We implement the same approach in Python leveraging the efficientAPI provided by the deep learning toolkit. The framework is compatiblewith other well-known solvers in deep learning toolkits, e.g., gradi-ent descent with momentum, Adam [23], providing additional solveroptions.

3.4 LegalizationWe also develop legalization as an operator in DREAMPlace. It firstfollows the Tetris-like procedure similar to NTUplace3 [2]. Then itperforms Abacus row-based legalization [24]. This step copies the celllocations from GPU to CPU and executes legalization purely on CPU

Page 5: DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · dpan@ece.utexas.edu ABSTRACT Placement for very-large-scale

because we observe that it only takes several seconds even for million-size designs with a single CPU thread.

4 EXPERIMENTAL RESULTSThe framework was developed in Python with PyTorch for optimizersand API, and C++/CUDA for low-level operators. The DREAMPlace pro-gram runs on a Linux server with 40-core Intel E5-2698 v4 @ 2.20GHzand 1 NVIDIA Tesla V100 GPU based on Volta architecture. Only asingle CPU thread was used by DREAMPlace for launching work tothe GPU in the experiments. RePlAce [6] runs on a Linux server with24-core 3.0 GHz Intel Xeon machine with 64GB memory allocated.ISPD 2005 contest benchmarks [25] and large industrial designs wereadopted. Currently, we only collected experimental results with double-precision floating point numbers on GPU, so additional easy speedupis possible by switching to single-precision.4.1 Placement AccelerationTable 2 and Table 3 show the HPWL and runtime details on ISPD2005 and industrial benchmarks. With almost the same solution quality(within 0.2% difference on average), DREAMPlace is able to achieve35× and 43× speedup in GP on the two benchmark suites compared toRePlAce with 40 threads. RePlAce [6] crashed on the 10-million-cell in-dustrial benchmark at the 9th iteration for Nesterov’s optimization. Thepotential reason is that the peak memory usage of RePlAce exceededthe maximum memory (64GB). Before crashing, it took 119 secondsfor initial placement and on average 9 seconds for each Nesterov itera-tion. As this benchmark takes 1000 iterations with DREAMPlace, wemade an estimation to the runtime lower bound 119 + 1000 ∗ 9 ≈ 9100seconds. The LG of DREAMPlace is also around 10× faster than theNTUplace3 legalizer in the RePlAce flow. As NTUplace3 does the DPfor both placers, so the runtime is similar. The speedup for the entireplacement flow is 5×.

Figure 5 plots the GP runtime comparison between DREAMPlaceand multi-threaded RePlAce. The speedup of RePlAce saturates quicklyfrom single thread to 40 threads, i.e., maximum around 2.5×. Figure 5(b)and Figure 5(c) present the scaling curves with increasing numberof cells. DREAMPlace shows both good stability and nearly linearscalability with problem sizes. Figure 6 draws the runtime breakdownof DREAMPlace on a 2-million-cell design bigblue4, where GP andLG only take 11.7% runtime of the entire flow. The runtime of GP and LGis even comparable to that of file IO for benchmark reading and writing.The majority of the runtime (76%) is taken by DP, which still relies onthe external placer currently. A previous study [26] has demonstratedaround 6× speedup from GPU acceleration for DP over multi-threadedCPU. While DP is not the focus of this paper, there is a potential of15× speedup for the entire placement by future incorporation of GPU-accelerated DP, e.g., 2463

43+9+336/6+54 = 15.2 for bigblue4. On the otherhand, within each forward and backward pass of GP, the density-relatedcomputation takes longer than wirelength (67.8% v.s. 32.2%). Withefficient DCT/IDCT implementation, the electric field computation isno longer the bottleneck for density forward and backward.4.2 Acceleration of Low-Level OperatorsWe further investigate the efficiency of our implementations of the low-level operators, e.g., wirelength forward and backward, DCT/IDCT fordensity forward and backward. Figure 7 compares three approaches dis-cussed in Section 3.1. “Net-by-Net” denotes the net-level parallelization;“Sparse” denotes the sparse matrix-vector multiplication approach [15];“Atomic” denotes the pin-level parallelization with atomic operationsin Algorithm 1. The atomic approach achieves 1.9× speedup over thenet-by-net one, 1.4× speedup over the sparse one.

Figure 8 compares the 2D DCT/IDCT implementation using 2N -point FFT (“DCT-2N” and “IDCT-2N”) and N -point FFT (“DCT-N” and

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LG 2.0

DP

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IO

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WL Forward

WL Backward

Density Map

Electric Field

Density Backward

Density Forward

25.7

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(b)

Figure 6: Runtime breakdown in percentages of DREAMPlace(a) on bigblue4 and (b) one forward and backward pass in GP.

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Figure 7: GPU runtime comparison of different implementa-tion of wirelength forward and backward.

512 1024 2048 4096

Map Size (N ×N)

0.1

1

10

100

Ru

nti

me

(ms) DCT-2N DCT-N

(a)

512 1024 2048 4096

Map Size (N ×N)

0.1

1

10

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Ru

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(ms) IDCT-2N IDCT-N

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Figure 8: GPU runtime comparison of DCT/IDCT algorithms.

“IDCT-N”) [22]. Considering the map sizes in the experiment (from512 × 512 to 4096 × 4096), the N -point implementation is 1.4× faster.Although the runtime gap is decreasing, the N -point implementationstill shows superior efficiency with typical map sizes for a wide rangeof designs.

Page 6: DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration …yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf · 2020-05-11 · dpan@ece.utexas.edu ABSTRACT Placement for very-large-scale

Table 2: Experimental results on ISPD 2005 benchmarks [25].

Design #cells #nets RePlAce [6] (40 Threads) DREAMPlaceHPWL GP (s) LG (s) DP (s) Total (s) HPWL GP (s) LG (s) DP (s) IO (s) Total (s)

adaptec1 211K 221K 73.26 106 5 24 139 73.30 5 0.5 25 5 37adaptec2 255K 266K 81.87 194 7 30 236 82.19 6 0.5 32 6 47adaptec3 452K 467K 193.20 382 22 53 466 194.12 10 1 58 10 82adaptec4 496K 516K 175.23 434 21 61 524 174.43 11 2 65 11 92bigblue1 278K 284K 89.85 168 3 30 206 89.43 7 0.3 35 6 51bigblue2 558K 577K 138.09 383 22 90 505 136.69 11 9 90 12 125bigblue3 1097K 1123K 304.83 967 46 138 1171 303.99 22 3 145 24 198bigblue4 2177K 2230K 743.73 2037 56 329 2463 743.75 43 9 336 54 446ratio - - 1.002 34.8 10.6 0.9 5.0 1.000 1.0 1.0 1.0 - 1.0

Table 3: Experimental results on industrial benchmarks.

Design #cells #nets RePlAce [6] (40 Threads) DREAMPlaceHPWL GP (s) LG (s) DP (s) Total (s) HPWL GP (s) LG (s) DP (s) IO (s) Total (s)

design1 1345K 1389K 340.42 974 46 155 1216 340.87 24 4 179 34 244design2 1306K 1355K 275.46 1001 44 152 1238 275.76 24 5 180 32 244design3 2265K 2276K 524.35 1767 84 257 2189 522.79 37 14 305 55 414design4 1525K 1528K 455.22 1130 55 187 1424 454.38 26 8 207 37 281design5 1316K 1364K 287.24 955 46 153 1193 288.41 22 4 186 33 248design6 10504K 10747K NA >9100 NA NA NA 2356.88 282 73 1681 276 2323ratio - - 1.000 43.1 9.5 0.9 5.0 1.000 1.0 1.0 1.0 - 1.0

5 CONCLUSIONIn this paper, we take a totally new perspective of solving classical ana-lytical placement by casting it into a neural network training problem.Leveraging the deep learning toolkit PyTorch, thus with small soft-ware development effort, we develop a new open-source placement en-gine, DREAMPlace with GPU acceleration. It achieves over 30× speedupin global placement and legalization without quality degradation foracademic and industrial benchmarks, compared to the state-of-the-artRePlAce running on many threads. We explore different implementa-tions of low-level operators for forward and backward propagation toboost the overall efficiency.

Furthermore, DREAMPlace is highly extensible to incorporate newalgorithms/solvers and new objectives by simply writing high-level pro-gramming languages such as Python. We plan to further investigatecell inflation for routability and net weighting for timing optimization[21, 27, 28] as well as GPU-accelerated detailed placement. It can alsobe extended to leverage multi-GPU platforms for further speedup. AsDREAMPlace decouples the high-level algorithmic design and low-levelacceleration efforts, it significantly reduces the development and main-tenance overhead. We believe this work shall open up new directionsfor revisiting classical EDA problems.

ACKNOWLEDGEThis project is supported in part by NVIDIA, Inc.

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[13] W. Li, M. Li, J. Wang, and D. Z. Pan, “UTPlaceF 3.0: A parallelization framework formodern FPGA global placement,” in Proc. ICCAD. IEEE, 2017, pp. 922–928.

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[15] C.-X. Lin and M. D. Wong, “Accelerate analytical placement with gpu: A genericapproach,” in Proc. DATE. IEEE, 2018, pp. 1345–1350.

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[20] A. B. Kahng and Q. Wang, “A faster implementation of APlace,” in Proc. ISPD. ACM,2006, pp. 218–220.

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