Driving Test Precision Into Volume

DAY 1 KEYNOTE: MAPS FOR CARS BY CARSRalf HerrtwichHead of Automotive Business Group, HERE

Mapping the roads of the world has always been a bold undertaking, and a kind of Sisyphus work, because it is never done as roads change all the time. When an out-of-date map is usually merely a nuisance to the human driver when getting inaccurate navigation instructions, it may constitute a more severe issue for automated vehicles. For them, the map needs to be not only more detailed, but also more accurate and up-to-date. Using vehicles themselves for mapping the road network in real time solves most of the problems – and we explain how this is done.

DAY 2 KEYNOTE: PROBING AND TESTING CHALLENGES IN THE 5G ERAOctavio MartinezVice President of Engineering, Qualcomm

The evolution of mobile communication systems into 5G enables the integration of a wide range of devices with unprecedented scale, speed, low power and complexity from smart phones to wearables to autonomous vehicles. 5G will exacerbate the long-standing challenges related to higher parallelism, and the emulation of the electrical characteristic of the package at the probe card / probe core. Octavio will discuss technological development to re-balance the tradeoff’s in measurements accuracy (good PDN)/ KGD quality, cost of test (parallelism / ATE resources), utilization (high-current probes) and design/fabrication cycle time.

October 19-20*, 2017Oceano Hotel, Half Moon Bay, CA*Welcome reception on October 18, 6:00-8:00PM.

Attend COMPASS 2017, FormFactor and Cascade Microtech's annual users' conference, and learn best practices using our products and emerging applications. COMPASS 2017 offers a great lineup of thought-provoking topics presented by industry experts.

Don't miss COMPASS 2017! Register today at compass.cascademicrotech.com

COMPASS 2017 will offer six track sessions focused on the following subject areas:

• High-power applications• Reliability / Parametric• Production test• RF/mmW probing• Advanced test challenges• Optoelectronics/photonics

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WEDNESDAY, OCTOBER 1818:00-20:00 Welcome Reception

THURSDAY, OCTOBER 1908:00-08:30 Registration/ Networking Breakfast/ Sponsor Expo

08:30-08:50 Welcome and Day 1 Agenda Review

08:50-09:40 Day 1 Keynote: Maps for Cars by Cars (Ralf Herrtwich, HERE Technologies)

09:40-10:00 Networking Break and Sponsor Expo

TRACK A: ADVANCED TESTING TRACK B: PHOTONICS/OPTOELECTRONICS

10:00-10:35 Magnetic Probe Cards – Hall Sensors and More (T.I.P.S) Test Challenges in AIM Photonics Multi-Project Wafer Offering (Columbia University)

10:40-11:15 Measurement Uncertainties due to Hitherto Unspecified Offsets Between Source Measurement Units (Infineon)

An Approach for Wafer-Level Optical Polarization Resolved Spectral Measurements (Keysight Technologies)

11:20-11:55 Probe Card Metrology, Challenges and Solutions (Rudolph Technologies)

Test Station for Flexible Semi-Automatic Wafer-Level Silicon Photonics Testing (imec and FormFactor)

11:55-13:00 Roundtable Lunch

TRACK C: RF/MMW PROBING TRACK D: RELIABILITY / PARAMETRIC

13:00-13:35 Multi-Port Millimeter-Wave Production Test Cell (Roos Instruments)

Accelerated Life Testing for Reliability Wearout Mechanisms in 180 nm CMOS Technology (Semi-Conductor Laboratory)

13:40-14:15 RF Massive Parallelism (FormFactor)Enhanced Lifetime of Copper Interconnect Lines Due to Stress Relaxation During Intermittent Current Studies (SUNY Polytechnic Institute)

14:15-14:30 Networking Break + Sponsor Expo

14:30-15:05Investigation of Parasitic Modes By 3D Full-Wave Electromagnetic Simulations Including RF Probe Tips (Karlsruhe Institute of Technology)

Modeling and Minimizing Stray Capacitance for Parametric Probe Cards (FormFactor)

15:10-15:45 Minimizing Discontinuities in Wafer-Level Sub-THz Measurements up to 750 GHz for Device Modelling Applications (FormFactor)

Overcoming Challenges of Unattended Over-Temperature Wafer-Level Measurements (X-FAB)

17:00-20:00 Offsite Event and Dinner

FRIDAY, OCTOBER 2008:00-08:30 Registration/ Networking Breakfast/ Sponsor Expo

08:30-08:50 Day 2 Agenda Preview

08:50-09:40 Day 2 Keynote: Probing and Testing Challenges in The 5G Era (Octavio Martinez, Qualcomm)

09:40-10:00 Networking Break + Sponsor Expo

TRACK E: PRODUCTION TEST TRACK F: POWER DEVICES

10:00-10:35 The CM300, MHU300 and PDC50 in the Wafer Fab (imec) A Roadmap of Next-Generation Power Devices with Gallium Nitride (University of California, Davis)

10:40-11:15 High-Parallelism Probe Card on V93000 Direct Dock System to Increase Testing Throughput on Automotive IC (FormFactor)

Forget the Paschen and Embrace Turbulence! (Celadon Systems)

11:20-11:55 A New Technology for Testing High-Speed RF Applications (Texas Instruments and FormFactor) TBA

12:00-12:45 Lunch / Sponsor Expo

12:45-15:35 Interactive WorkshopSee page 7 for details.

15:45-16:30 Happy Hour/ Networking Reception

* Preliminary program is subject to change

Program At A Glance (As of September 2017)

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General Sessions

TRACK A: ADVANCED TESTING

Magnetic Probe Cards – Hall Sensors and MoreRainer Gaggl, T.I.P.S. Messtechnik

With “Internet of Things”, mobile devices with multi-sensor functionality and other countless applications of sensors, high-volume production test capabilities for these devices will be essential. In this work probe card configurations for wafer test of magnetic sensor devices with different magnetic field requirements will be presented. Starting with principles of magnetic field sensors, magnetic field design and field generation, integration of these into probe card platforms and sample data from test floor will be shown. A deep insight into the challenges of wafer test for these devices will be given. Furthermore, aspects of multi-site probing and calibration as well as thermal management on the probe card will be highlighted. Last but not least, the merging of field generation techniques developed for probe cards into final test will be briefly shown.

Measurement Uncertainties Due to Hitherto Unspecified Offsets Between Source Measurement Units Sebastian Koch, Infineon

Measurement system analysis of setups involving more than one DC source reveals that although each source measurement unit (SMU) is calibrated according to specifications, measurement uncertainties can be significantly larger than expected due to unspecified potential offsets between multiple SMUs. The results of a transfer characteristic measurement of a MOSFET device before and after adjustment of the potential equalization will be shown. Four SMUs are used to bias gate, source, drain and bulk terminals. Each individual measurement is highly repeatable and shows good agreement between measured drain current and the current measured by another SMU at the source terminal (< 150 ppm difference). However, when the SMU at the drain terminal is switched out for another one of the same model, we observe a 3.9 percent (39,000 ppm) variance of measured currents. This inaccuracy is mainly due to potential offsets between the SMUs. A simple improvement of the potential equalization of the SMUs can bring the uncertainty down by one order of magnitude (3,600 ppm). With increasing requirements regarding quality management (ISO 9001 / IATF 16949:2016), we would like to raise awareness of this issue which is so far neither subjected to specifications nor dealt with by regular calibration efforts. Our aim is to convince both users and vendors of SMUs that specifications, calibration possibilities or at least best-practice solutions should be provided for the common use case of employing multiple SMUs in one measurement.

Probe Card Metrology, Challenges and SolutionsJim Powell, Rudolph Technologies

The increasing complexity of advanced probe card solutions conspires to have probe card investment outweigh nearly any other investment in the logic probe test cell, today. Probe cards necessary to support the testing in high parallelism of Applications Processors and Graphics or Micro- Processors, today, are frequently representing a meaningful fraction of the cost of the underlying test system. Ensuring the proper build/manufacture of these cards requires probe card metrology capable of substantially emulating that test system. But, more to the point, ensuring on-going performance and extending the useful life of these cards demands that users increasing invest in probe card metrology that is similarly capable. This paper will explore the attributes of “probe card metrology solutions” to include the probe card metrology and probe card interface (or motherboard) necessary to insure the goodness of the probe test cell in manufacturing.

TRACK B: PHOTONICS/OPTOELECTRONICS

Test Challenges in AIM Photonics Multi-Project Wafer OfferingRobert Polster, Columbia University

Since the beginning of 2017, the American Institute for Manufacturing Integrated Photonics (AIM Photonics) is offering multi-project wafer runs, giving small businesses access to silicon photonics. In the beginning of 2018, AIM Photonics will add a wafer-scale high-speed testing service for the fabricated photonic ICs (PICs) as well as 2.5D assemblies. To make this testing service possible, design for test ideas and standards were defined and will be presented. The set of standards range from alignment aids to test structures allowing the verification of the PICs and assemblies. AIM is currently developing a wafer-scale edge-coupling technique granting direct access to the device under test using planar lightwave circuits (PLCs). Wafer-scale edge coupling makes taps to grating coupler redundant, hence leads to major improvements in the power budget and the component density of the PIC. Optical IO density is usually defined by the fiber cladding diameter which is 127 μm for a single mode fiber. Using glass based PLCs as an intermediary between fiber and PIC the pitch between couplers can be as small as 20 μm on the PIC. First measurement results, designs and next steps will be presented.

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An Approach for Wafer-Level Optical Polarization Resolved Spectral MeasurementsKarl Merkel, Keysight Technologies

With the widespread move to wafer-scale production using integrated photonics technology, the throughput for testing needs to be optimized. A significant part of the time for optical testing on wafers and chips is often used for optimizing the probe coupling. An extra aspect of this for optical coupling involves testing with the intended polarization alignment of the light. Planar devices often have differing optical properties for light polarized parallel (TE) or perpendicular (TM) to the device plane. The coupling from the probe can also have a strong polarization dependence, especially with surface grating couplers. Often during initial research and development, this is dealt with by manually aligning the polarization as part of the probe adjustment process. But that quickly becomes a bottleneck for getting fast automated and reproducible results. Especially for spectral measurements of wavelength dependence, the attempt to hold this polarization alignment while the wavelength is scanned is a real challenge for both speed and reproducibility. A powerful way to address this challenge is with fast automated measurements of the complete polarization dependence, from which the results for aligned polarization can be extracted. Results using a swept wavelength tunable laser based approach will be presented.

Test Station for Flexible Semi-Automatic Wafer-Level Silicon Photonics TestingAuthor: Jeroen De Coster, imec. Presenter: Bryan Bolt, FormFactor

Silicon photonics technologies are a particularly attractive solution for developing low-cost optical interconnects with high performance. imec is developing a silicon photonics technology platform. Developing this platform requires continuous process optimization and design verification, both of which are enabled by the flexible wafer-level test solution that is presented in this paper. The test station enables semi-automatic optical and electro-optical testing of passive and active silicon photonics components and circuits, including waveguides, fiber grating couplers, photodetectors, modulators, filters etc. The measured insertion loss of fiber grating couplers is repeatable to within 0.07 dB (6s), for photodetector responsivity the repeatability is around 0.02 A/W (6s). Calibration procedures have been designed to ensure the long-term reproducibility of measurement results. This is demonstrated with wafer-level measurement data for fiber grating couplers and photodetectors that were gathered over a five-month period. The reproducibility over this period is 0.8 dB for the insertion loss and 0.09 A/W for the responsivity measurement.

TRACK C: RF/MMW PROBING

Multi-Port Millimeter-Wave Production Test Cell Devin Morris, Roos Instruments

With the emergence of integrated, low-cost, high-volume millimeter-wave ICs, the need for production test capability to address this burgeoning market has become paramount to insuring market viability. Point-to-point communication and automotive radar applications have given way to larger markets in next-generation 5G backhaul and 5G handsets. To facilitate millimeter-wave at this scale, production test solutions face the difficult logistics of addressing both the capability requirements of millimeter-wave as well as cost of test. Demonstrated is an implemented test cell for high-density millimeter-wave production test. The test cell is comprised of a Cassini 16 ATE system configured with multi-port millimeter-wave source/measure port capability with a Pyramid Probe® card and autoloading TEL probe system. The setup demonstrates a complete production solution with on-wafer calibration standards and verified measurement performance, automated probe card calibration and thermal offset correction capability within an extensible architecture to address multiple applications from 71-86 GHz.

RF Massive Parallelism Daniel Bock, FormFactor

New applications using Radio Frequency (RF) chips are driving the total number of RF lines to numbers not seen in previous generations. Historically, RF devices typically had one or two lines for transmit and a similar number for receiving. Because of the higher data rate requirements and higher operating frequencies, new applications with phased antenna arrays, such as 5G applications or SW defined radios, have pushed the number of lines up into the 20’s or 30’s for a single device. Add the ongoing push for more parallelism in testing and engineers will soon be grappling to support probe cards with well over 100 RF lines. This session will consider the market drivers that are behind this trend, including the new requirements that it places on testing and the potential solutions available to enable this next generation of RF devices discussing channel count, isolation and RF calibration considerations.

Investigation of Parasitic Modes by 3D Full-Wave Electromagnetic Simulations Including RF Probe Tips Florian Boes, Karlsruhe Institute of Technology

In the millimeter-wave frequency range on-wafer measurements of passive and active circuits are prone to severe deviations between measurement and simulation. One way to achieve a better match is to perform full 3D electromagnetic field simulations (EMFS) of the devices under test (DUT). These simulations cover effects like coupling between structures or complex electromagnetic behavior e.g. in coplanar waveguide (CPW) corners and T-junctions, which are enhanced with air bridges. While these simulations are sufficient at lower frequencies, at frequencies above 200 GHz part of the deviation between measurement and simulation arise from the excitation of parasitic modes which are unobserved using classical EMFS techniques. An extensive study resulted in the conclusion, that these modes depend on the RF probe tip, which used in the measurement setup, and therefore has to be included into the EMFS

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simulation. A part of an Infinity Probe® tip was remodeled and used to excite various circuits. In order to de-embed the probe tip out of the simulation results, the ISS calibration standards were also remodeled and a thru-reflect-line (TRL) error set based on EMFS simulations was calculated, achieving a very good agreement between measurement and simulation.

Minimizing Discontinuities in Wafer-Level Sub-THz Measurements up to 750 GHz for Device Modelling Applications Choon Beng Sia, FormFactor

Achieving accurate and continuous measurement for sub-THz wafer-level device characterization is particularly important for device modelling applications. This presentation outlines, for the first time, challenges affecting measurement continuity and accuracy at such high frequencies. The newly proposed sub-THz measurement strategy with pre-calibration check for low probe contact resistance, combining power and S-parameter probe tip calibration, implementing post-calibration verification checks and ensuring consistent and accurate DC biasing of devices across all frequency bands, has been demonstrated in this work to improve measurement continuity and quality of wafer-level measurements up to 750 GHz.

TRACK D: RELIABILITY/PARAMETRIC

Accelerated Life Testing for Reliability Wearout Mechanisms in 180 nm CMOS TechnologyShammi Verma, Semi-Conductor Laboratory

The concept of accelerated testing to estimate the reliability lifetime for wearout mechanisms like Electromigration (EM), Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI) and Time Dependent Dielectric Breakdown (TDDB) in 180 nm CMOS technology will be discussed. The details of test structures used and testing methodology (stress conditions etc.) will be discussed herein. Specially designed reliability test structures fabricated at Semi-Conductor Laboratory (SCL), Chandigarh using 180 nm standard CMOS process were tested on 1164 Reliability Test System for reliability lifetime estimation. For EM testing, test structures covering all metal and via levels were analyzed for both upward and downward current flow. HCI and NBTI testing was performed on different MOSFETs. The dielectric breakdown (TDDB) has been statistically analyzed on area, periphery and isolation MOS capacitors. The data analysis approach beginning from ranking the failure data, fitting the data, model parameter extraction, voltage and temperature acceleration factors, extrapolation at use conditions using statistical distributions such as Weibull and Lognormal will also be covered. A comprehensive summary of different reliability test results for all failure mechanisms will also be presented.

Enhanced Lifetime of Copper Interconnect Lines Due to Stress Relaxation During Intermittent Current Studies Jennifer Passage, SUNY Polytechnic Institute

Electromigration testing is generally performed via the application of a constant direct current. However, in “real life” the conductor is subjected to an alternating current or pulsed DC sometimes with a low duty cycle. If at all, compensation for pulsed operation is treated “time on,” where the duty cycle is modelled as a linear multiplier of the lifetime. However, electromigration lifetime is determined by the electromigration driving force and an induced stress gradient driving force. The electromigration driving force produces a counter force in the form of a stress gradient. Damage occurs when there is enough stress to nucleate a void. It makes sense that turning off the current periodically should provide some relaxation of the stress gradient and contribute to a longer lifetime than if the current were uninterrupted DC. In this experiment, we studied the electromigration failure of copper interconnects using intermittent current at a previously neglected very low frequency, 10 Hz, with FormFactor’s new module capable of intermittent electromigration stressing. The effects of temperature and duty cycle were studied and compared to earlier studies. Evidence of stress relaxation was revealed in significantly longer lifetimes than expected if “time on” were the only criterion for damage creation. The consequences for extrapolation of lifetimes from accelerated to use conditions is discussed.

Modeling and Minimizing Stray Capacitance for Parametric Probe CardsLarry Levy, FormFactor

The stray capacitance of probe cards is starting to impact certain parametric measurements. Prior to doing parametric test a procedure is usually performed to null out the capacitance produced by the tester and probe card. These days, with shrinking geometries and new test requirements, the capacitance induced by the card can become a large percent of the value we are trying to measure, thus introducing concern about the measurements accuracy. Stray capacitance in probe cards is usually measured in air. However, certain test structures in the wafer can also greatly contribute to the stray capacitance generated by the card. By localizing the values of stray capacitance produced by the main components of the probe card we were able to reengineer the card greatly reducing the stray capacitance while addressing the impact of potential structures in the wafer.

Overcoming Challenges of Unattended Over-Temperature Wafer-Level MeasurementChai Kheh Aun, X-FAB

Measurements for device characterization during process development are more extensive and time consuming than production measurements. Extracting accurate device model requires higher volume of measured data not only at ambient temperature, but also at different temperatures (-40°C to 175°C). Data collection across different temperatures can spent many hours to acquire data at each temperature. Therefore, unattended over-temperature wafer-level testing is the key to improve measurement efficiency. In this session, the challenges and solutions on unattended over temperature measurement will be discussed.

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TRACK E: PRODUCTION TEST

The CM300, MHU300 and PDC50 in the Wafer FabBart De Wachter, imec

To handle high volumes of wafer probe and test, it required a probe station equipped with a wafer cassette load port/wafer handler to allow a 24/7 unattended test modus (non-stop wafer load and test). The CM300 probe station was selected, expanded with the MHU300 wafer handling unit and a PDC50 customized probe card solution for low-resistance (<1 Ω) probe-to-wafer contacts, low-leakage levels (<pA) and tiny probe-pad scrub marks which are favored for downstream processing.

High Parallelism Probe Card on V93000 Direct Dock System to Increase Testing Throughput on Automotive ICs Alan Liao, FormFactor

As automotive IC fabrication process transition to sub-40 nm 12-inch wafers, customers are exploring more efficient testing solutions on the V93000 direct dock system due to increased die per wafer. While the parallelism and probing area requirement increase, the wafer probing on automotive ICs also face new challenges. The failure rate in automotive ICs requires close to none, and zero-defect ICs, wide temperature range testing and minimum pad damage are the key demanding requirements on wafer probing test. These requirements challenge probe card suppliers to provide a product solution to maintain the probe’s thermal planarity across a large probing area and wide temperature range, reduce probe pressure to minimize pad damage prevent dielectric punch-through. FormFactor MEMS probe technology and TrueScale™ Matrix architecture enable a probe card solution to meet these requirements. FormFactor and Advantest successfully developed TrueScale Matrix probe cards for Advantest 93000 direct dock system, enabling up to 128 DUT parallel test on automotive micro-controller device at -40°C to 130°C. The presentation will highlight extensive engineering characterization results on prober deflection and thermal behavior, high pin count probe card AOT vs. POT, and low force MEMS probe on wafer pad to achieve zero defect IC wafer probing requirement.

A New Technology for Testing High Speed RF Applications Within Texas Instruments Author: Brandon Mair, Texas Instruments. Presenter: Patrick Rhodes, Product Engineer, FormFactor

High-speed testing has been a specialized area that not every probe card supplier is able to play in. There is much to be studied and understood in both design of board and also repeatability of measurements due to sensitivity of application for high volume, large site count probing. Cascade Microtech’s membrane-based Pyramid Probe card has long been one of the leading probe card technologies in the RF space. With the recent purchase of Cascade Microtech by Formfactor, there is now the opportunity to evaluate some of Formfactor’s technologies for high speed. This paper will look to compare and contrast the performance of FormFactor’s Katana RFx technology to the Pyramid Probe results. This paper will compare and contrast the two technologies on the same device and look to provide another option for RF testing using the Katana RFx pin.

TRACK F: POWER DEVICES

Role of Wide Bandgap Semiconductors in Next-Generation Power ConvertersSrabanti Chowdhury, University of California, Davis

Wide bandgap semiconductors present a pathway to push the limits of power conversion efficiency beyond that available from Silicon-based devices, enabling significant energy savings. Recent progress in Gallium Nitride (GaN)-based power electronic devices has been compelling. Reducing conversion losses is not only critical for minimizing consumption of limited resources, it simultaneously enables new compact architectures, the basis for a new industry offering increased power conversion performance at reduced system cost. This is because GaN devices enable power electronics with 1) higher efficiency at higher frequency of operation and 2) higher efficiency over a wider range of operating temperature, compared with what is possible with Si, which is approaching its physical material limit in power conversion. High efficiency operation at higher operating frequency reduces the size, weight and cost of the overall system by reducing the size of the passive components and the heat sink. GaN-based Photovoltaic (PV) inverters have achieved efficiency above 98% at a pulse-width modulation frequency of 50 kHz (vs. 96% with Si at 15 kHz), reducing loss by 50%, thereby shrinking the PV inverter size by 40%. While Lateral GaN devices are more matured in technology and have entered the medium power conversion market (up to 10 kW), Vertical GaN devices are evolving to address high power conversion (10 kW-10 MW). The novelty of the device design can be extended beyond GaN to other wider bandgap materials like Gallium Oxide, Aluminum Nitride and Diamond for more futuristic power and other novel fields like photovoltaic and GHz-THz frequency applications.

Forget the Paschen and Embrace Turbulence! Adam Shultz, Celadon Systems

Celadon, jointly with Keithley Instruments, will present a unique and unconventional approach to very high-voltage on-wafer testing. Paschen’s Law has historically been used by engineers as the reference curve for voltage breakdown as a function of gas pressure and gap distance. After extensive data collection and analysis, the presentation will reveal unexpected and compelling results regarding Paschen’s Law. Further, a surprising correlation between high-voltage “soft fails” and Time Dependent Dielectric

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Breakdown (TDDB) reliability testing techniques has been discovered and will be reviewed. When taking high-voltage measurements, surface arcing must be suppressed to prevent damage to the device; a simple yet effective solution called Direct Jet™ will be presented as part of the overall test solution. The on-wafer test solution of high-power devices up to 3 kV which will be presented, is an easy-to-use and safe method for obtaining accurate results under extreme test conditions.

INTERACTIVE WORKSHOP SESSIONSFor the first time, COMPASS offers educational workshop sessions. Our subject experts will share their experiences and knowledge, give you practical tips and answer your questions. The workshop is offered as modules, to keep the class size small and encourage open discussions. Most sessions will be repeated twice, so you can attend more than one.

SESSION TITLES

1. mm Solution for On-wafer Measurements (Suren Singh, Keysight Technologies)2. Prober Implementation for On-wafer Measurements at 120 GHz (Gavin Fisher, FormFactor)3. RF Multisite Calibration (Daniel Bock, FormFactor)4. How to Optimize Probe Card Touchdown (Alan Liao, FormFactor)5. Probe Card Selection Guide (Ashish Bhardwaj, FormFactor)6. Adjustable Multi-Site Probing Solution for WLR Testing (Eric Wilcox, FormFactor)7. Cleaning Solutions for FormFactor Probe Cards (Doug Odrick, FormFactor)8. Ultra-high Parallel Test Enabled Through Tester Resource Enhancement (Michael Huebner, FormFactor)

INTERACTIVE WORKSHOP SCHEDULE

Grand Ballroom Montara Room Mirada Room

12:45-13:15 1 3 6

13:20-13:50 2 4 7

13:55-14:25 1 5 3

14:30-15:00 2 6 4

15:05-15:35 8 7 5

SESSION DESCRIPTIONS

1. Millimeter-wave Solution for On-wafer Measurements This presentation will focus on the key aspects of a mmW VNA designed for on-wafer measurements. We will cover the hardware

architecture of the solution focusing on the key performance parameters that enable on-wafer measurements, as well as how to optimize the measurement of on-wafer devices and components.

2. Prober Implementation for mmW On-wafer Measurements at 120 GHz We will show an example of a new programmable positioner which automates the process of moving mmW probes on multi-device

layout, and a new chuck enclosure that minimizes cable length to reduce insertion loss, improving raw directivity and stability. Results will be shown regarding system stability as a function of time, calibration repeatability, and a cross comparison of device measurements from one system to another.

3. RF Multi-site Calibration We will go over how to get the most out of the use of Keysight VNAs in order to get an excellent RF calibration in multi-port probing

designs.

4. How to Optimize Probe Card Touchdown The optimized touch down has a direct impact on the overall cost of test and yield. In this session, we will review factors that could

affect the touchdown and discuss how your probe card touchdown can be improved.

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5. Probe Card Selection Guide There are various types of applications in the market today that require different set of probe card capabilities for their wafer

test. Each probe card technology has different set of capabilities and cater to specific design requirements such as speed, pitch, pad/bump type and parallelism. We will discuss the selection of probe technology based on the application space and cost of ownership.

6. Adjustable Multi-Site Probing Solution for WLR Testing Traditional 4.5” and full wafer multi-site probe cards for WLR testing have fixed test sites with no adjustability, thus the probe card

is designed specifically for one wafer layout, and additional probe cards are required for each wafer with a different layout or die size. We will review a multi-site probing solution that addresses this challenge by achieving independent adjustability for each of the test sites.

7. Cleaning Solutions for FormFactor Probe Cards This presentation explores the options for online and offline cleaning of various FormFactor probe technologies. We will discuss

why cleaning is needed and the recommended cleaning solutions for our various probes. Also, we will study a trade-off between maintaining stable CRES and maximizing probe lifetime.

8. Ultra-high Parallel Test Enabled Through Tester Resource Enhancement Most probe cards for memory device test (DRAM of Flash) take advantage of Tester Resource Enhancement (TRE) or Advanced

Tester Resource Enhancement (ATRE). TRE is generally a split of control signals where ATRE technology generally uses Multiplexing circuits to use DC and power resources on multiple DUTs. We will review the basic aspects of TRE and ATRE, a detailed overview of the implementation, control and capabilities of circuits on ultra-high parallel memory probe cards.