dual, low power, 8-/10-/12-/14-bit txdacdigital-to-analog ... · ad9717 nsd @ 1 mhz output, 125...

Dual, Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters

Data Sheet AD9714/AD9715/AD9716/AD9717

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES Power dissipation @ 3.3 V, 2 mA output

37 mW @ 10 MSPS 86 mW @ 125 MSPS

Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist

84 dBc @ 1 MHz output 75 dBc @ 10 MHz output

AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz Differential current outputs: 1 mA to 4 mA 2 on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS Wireless infrastructures

Picocell, femtocell base stations Medical instrumentation

Ultrasound transducer excitation Portable instrumentation

Signal generators, arbitrary waveform generators

GENERAL DESCRIPTION The AD9714/AD9715/AD9716/AD9717 are pin-compatible, dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of commu-nication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.

The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS.

The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications.

PRODUCT HIGHLIGHTS 1. Low Power.

DACs operate on a single 1.8 V to 3.3 V supply; total powerconsumption reduces to 35 mW at 125 MSPS with a 1.8 Vsupply. Sleep and power-down modes are provided for lowpower idle periods.

2. CMOS Clock Input.High speed, single-ended CMOS clock input supports a125 MSPS conversion rate.

3. Easy Interfacing to Other Components.Adjustable output common mode from 0 V to 1.2 V allows easy interfacing to other components that accept common-mode levels greater than 0 V.

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AD9714/AD9715/AD9716/AD9717 Data Sheet

Rev. B | of 80

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5

DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 7 AC Specifications .......................................................................... 8

Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 18 Terminology .................................................................................... 31 Theory of Operation ...................................................................... 32 Serial Peripheral Interface (SPI) ................................................... 33

General Operation of the Serial Interface ............................... 33 Instruction Byte .......................................................................... 33 Serial Interface Port Pin Descriptions ..................................... 33 MSB/LSB Transfers..................................................................... 34 Serial Port Operation ................................................................. 34 Pin Mode ..................................................................................... 34

SPI Register Map ............................................................................. 35 SPI Register Descriptions .............................................................. 36 Digital Interface Operation ........................................................... 40

Digital Data Latching and Retimer Block ............................... 41

Estimating the Overall DAC Pipeline Delay........................... 42 Reference Operation .................................................................. 43 Reference Control Amplifier .................................................... 43 DAC Transfer Function ............................................................. 44 Analog Output ............................................................................ 44 Self-Calibration ........................................................................... 45 Coarse Gain Adjustment ........................................................... 46 Using the Internal Termination Resistors ............................... 47

Applications Information .............................................................. 48 Output Configurations .............................................................. 48 Differential Coupling Using a Transformer ............................... 48 Single-Ended Buffered Output Using an Op Amp ................ 48 Differential Buffered Output Using an Op Amp ................... 49 Auxiliary DACs........................................................................... 49 DAC-to-Modulator Interfacing ................................................ 50 Correcting for Nonideal Performance of Quadrature Modulators on the IF-to-RF Conversion ................................ 50 I/Q-Channel Gain Matching .................................................... 50 LO Feedthrough Compensation .............................................. 51 Results of Gain and Offset Correction .................................... 51 Modifying the Evaluation Board to Use the ADL5370 On-Board Quadrature Modulator................................................... 52

Evaluation Board Shematics and Artwork .................................. 53 Schematics ................................................................................... 53 Silkscreens ................................................................................... 61

Bill of Materials ............................................................................... 76 Outline Dimensions ....................................................................... 79

Ordering Guide .......................................................................... 79


Rev. B | of 80

REVISION HISTORY 1/2018—Rev. A to Rev. B Changes to Figure 94 ...................................................................... 41 Changes to Estimating the Overall DAC Pipeline Section ........ 42 Changes to Ordering Guide ........................................................... 79

3/2009—Rev. 0 to Rev. A Changes to Figure 1........................................................................... 4 Changed DVDD = 3.3 V to DVDD = 1.8 V, Table 1 Conditions ............................................................................ 5 Changes to Table 1 ............................................................................ 5 Changed DVDD = 3.3 V to DVDD = 1.8 V, Table 2 Conditions ............................................................................ 7 Changed DVDD = 3.3 V to DVDD = 1.8 V, and DVDDIO = 1.8 V to DVDDIO = 3.3 V, Table 3 Conditions ....................................... 8 Changed DVDD = 3.3 V to DVDD = 1.8 V, CVDD = 3.3 V to CVDD = 1.8 V, Table 4 Conditions ................................................. 8 Changes to Table 5 and Table 6 ....................................................... 9 Changes to Figure 2 and Table 7 ................................................... 10 Changes to Figure 3 and Table 8 ................................................... 12 Changes to Figure 4 and Table 9 ................................................... 14 Changes to Table 10 ........................................................................ 16 Changes to Typical Performance Characteristics Section ......... 18 Changes to Figure 84 and Theory of Operation Section ........... 32 Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34 Changes to Pin Mode Section ........................................................ 35

Changes to Table 13 ........................................................................ 36 Changes to Table 14 ........................................................................ 37 Changes to Digital Interface Operation Section and Figure 89 to Figure 93 ........................................................................................... 40 Changes to Digital Data Latching and Retimer Block Section, Figure 94, and Retimer Section ..................................................... 41 Changes to Estimating the Overall DAC Pipeline Delay Section .............................................................................................. 42 Added Reference Operation Section, Figure 96, Recommendations When Using an External Reference Section, and Reference Control Amplifier Section.................................... 43 Added Table 17; Renumbered Sequentially ................................. 43 Added DAC Transfer Function Section and Analog Output Section .............................................................................................. 44 Changes to Figure 99 and Figure 100 ........................................... 46 Changes to Auxiliary DACs Section and Figure 107.................. 49 Changes to DAC-to-Modulator Interfacing Section and Figure 108 ......................................................................................... 49 Changes to Figure 108 and Figure 109 ......................................... 50 Added Evaluation Board Schematics and Artwork Section, and Figure 112 to Figure 134 ................................................................. 53 Added Bill of Materials Section and Table 18 ............................. 76

8/2008—Revision 0: Initial Version


Rev. B | of 80

FUNCTIONAL BLOCK DIAGRAM

I DAC

Q DAC

AUX1DAC

AUX2DAC

BANDGAP

CLOCKDIST

10kΩ

QRSET16kΩ

IRSET16kΩ

IREF100µA

IRCML1kΩ TO

250Ω

QRCML1kΩ TO

250Ω

500Ω

500Ω

500Ω

500Ω

SPIINTERFACE

1 INTO 2INTERLEAVED

DATAINTERFACE

I DATA

Q DATA1.8VLDO

1V AD9717

0726

5-00

1

RLIN

IOUTN

IOUTP

RLIP

AVDD

AVSS

RLQP

QOUTP

QOUTN

RLQN

DB11

DB10

DB9

DB8

DVDDIO

DVSS

DVDD

DB7

DB6

DB5

DB

12

DB

13 (

MS

B)

CS

/PW

RD

N

SD

IO/F

OR

MA

T

SC

LK

/CL

KM

D

RE

SE

T/P

INM

D

RE

FIO

FS

AD

JI/A

UX

I

FS

AD

JQ/A

UX

Q

CM

LI

DB

4

DB

3

DB

2

DB

1

DB

0 (L

SB

)

DC

LK

IO

CV

DD

CL

KIN

CV

SS

CM

LQ

Figure 1.


Rev. B | of 80

SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted.

Table 1.

Parameter AD9714 AD9715 AD9716 AD9717

Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max RESOLUTION 8 10 12 14 Bits

ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V

Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.7 LSB Postcalibration ±0.003 ±0.01 ±0.2 ±1.0 LSB

Integral Nonlinearity (INL) Precalibration ±0.025 ±0.13 ±0.4 ±1.8 LSB Postcalibration ±0.01 ±0.05 ±0.3 ±1.3 LSB

ACCURACY, AVDD = DVDDIO = CVDD = 1.8 V

Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.2 LSB Postcalibration ±0.005 ±0.01 ±0.2 ±1.0 LSB

Integral Nonlinearity (INL) Precalibration ±0.025 ±0.12 ±0.4 ±1.5 LSB Postcalibration ±0.02 ±0.05 ±0.25 ±1.1 LSB

MAIN DAC OUTPUTS Offset Error −1 0 +1 −1 0 +1 −1 0 +1 −1 0 +1 mV Gain Error

Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR Full-Scale Output Current1

AVDD = 3.3 V 1 2 4 1 2 4 1 2 4 1 2 4 mA AVDD = 1.8 V 1 2 2.5 1 2 2.5 1 2 2.5 1 2 2.5 mA

Output Compliance Range −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 V Output Resistance 200 200 200 200 MΩ Crosstalk, Q DAC to I DAC

fOUT = 30 MHz 97 97 97 97 dB fOUT = 60 MHz 78 78 78 78 dB

MAIN DAC TEMPERATURE DRIFT Offset 0 0 0 0 ppm/°C Gain ±40 ±40 ±40 ±40 ppm/°C Reference Voltage ±25 ±25 ±25 ±25 ppm/°C

AUXDAC OUTPUTS Resolution 10 10 10 10 Bits Full-Scale Output Current

(Current Sourcing Mode) 125 125 125 125 µA

Voltage Output Mode VSS VDD VSS VDD VSS VDD VSS VDD V Output Compliance Range

(Sourcing 1 mA) VSS VDD −

0.25 VSS VDD −

0.25 VSS VDD −

0.25 VSS VDD −

0.25 V

Output Compliance Range (Sinking 1 mA)

VSS + 0.25

VDD VSS + 0.25

VDD VSS + 0.25

VDD VSS + 0.25

VDD V

Output Resistance in Current Output Mode, AVSS to 1 V

1 1 1 1 MΩ

AUX DAC Monotonicity Guaranteed

10 10 10 10 Bits

REFERENCE OUTPUT Internal Reference Voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 V Output Resistance 10 10 10 10 kΩ


Rev. B | of 80


Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

REFERENCE INPUT Voltage Compliance

AVDD = 3.3 V 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 V AVDD = 1.8 V 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 V

Input Resistance External Reference Mode

1 1 1 1 MΩ

DAC MATCHING Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % FSR

ANALOG SUPPLY VOLTAGES AVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V CVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V

DIGITAL SUPPLY VOLTAGES DVDD 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 V DVDDIO 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V

POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 3.3 V

fDAC = 125 MSPS, IF = 12.5 MHz 86 86 86 86 mW IAVDD 10 10 10 10 mA IDVDD + IDVDDIO

11 11 11 11 mA ICVDD 3 3 3 3 mA Power-Down Mode with Clock 50 50 50 50 mW Power-Down Mode, No Clock 1.5 1.5 1.5 1.5 mW Power Supply Rejection Ratio −0.04 −0.04 −0.04 −0.04 % FSR/V

POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 1.8 V.

fDAC = 125 MSPS, IF = 12.5 MHz 35 35 35 35 mW IAVDD 10 10 10 10 mA IDVDD + IDVDDIO 8 8 8 8 mA ICVDD 1.5 1.5 1.5 1.5 mA Power-Down Mode with Clock 12 12 12 12 mW Power-Down Mode, No Clock 850 850 850 850 µW Power Supply Rejection Ratio −0.001 −0.001 −0.001 −0.001 % FSR/V

OPERATING RANGE –40 +25 +85 –40 +25 +85 –40 +25 +85 –40 +25 +85 °C 1 Based on a 10 kΩ external resistor.


Rev. B | of 80

DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted.

Table 2. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN)

VIH 2.1 3 V VIL 0 0.9 V Maximum Clock Rate 125 MSPS

SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 25 MHz Minimum Pulse Width High 20 ns Minimum Pulse Width Low 20 ns

INPUT DATA 1.8 V Q Channel or DCLKIO Falling Edge

Setup 0.25 ns Hold 1.2 ns

1.8 V I Channel or DCLKIO Rising Edge Setup 0.13 ns Hold 1.1 ns

3.3 V Q Channel or DCLKIO Falling Edge Setup −0.2 ns Hold 1.5 ns

3.3 V I Channel or DCLKIO Rising Edge Setup −0.2 ns Hold 1.6 ns

VIH 2.1 3 V VIL 0 0.9 V


Rev. B | of 80

AC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted.

Table 3.


Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fDAC = 125 MSPS, fOUT = 10 MHz 75 82 83 84 dBc fDAC = 125 MSPS, fOUT = 50 MHz 60 61 62 63 dBc

TWO TONE INTERMODULATION DISTORTION (IMD)


NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING

fDAC = 125 MSPS, fOUT = 10 MHz −129 −141 −149 −152 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −123 −135 −137 −141 dBc/Hz

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

fDAC = 61.44 MSPS, fOUT = 20 MHz −71 −71 −71 −71 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz −72 −72 −72 −72 dBc

TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted.

Table 4.


Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max SPURIOUS-FREE DYNAMIC RANGE (SFDR)


TWO TONE INTERMODULATION DISTORTION (IMD)


NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING

fDAC = 125 MSPS, fOUT = 10 MHz −132 −141 −146 −148 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −126 −131 −131 −132 dBc/Hz

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

fDAC = 61.44 MSPS, fOUT = 20 MHz −68 −68 −68 −68 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz −68 −68 −68 −68 dBc


Rev. B | of 80

ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating

AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS −0.3 V to +3.9 V DVDD to DVSS −0.3 V to +2.1 V AVSS to DVSS, CVSS −0.3 V to +0.3 V DVSS to AVSS, CVSS −0.3 V to +0.3 V CVSS to AVSS, DVSS −0.3 V to +0.3 V REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS −0.3 V to AVDD + 0.3 V QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS

−1.0 V to AVDD + 0.3 V

DBn1 (MSB) to DB0 (LSB), CS, SCLK, SDIO, RESET to DVSS

−0.3 V to DVDDIO + 0.3 V

CLKIN to CVSS −0.3 V to CVDD + 0.3 V Junction Temperature 125°C Storage Temperature Range −65°C to +150°C 1 n stands for 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13

for the AD9717.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE

Table 6. Package Type θJA θJB

1 θJC1 Unit

40-Lead LFCSP (with No Airflow Movement)

29.8 19.0 3.4 °C/W

1 These calculations are intended to represent the thermal performance of the

indicated packages using a JEDEC multilayer test board. Do not assume the same level of thermal performance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations.

ESD CAUTION


Rev. B | of 80

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

0726

5-06

6

PIN 1INDICATOR

1DB52DB43DB34DB25DVDDIO6DVSS7DVDD8DB19DB0 (LSB)

10NC

23 QOUTP24 RLQP25 AVSS26 AVDD27 RLIP28 IOUTP29 IOUTN30 RLIN

22 QOUTN21 RLQN

11N

C12

NC

13N

C

15N

C

17C

VDD

16D

CLK

IO

18C

LKIN

19C

VSS

20C

MLQ

14N

C

33FS

AD

JI/A

UXI

34R

EFIO

35R

ESET

/PIN

MD

36SC

LK/C

LKM

D37

SDIO

/FO

RM

AT3839

DB

7 (M

SB)

40D

B6

32FS

AD

JQ/A

UXQ

31C

MLI

TOP VIEW(Not to Scale)

AD9714

NOTES1. NC = NO CONNECT2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.

CS/

PWR

DN

Figure 2. AD9714 Pin Configuration

Table 7. AD9714 Pin Function Descriptions Pin No. Mnemonic Description 1 to 4 DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a

1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 DB1 Digital Inputs. 9 DB0 (LSB) Digital Input (LSB). 10 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to

the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω.

21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally.

22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTN externally.


Rev. B | of 80

Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the

on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the Using the Internal Termination Resistors section). The recommended value for this external resistor is 0 Ω.

32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.

Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.

33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is full-scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.

Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output.

34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values.

A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When

DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section).

37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-

down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the two complement input data format.

38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.

Power-Down (PWRDN). In pin mode, PWRDN powers down the device except for the SPI port. 39 DB7 (MSB) Digital Input (MSB). 40 DB6 Digital Input. 41 (EPAD) Exposed Pad

(EPAD) The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the package corners is connected to this pad.


Rev. B | of 80

072

65-0

67

PIN 1INDICATOR

1DB72DB63DB54DB45DVDDIO6DVSS7DVDD8DB39DB2

10DB1


22 QOUTN21 RLQN

11D

B0

(LS

B)

12N

C13

NC

15N

C

17C

VD

D16

DC

LK

IO

18C

LK

IN19

CV

SS

20C

ML

Q

14N

C

33F

SA

DJI

/AU

XI

34R

EF

IO35

RE

SE

T/P

INM

D36

SC

LK

/CL

KM

D37

SD

IO/F

OR

MA

T3839

DB

9 (M

SB

)40

DB

8

32F

SA

DJQ

/AU

XQ

31C

ML

I


AD9715


CS

/PW

RD

N



1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 10 DB[3:1] Digital Inputs. 11 DB0 (LSB) Digital Input (LSB). 12 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to






IOUTN externally.


Rev. B | of 80





33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.






37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low

(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format.

38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.

Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.

39 DB9 (MSB) Digital Input (MSB). 40 DB8 Digital Input. 41 (EPAD) Exposed Pad



Rev. B | of 80

072

65-0

03

PIN 1INDICATOR


10DB3


22 QOUTN21 RLQN

11D

B2

12D

B1

13D

B0

(LS

B)

15N

C

17C

VD

D16

DC

LK

IO

18C

LK

IN19

CV

SS

20C

ML

Q

14N

C

33F

SA

DJI

/AU

XI

34R

EF

IO35

RE

SE

T/P

INM

D36

SC

LK

/CL

KM

D37

SD

IO/F

OR

MA

T3839

DB

11 (

MS

B)

40D

B10

32F

SA

DJQ

/AU

XQ

31C

ML

I


AD9716


CS

/PW

RD

N



1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 12 DB[5:1] Digital Inputs. 13 DB0 (LSB) Digital Input (LSB). 14, 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to






IOUTN externally.


Rev. B | of 80


















Rev. B | of 80

PIN 1INDICATOR


10DB5


22 QOUTN21 RLQN

11D

B4

12D

B3

13D

B2

15D

B0

(LS

B)

17C

VD

D16

DC

LK

IO

18C

LK

IN19

CV

SS

20C

ML

Q

14D

B1

33F

SA

DJI

/AU

XI

34R

EF

IO35

RE

SE

T/P

INM

D36

SC

LK

/CL

KM

D37

SD

IO/F

OR

MA

T3839

DB

13 (

MS

B)

40D

B12

32F

SA

DJQ

/AU

XQ

31C

ML

I


0726

5-0

02

AD9717

NOTES1. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.

CS

/PW

RD

N



1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 14 DB[7:1] Digital Inputs. 15 DB0 (LSB) Digital Input (LSB). 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to






IOUTN externally.


Rev. B | of 80


















Rev. B | of 80

TYPICAL PERFORMANCE CHARACTERISTICS IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. DVDD is always at 1.8 V.

1.5

1.0

0.5

0

–0.5

–1.0

–1.50 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

PREC

ALI

BR

ATI

ON

INL

(LSB

)

0726

5-00

4

Figure 6. AD9717 Precalibration INL at 1.8 V (DVDD = 1.8 V)

1.5

1.0

0.5

0

–0.5

–1.0

–1.50 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

PREC

ALI

BR

ATI

ON

DN

L (L

SB)

0726

5-00

5

Figure 7. AD9717 Precalibration DNL at 1.8 V (DVDD = 1.8 V)

1.75

1.25

0.75

0.25

–0.75

–0.25

–1.25

–1.750 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

PREC

ALI

BR

ATI

ON

INL

(LSB

)

0726

5-00

6

Figure 8. AD9717 Precalibration INL at 3.3 V (DVDD = 1.8 V)

1.5

1.0

0.5

0

–0.5

–1.0

–1.50 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

POST

CA

LIB

RA

TIO

N IN

L (L

SB)

0726

5-00

7

Figure 9. AD9717 Postcalibration INL at 1.8 V (DVDD = 1.8 V)

1.5

1.0

0.5

0

–0.5

–1.0

–1.50 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

POST

CA

LIB

RA

TIO

N D

NL

(LSB

)

0726

5-00

8

Figure 10. AD9717 Postcalibration DNL at 1.8 V (DVDD = 1.8 V)

1.75

1.25

0.75

0.25

–0.75

–0.25

–1.25

–1.750 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

POST

CA

LIB

RA

TIO

N IN

L (L

SB)

0726

5-00

9

Figure 11. AD9717 Postcalibration INL at 3.3 V (DVDD = 1.8 V)


Rev. B | of 80

1.75

1.25

0.75

0.25

–0.75

–0.25

–1.25

–1.750 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

PR

EC

AL

IBR

AT

ION

DN

L (

LS

B)

072

65-0

10

Figure 12. AD9717 Precalibration DNL at 3.3 V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PR

EC

AL

IBR

AT

ION

IN

L (

LS

B)

072

65-

011

Figure 13. AD9716 Precalibration INL at 1.8 V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PR

EC

AL

IBR

AT

ION

DN

L (

LS

B)

072

65-

012


1.75

1.25

0.75

0.25

–0.75

–0.25

–1.25

–1.750 2048 4096 6144 8192 10,240 12,288 14,336 16,384

CODE

PO

ST

CA

LIB

RA

TIO

N D

NL

(L

SB

)

072

65-0

13

Figure 15. AD9717 Postcalibration DNL at 3.3 V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PO

ST

CA

LIB

RA

TIO

N I

NL

(L

SB

)

072

65-

014

Figure 16. AD9716 Postcalibration INL at 1.8 V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PO

ST

CA

LIB

RA

TIO

N D

NL

(L

SB

)

072

65-

015



Rev. B | of 80

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PR

EC

AL

IBR

AT

ION

IN

L (

LS

B)

072

65-

016


0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PR

EC

AL

IBR

AT

ION

DN

L (

LS

B)

072

65-

017


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PR

EC

AL

IBR

AT

ION

IN

L (

LS

B)

072

65-0

18


0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PO

ST

CA

LIB

RA

TIO

N I

NL

(L

SB

)

072

65-

019


0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.40 512 1024 1536 2048 2560 3072 3584 4096

CODE

PO

ST

CA

LIB

RA

TIO

N D

NL

(L

SB

)

072

65-

020


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PO

ST

CA

LIB

RA

TIO

N I

NL

(L

SB

)

072

65-0

21



Rev. B | of 80

0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PR

EC

AL

IBR

AT

ION

DN

L (

LS

B)

072

65-0

22


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PR

EC

AL

IBR

AT

ION

IN

L (

LS

B)

072

65-0

23


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PR

EC

AL

IBR

AT

ION

DN

L (

LS

B)

072

65-0

24


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PO

ST

CA

LIB

RA

TIO

N D

NL

(L

SB

)

072

65-0

25


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PO

ST

CA

LIB

RA

TIO

N I

NL

(L

SB

)

072

65-0

26


0.13

0.08

0.03

–0.02

–0.07

–0.120 128 256 384 512 640 768 896 1024

CODE

PO

ST

CA

LIB

RA

TIO

N D

NL

(L

SB

)

072

65-0

27



Rev. B | of 80

0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

PREC

ALI

BR

ATI

ON

INL

(LSB

)

0726

5-02

8

16 48 80 112 144 176 208 240


0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

PREC

ALI

BR

ATI

ON

DN

L (L

SB)

0726

5-02

9

16 48 80 112 144 176 208 240


0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

PREC

ALI

BR

ATI

ON

INL

(LSB

)

0726

5-03

0

16 48 80 112 144 176 208 240


0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

POST

CA

LIB

RA

TIO

N IN

L (L

SB)

0726

5-03

1

16 48 80 112 144 176 208 240


0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

POST

CA

LIB

RA

TIO

N D

NL

(LSB

)

0726

5-03

2

16 48 80 112 144 176 208 240


0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

POST

CA

LIB

RA

TIO

N IN

L (L

SB)

0726

5-03

3

16 48 80 112 144 176 208 240



Rev. B | of 80

0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

PR

EC

AL

IBR

AT

ION

DN

L (

LS

B)

072

65-0

34

16 48 80 112 144 176 208 240


–126

–132

–138

–144

–150

–1560 5 10 15 20 25 30 35 40 45 50 55

fOUT (MHz)

NS

D (

dB

c)

0726

5-0

38

AD9717

AD9715

AD9714

AD9716

Figure 37. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 1.8 V

–154

–151

–148

–145

–142

–139

–136

–133

5 10 15 20 25 30 35 40 45 50 55

fOUT (MHz)

NS

D (

dB

c)

0726

5-1

38

–40°C

+25°C

+85°C

Figure 38. AD9717 Noise Spectral Density at Three Temperatures, 1.8 V

0.025

0.020

0.015

0.010

0.005

0

–0.005

–0.010

–0.015

–0.020

–0.0250 32 64 96 128 160 192 224 256

CODE

PO

ST

CA

LIB

RA

TIO

N D

NL

(L

SB

)

072

65-0

37

16 48 80 112 144 176 208 240


–126

–129

–132

–135

–138

–141

–144

–147

–150

–153

–1560 5 10 15 20 25 30 35 40 45 50 55

fOUT (MHz)

NS

D (

dB

c)

0726

5-0

35

AD9717

AD9715

AD9714

AD9716

Figure 40. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 3.3 V

–154

–151

–148

–145

–142

–139

–136

–133

5 10 15 20 25 30 35 40 45 50 55

fOUT (MHz)

NS

D (

dB

c)

0726

5-1

41

+25°C

–40°C

+85°C

Figure 41. AD9717 Noise Spectral Density at Three Temperatures, 3.3 V


Rev. B | of 80

–157

–154

–151

–148

–145

–142

–139

–136

–133

–130

0 5 10 15 20 25 30 35 40 45 50 55

fOUT (MHz)

NS

D (

dB

c)

0726

5-1

42

1.8V, 1mA

1.8V, 2mA

Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.8 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110START 1MHz 1.5MHz/DIV STOP 16MHz

(dB

m)

072

65-0

85

Figure 43. AD9717 Two Tone Spectrum, 1.8 V

88

82

76

70

64

58

525 10 15 20 25 30 35 40 45 50

fOUT (MHz)

IMD

(d

Bc)

0726

5-09

8

AD9714AD9715AD9716AD9717

Figure 44. AD9714/AD9715/AD9716/AD9717 IMD at 1.8 V

–157

–154

–151

–148

–145

–142

–139

–136

–133

–130

0 5 10 15 20 25 30 35 40 45 50 55

fOUT (MHz)

NS

D (

dB

c)

0726

5-1

45

3.3V, 1mA

3.3V, 4mA 3.3V, 2mA

Figure 45. AD9717 Noise Spectral Density at Three Output Currents, 3.3 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100


(dB

m)

072

65-0

88

Figure 46. AD9717 Two Tone Spectrum, 3.3 V

100

94

88

82

76

705 10 15 20 25 30 35 40 45 50

fOUT (MHz)

IMD

(d

Bc)

0726

5-0

40

AD9717

AD9715

AD9714

AD9716

Figure 47. AD9714/AD9715/AD9716/AD9717 IMD at 3.3 V


Rev. B | of 80

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50

fOUT (MHz)

IMD

(d

Bc) –40°C

+85°C

+25°C

0726

5-1

48

Figure 48. AD9717 IMD at Three Temperatures, 1.8 V

88

82

76

70

64

58

525 10 15 20 25 30 35 40 45 50

fIN (MHz)

IMD

(d

Bc)

0726

5-0

89

0dB

–3dB

–6dB

Figure 49. AD9717 IMD at Three Digital Input Levels, 1.8 V

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50

fOUT (MHz)

IMD

(d

Bc)

0726

5-1

50

1mA

2mA

Figure 50. AD9717 IMD at Two Output Currents, 1.8 V

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50

fOUT (MHz)

IMD

(d

Bc)

–40°C

+85°C

+25°C

0726

5-15

1

Figure 51. AD9717 IMD at Three Temperatures, 3.3 V

91

88

85

82

79

765 10 15 20 25 30 35 40 45 50

fIN (MHz)

IMD

(d

Bc)

0726

5-0

90

0dB–3dB

–6dB

Figure 52. AD9717 IMD at Three Digital Input Levels, 3.3 V

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50

fOUT (MHz)

IMD

(d

Bc)

0726

5-1

53

1mA

2mA

4mA

Figure 53. AD9717 IMD at Three Output Currents, 3.3 V


Rev. B | of 80

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100


(dB

m)

0726

5-08

4

Figure 54. AD9717 Single-Tone Spectrum, 1.8 V

50

56

62

68

74

80

86

5 10 15 20 25 30 35 40 45 50 55 60fOUT (MHz)

SFD

R (d

Bc)

0726

5-15

5

AD9717AD9716AD9715AD9714

Figure 55. AD9714/AD9715/AD9716/AD9717 SFDR at 1.8 V

48

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50 55 60fOUT (MHz)

SFD

R (d

Bc)

0726

5-15

6

–40°C

+85°C

+25°C

Figure 56. AD9717 SFDR at Three Temperatures, 1.8 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100


(dB

m)

0726

5-08

7

Figure 57. AD9717 Single-Tone Spectrum, 3.3 V

66

69

72

75

78

84

87

81

93

90

5 10 15 20 25 30 35 40 45 50 55 60fOUT (MHz)

SFD

R (d

Bc)

0726

5-15

8

AD9717AD9716AD9715AD9714

Figure 58. AD9714/AD9715/AD9716/AD9717 SFDR at 3.3 V

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50 55 60fOUT (MHz)

SFD

R (d

Bc)

0726

5-15

9

3.3V, +85°C

3.3V, –40°C 3.3V, +25°C

Figure 59. AD9717 SFDR at Three Temperatures, 3.3 V


Rev. B | of 80

90

85

80

75

70

65

60

55

500 10 20 30 40 50 60

fIN (MHz)

SF

DR

(d

Bc)

0726

5-0

92

0dB–3dB

–6dB

Figure 60. SFDR at Three Digital Input Levels vs. fIN, 1.8 V

48

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50 55 60

fOUT (MHz)

SF

DR

(d

Bc)

1mA

2mA

0726

5-1

60

Figure 61. SFDR at Two Output Currents, 1.8 V

CENTER 22.90MHz

TOTAL CARRIER POWER –19.81dBm/7.87420MHz REF CARRIER POWER –19.81dBm/4.03420MHzRCC FILTER: OFF FILTER ALPHA 0.22

1. –19.81dBm 5.000MHz 3.840MHz –70.32 –90.13 –72.61 –92.422. –85.75dBm 10.00MHz 3.840MHz –71.81 –91.61 –71.60 –91.41 15.00MHz 3.840MHz –72.59 –92.40 –65.50 –85.31

10d

B/D

IV

VBW 300kHz

OFFSETFREQ

INTEGBW dBc dBm dBc

LOWER UPPERdBm

SPAN 38.84MHz

RES BW 30kHz SWEEP 126ms (601pts)

072

65-1

61

AC-COUPLED: UNSPECIFIEDBELOW 20MHz

Figure 62. AD9717 One-Carrier ACLR, 1.8 V

90

85

80

75

70

65

60

55

500 10 20 30 40 50 60

fIN (MHz)

SF

DR

(d

Bc)

0726

5-0

91

0dB–3dB

–6dB

Figure 63. SFDR at Three Digital Input Levels vs. fIN, 3.3 V

54

60

66

72

78

84

90

5 10 15 20 25 30 35 40 45 50 55 60

fOUT (MHz)

SF

DR

(d

Bc)

0726

5-1

62

2mA

4mA

1mA

Figure 64. SFDR at Three Output Currents, 3.3 V

CENTER 22.90MHz



10d

B/D

IV

VBW 300kHz

OFFSETFREQ

INTEGBW dBc dBm dBc

LOWER UPPERdBm

SPAN 38.84MHz


072

65-1

63


Figure 65. AD9717 One-Carrier ACLR, 3.3 V


Rev. B | of 80

–60

–65

–70

–7515 25 35 45

fOUT (MHz)

AC

LR (d

Bc)

0726

5-06

8

1mA POSTCAL

2mA POSTCAL

1mA PRECAL

2mA PRECAL

Figure 66. AD9717 One-Carrier W-CDMA First ACLR, 1.8 V

–60

–65

–70

–7515 25 35 45

fOUT (MHz)

AC

LR (d

Bc)

0726

5-07

1

1mA PRECAL

2mA PRECAL

2mA POSTCAL

1mA POSTCAL

Figure 67. AD9717 One-Carrier W-CDMA Second ACLR, 1.8 V

–60

–65

–70

–7520 30 40

fOUT (MHz)

AC

LR (d

Bc)

0726

5-07

2

1mA PRECAL

2mA PRECAL

1mA POSTCAL

2mA POSTCAL

Figure 68. AD9717 One-Carrier W-CDMA Third ACLR, 1.8 V

–60

–65

–70

–75

–8015 25 35 45

fOUT (MHz)

AC

LR (d

Bc)

0726

5-07

0

1mA POSTCAL

1mA PRECAL

2mA PRECAL

2mA POSTCAL

4mA POSTCAL

4mA PRECAL

Figure 69. AD9717 One-Carrier W-CDMA First ACLR, 3.3 V

–60

–65

–70

–75

–8015 25 35 45

fOUT (MHz)

AC

LR (d

Bc)

0726

5-07

4

1mA PRECAL

2mA PRECAL

2mA POSTCAL

4mA POSTCAL

4mA PRECAL

1mA POSTCAL

Figure 70. AD9717 One-Carrier W-CDMA Second ACLR, 3.3 V

–60

–65

–70

–75

–8020 30 40

fOUT (MHz)

AC

LR (d

Bc)

0726

5-07

5

1mA PRECAL

2mA PRECAL

2mA POSTCAL

4mA POSTCAL

4mA PRECAL

1mA POSTCAL

Figure 71. AD9717 One-Carrier W-CDMA Third ACLR, 3.3 V


Rev. B | of 80

CENTER 22.90MHz



10d

B/D

IV

VBW 300kHz

OFFSETFREQ

INTEGBW dBc dBm dBc

LOWER UPPERdBm

SPAN 38.84MHz


072

65-1

64


Figure 72. AD9717 Two-Carrier ACLR, 1.8 V

–55

–60

–65

–7015 20 25 30 35 40

fOUT (MHz)

AC

LR

(d

Bc)

072

65-0

73

2mA POSTCAL

2mA PRECAL

1mA PRECAL

1mA POSTCAL

Figure 73. AD9717 Two-Carrier W-CDMA First ACLR, 1.8 V

–55

–60

–65

–7015 20 25 30 35 40

fOUT (MHz)

AC

LR

(d

Bc)

072

65-0

77

1mA PRECAL

1mA POSTCAL

2mA PRECAL

2mA POSTCAL

Figure 74. AD9717 Two-Carrier W-CDMA Second ACLR, 1.8 V

CENTER 22.90MHz



10d

B/D

IV

VBW 300kHz

OFFSETFREQ

INTEGBW dBc dBm dBc

LOWER UPPERdBm

SPAN 38.84MHz


072

65-1

65

AC-COUPLED:UNSPECIFIEDBELOW 20MHz

Figure 75. AD9717 Two-Carrier ACLR, 3.3 V

–55

–60

–65

–70

–7515 20 25 30 35 40

fOUT (MHz)

AC

LR

(d

Bc)

072

65-0

76

1mA PRECAL

2mA PRECAL

2mA POSTCAL

4mA POSTCAL

4mA PRECAL

1mA POSTCAL

Figure 76. AD9717 Two-Carrier W-CDMA First ACLR, 3.3 V

–55

–60

–65

–70

–7515 20 25 30 35 40

fOUT (MHz)

AC

LR

(d

Bc)

072

65-0

80

1mA POSTCAL

1mA PRECAL

2mA PRECAL

2mA POSTCAL

4mA POSTCAL4mA PRECAL

Figure 77. AD9717 Two-Carrier W-CDMA Second ACLR, 3.3 V


Rev. B | of 80

–55

–60

–65

–7020 25 30 35 40

fOUT (MHz)

AC

LR

(d

Bc)

072

65-0

78

1mA PRECAL

1mA POSTCAL 2mA PRECAL

2mA POSTCAL

Figure 78. AD9717 Two-Carrier W-CDMA Third ACLR, 1.8 V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.5

–0.4

0

CODE

AU

XD

AC

DN

L (

LS

B)

128 256 384 512 640 768 896 1024

0726

5-14

7

Figure 79. AUXDAC DNL

25

20

15

10

5

00 20 40 60 80 100 120 140

fCLK (MHz)

CU

RR

EN

T (

mA

)

072

65-0

41

CVDD

TOTAL CURRENT @ 1mA OUT


DVDD

AVDD @ 1mA OUT

AVDD @ 2mA OUT

Figure 80. Supply Current vs. Clock Frequency at 1.8 V

–55

–60

–65

–70

–7520 25 30 35 40

fOUT (MHz)

AC

LR

(d

Bc)

072

65-0

81

1mA POSTCAL

1mA PRECAL

2mA PRECAL

2mA POSTCAL

4mA PRECAL4mA POSTCAL

Figure 81. AD9717 Two-Carrier W-CDMA Third ACLR, 3.3 V

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–1.0

–0.8

0

CODE

AU

XD

AC

IN

L (

LS

B)

128 256 384 512 640 768 896 1024

0726

5-14

4

Figure 82. AUXDAC INL

CVDDDVDD

30

20

10

00 20 40 60 80 100 120 140

fCLK (MHz)

CU

RR

EN

T (

mA

)

072

65-0

44



AVDD @ 1mA OUT

AVDD @ 4mA OUT

AVDD @ 2mA OUT


Figure 83. Supply Current vs. Clock Frequency at 3.3 V


Rev. B | of 80

TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.

Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTP, 0 mA output is expected when the inputs are all 0. For IOUTN, 0 mA output is expected when all inputs are set to 1.

Gain Error Gain error is the difference between the actual and the ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.

Output Compliance Range Output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temperature Drift Temperature drift is specified as the maximum change from the ambient value (25°C) to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range per degree Celsius (ppm FSR/°C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/°C).

Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.

Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate.

Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels.

Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB).

Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.


Rev. B | of 80

THEORY OF OPERATION

I DAC

Q DAC

AUX1DAC

AUX2DAC

BANDGAP

CLOCKDIST

10kΩ

QRSET16kΩ

IRSET16kΩ

IREF100µA

IRCML1kΩ TO

250Ω

QRCML1kΩ TO

250Ω

500Ω

500Ω

500Ω

500Ω

SPIINTERFACE

1 INTO 2INTERLEAVED

DATAINTERFACE

I DATA

Q DATA1.8VLDO

1V AD9717

0726

5-04

6

RLIN

IOUTN

IOUTP

RLIP

AVDD

AVSSRLQP

QOUTP

QOUTN

RLQN

DB11

DB10

DB9

DB8

DVDDIO

DVSS

DVDD

DB7

DB6

DB5

DB

12

DB

13 (M

SB)

SDIO

/FO

RM

AT

SCLK

/CLK

MD

RES

ET/P

INM

D

REF

IO

FSA

DJI

/AU

XI

FSA

DJQ

/AU

XQ

CM

LI

DB

4

DB

3

DB

2

DB

1

DB

0 (L

SB)

DC

LKIO

CVD

D

CLK

IN

CVS

S

CM

LQ

CS/

PWR

DN

Figure 84. Simplified Block Diagram

Figure 84 shows a simplified block diagram of the AD9714/ AD9715/AD9716/AD9717 that consists of two DACs, digital control logic, and a full-scale output current control. Each DAC contains a PMOS current source array capable of providing a nominal full-scale current (IxOUTFS) of 2 mA and a maximum of 4 mA. The arrays are divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an MSB current source. The remaining LSBs are binary weighted fractions of the current sources of the middle bits. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the DACs (that is, >200 MΩ).

All of these current sources are switched to one or the other of the two output nodes (IOUTP or IOUTN) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD976x family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches.

The analog and digital I/O sections of the AD9714/AD9715/ AD9716/AD9717 have separate power supply inputs (AVDD and DVDDIO) that can operate independently over a 1.8 V to 3.3 V range. The core digital section requires 1.8 V. An optional on-chip

LDO is provided for DVDDIO supplies greater than 1.8 V, or the 1.8 V can be supplied directly through DVDD. A 1.0 µF bypass capacitor at DVDD (Pin 7) is required when using the LDO.

The core is capable of operating at a rate of up to 125 MSPS. It consists of edge-triggered latches and the segment decoding logic circuitry. The analog section includes PMOS current sources, associated differential switches, a 1.0 V band gap voltage reference, and a reference control amplifier.

Each DAC full-scale output current is regulated by the reference control amplifier and can be set from 1 mA to 4 mA via an external resistor, xRSET, connected to its full-scale adjust pin (FSADJx).

The external resistor, in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IxREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IxOUTFS, is 32 × IxREF.

Optional on-chip xRSET resistors are provided that can be pro-grammed between a nominal value of 8 kΩ to 32 kΩ (4 mA to 1 mA IxOUTFS, respectively).

The AD9714/AD9715/AD9716/AD9717 provide the option of setting the output common mode to a value other than AVSS via the output common-mode pins (CMLI and CMLQ). This facilitates directly interfacing the output of the AD9714/AD9715/ AD9716/AD9717 to components that require common-mode levels greater than 0 V.


Rev. B | of 80

SERIAL PERIPHERAL INTERFACE (SPI) The serial port of the AD9714/AD9715/AD9716/AD9717 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchron-ous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9714/AD9715/AD9716/AD9717. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial interface port of the AD9714/ AD9715/AD9716/AD9717 is configured as a single I/O pin on the SDIO pin.

GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communications cycle on the AD9714/ AD9715/AD9716/AD9717. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9714/AD9715/ AD9716/AD9717, coinciding with the first eight SCLK rising edges. In Phase 2, the instruction byte provides the serial port controller of the AD9714/AD9715/AD9716/AD9717 with infor-mation regarding the data transfer cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9714/AD9715/AD9716/AD9717.

A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written.

The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9714/ AD9715/AD9716/AD9717 and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. Using one multi-byte transfer is the preferred method. Single-byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.

INSTRUCTION BYTE The instruction byte contains the information shown in Table 11.

Table 11. MSB LSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/W N1 N0 A4 A3 A2 A1 A0

R/W (Bit 7 of the instruction byte) determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 12.

Table 12. Byte Transfer Count N1 N0 Description 0 0 Transfer 1 byte 0 1 Transfer 2 bytes 1 0 Transfer 3 bytes 1 1 Transfer 4 bytes

A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. For multi-byte transfers, this address is the starting byte address. The following register addresses are generated internally by the AD9714/AD9715/AD9716/AD9717, based on the LSBFIRST bit (Register 0x00, Bit 6).

SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK—Serial Clock

The serial clock pin is used to synchronize data to and from the AD9714/AD9715/AD9716/AD9717 and to run the internal state machines. The SCLK maximum frequency is 20 MHz. All data input to the AD9714/AD9715/AD9716/AD9717 is registered on the rising edge of SCLK. All data is driven out of the AD9714/ AD9715/AD9716/AD9717 on the falling edge of SCLK.

CS—Chip Select

An active low input starts and gates a communications cycle. It allows more than one device to be used on the same serial communications lines. The SDIO/FORMAT pin reaches a high impedance state when this input is high. Chip select should stay low during the entire communications cycle.

SDIO—Serial Data I/O

The SDIO pin is used as a bidirectional data line to transmit and receive data.


Rev. B | of 80

MSB/LSB TRANSFERS The serial port of the AD9714/AD9715/AD9716/AD9717 can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0).

When LSBFIRST = 0 (MSB first), the instruction and data bytes must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from a high address to a low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle.

When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most signifi-cant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle.

The serial port controller data address of the AD9714/AD9715/ AD9716/AD9717 decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB first mode is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB first mode is active.

SERIAL PORT OPERATION The serial port configuration of the AD9714/AD9715/AD9716/ AD9717 is controlled by Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communications cycle. Care must be taken to compensate for this new configu-ration for the remaining bytes of the current communications cycle.

The same considerations apply to setting the software reset bit (Register 0x00, Bit 5). All registers are set to their default values except Register 0x00, which remains unchanged.

Use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior.

R/W N1 N0 A4 A3 A2 A1 A0 D7N D6N D5N D00D10D20D30

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

SDIO

0726

5-29

1

Figure 85. Serial Register Interface Timing, MSB First Write

R/W N1 N0 A4 A3 A2 A1 A0

D7

D6N D5N D00D10D20D30


SCLK

SDIO

SDO 072

65-2

90

CS

Figure 86. Serial Register Interface Timing, MSB First Read

A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D7ND6ND5ND4N


SCLK

SDIO

072

65-2

89

CS

Figure 87. Serial Register Interface Timing, LSB First Write


SCLK

SDIO

SDO

A0 A1 A2 A3 A4 N0 N1 R/W D10 D20 D7ND6ND5ND4N

D0

072

65-2

88

CS

Figure 88. Serial Register Interface Timing, LSB First Read

PIN MODE The AD9714/AD9715/AD9716/AD9717 can also be operated without ever writing to the serial port. With the RESET/PINMD pin tied high, the SCLK pin becomes CLKMD to provide for clock mode control (see the Retimer section), the SDIO pin becomes FORMAT and selects the input data format, and the CS/PWRDN pin serves to power down the device.

Operation is otherwise exactly as defined by the default register values in Table 13; therefore, external resistors at FSADJI and FSADJQ are needed to set the DAC currents, and both DACs are active. This is also a convenient quick checkout mode.

DAC currents can be externally adjusted in pin mode by sourcing or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ pins as desired with the fixed resistors installed. An op amp output with appropriate series resistance is one of many possibili-ties. This has the same effect as changing the resistor value. Place at least 10 kΩ resistors in series right at the DAC to guard against accidental short circuits and noise modulation. The REFIO pin can be adjusted ±25% in a similar manner, if desired.


Rev. B | of 80

SPI REGISTER MAP Table 13. Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Control 0x00 0x00 Reserved LSBFIRST Reset LNGINS Power-Down 0x01 0x40 LDOOFF LDOSTAT PWRDN Q DACOFF I DACOFF QCLKOFF ICLKOFF EXTREF Data Control 0x02 0x34 TWOS Reserved IFIRST IRISING SIMULBIT DCI_EN DCOSGL DCODBL I DAC Gain 0x03 0x00 Reserved I DACGAIN[5:0] IRSET 0x04 0x00 IRSETEN Reserved IRSET[5:0] IRCML 0x05 0x00 IRCMLEN Reserved IRCML[5:0] Q DAC Gain 0x06 0x00 Reserved Q DACGAIN[5:0] QRSET 0x07 0x00 QRSETEN Reserved QRSET[5:0] QRCML 0x08 0x00 QRCMLEN Reserved QRCML[5:0] AUXDAC Q 0x09 0x00 QAUXDAC[7:0] AUX CTLQ 0x0A 0x00 QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] AUXDAC I 0x0B 0x00 IAUXDAC[7:0] AUX CTLI 0x0C 0x00 IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] Reference Resistor 0x0D 0x00 Reserved RREF[5:0] Cal Control 0x0E 0x00 PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] Cal Memory 0x0F 0x00 CALSTATQ CALSTATI CALMEMQ[1:0] CALMEMI[1:0] Memory Address 0x10 0x00 Reserved MEMADDR[5:0] Memory Data 0x11 0x34 Reserved MEMDATA[5:0] Memory R/W 0x12 0x00 CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODE 0x14 0x00 CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Version 0x1F 0x03 Version[7:0]


Rev. B | of 80

SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted.

Table 14. Register Address Bit Name Description SPI Control 0x00 6 LSBFIRST 0 (default): MSB first, per SPI standard.

1: LSB first, per SPI standard. Note that the user must always change the LSB/MSB order in single-byte

instructions to avoid erratic behavior due to bit order errors. 5 Reset Execute software reset of SPI and controllers, reload default register values except

Register 0x00. 1: sets software reset; write 0 on the next (or any following) cycle to release reset.

4 LNGINS 0 (default): the SPI instruction word uses a 5-bit address. 1: the SPI instruction word uses a 13-bit address.

Power-Down 0x01 7 LDOOFF 0 (default): LDO voltage regulator on. 1: turns core LDO voltage regulator off. 6 LDOSTAT 0: indicates that the core LDO voltage regulator is off. 1 (default) : indicates that the core LDO voltage regulator is on. 5 PWRDN 0 (default): all analog and digital circuitry and SPI logic are powered on. 1: powers down all analog and digital circuitry except for SPI logic. 4 Q DACOFF 0 (default): turns on Q DAC output current. 1: turns off Q DAC output current. 3 I DACOFF 0 (default): turns on I DAC output current. 1: turns off I DAC output current. 2 QCLKOFF 0 (default): turns on Q DAC clock. 1: turns off Q DAC clock. 1 ICLKOFF 0 (default): turns on I DAC clock. 1: turns off I DAC clock. 0 EXTREF 0 (default): turns on internal voltage reference.

1: powers down internal voltage reference (external reference required). Data Control 0x02 7 TWOS 0 (default): unsigned binary input data format.

1: twos complement input data format. 5 IFIRST 0: pairing of data—Q first of pair on data input pads. 1 (default): pairing of data—I first of pair on data input pads. 4 IRISING 0: Q data latched on DCLKIO rising edge. 1 (default): I data latched on DCLKIO rising edge. 3 SIMULBIT 0 (default): allows simultaneous input and output enable on DCLKIO. 1: disallows simultaneous input and output enable on DCLKIO. 2 DCI_EN Controls the use of the DCLKIO pad for data clock input. 0: data clock input disabled. 1 (default): data clock input enabled. 1 DCOSGL Controls the use of the DCLKIO pad for data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. 0 DCODBL Controls the use of the DCLKIO pad for data clock output.

0 (default): DCODBL data clock output disabled. 1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive

current. I DAC Gain 0x03 5:0 I DACGAIN[5:0] DAC I fine gain adjustment; alters the full-scale current as shown in Figure 100.

Default IDACGAIN = 0x00.


Rev. B | of 80

Register Address Bit Name Description IRSET 0x04 7 IRSETEN 0 (default): IRSET resistor value for I channel is set by an external resistor connected

to the FADJI/AUXI pin. Nominal value for this external resistor is 16 kΩ. 1: enables the on-chip IRSET value to be changed for I channel. 5:0 IRSET[5:0] Changes the value of the on-chip IRSET resistor for I channel; this scales the full-scale

current of the DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 99. 000000 (default): IRSET = 16 kΩ. 011111: IRSET = 32 kΩ. 100000: IRSET = 8 kΩ. 111111: IRSET = 16 kΩ.

IRCML 0x05 7 IRCMLEN 0 (default): IRCML resistor value for the I channel is set by an external resistor connected to the CMLI pin. Recommended value for this external resistor is 0 Ω.

1: enables on-chip IRCML adjustment for I channel. 5:0 IRCML[5:0] Changes the value of the on-chip IRCML resistor for I channel; this adjusts the

common-mode level of the DAC output stage. 000000 (default): IRCML = 250 Ω. 100000: IRCML= 625 Ω. 111111: IRCML = 1 kΩ. Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] DAC Q fine gain adjustment; alters the full-scale current as shown in Figure 100.

Default QDACGAIN = 0x00. QRSET 0x07 7 QRSETEN 0 (default): QRSET resistor value for Q channel is set by an external resistor connected

to the FADJQ/AUXQ pin. Recommended value for this external resistor is 16 kΩ. 1: enables on-chip QRSET adjustment for Q channel. 5:0 QRSET[5:0] Changes the value of the on-chip QRSET resistor for Q channel; this scales the full-

scale current of the DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 99.

000000 (default): QRSET = 16 kΩ. 011111: QRSET = 32 kΩ. 100000: QRSET = 8 kΩ. 111111: QRSET = 16 kΩ. QRCML 0x08 7 QRCMLEN 0 (default): QRCML resistor value for the Q channel is set by an external resistor

connected to CMLQ pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip QRCML adjustment for Q channel. 5:0 QRCML[5:0] Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the

common-mode level of the DAC output stage. 000000 (default): QRCML = 250 Ω. 100000: QRCML = 625 Ω. 111111: QRCML = 1 kΩ. AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUXDAC Q output voltage adjustment word LSBs. 0x3FF: sets AUXDAC Q output to full scale. 0x200: sets AUXDAC Q output to midscale. 0x000 (default): sets AUXDAC Q output to bottom of scale. AUX CTLQ 0x0A 7 QAUXEN 0 (default): AUXDAC Q output disabled.

1: enables AUXDAC Q output. 6:5 QAUXRNG[1:0] 00 (default): sets AUXDAC Q output voltage range to 2 V. 01: sets AUXDAC Q output voltage range to 1.5 V. 10: sets AUXDAC Q output voltage range to 1.0 V. 11: sets AUXDAC Q output voltage range to 0.5 V. 4:2 QAUXOFS[2:0] 000 (default): sets AUXDAC Q top of range to 1.0 V. 001: sets AUXDAC Q top of range to 1.5 V. 010: sets AUXDAC Q top of range to 2.0 V. 011: sets AUXDAC Q top of range to 2.5 V. 100: sets AUXDAC Q top of range to 2.9 V. 1:0 QAUXDAC[9:8] AUXDAC Q output voltage adjustment word MSBs (default = 00).


Rev. B | of 80

Register Address Bit Name Description AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUXDAC I output voltage adjustment word LSBs. 0x3FF: sets AUXDAC I output to full scale. 0x200: sets AUXDAC I output to midscale. 0x000 (default): sets AUXDAC I output to bottom of scale. AUX CTLI 0x0C 7 IAUXEN 0 (default): AUXDAC I output disabled.

1: enables AUXDAC I output. 6:5 IAUXRNG[1:0] 00 (default): sets AUXDAC I output voltage range to 2 V. 01: sets AUXDAC I output voltage range to 1.5 V. 10: sets AUXDAC I output voltage range to 1.0 V. 11: sets AUXDAC I output voltage range to 0.5 V. 4:2 IAUXOFS[2:0] 000 (default): sets AUXDAC I top of range to 1.0 V. 001: sets AUXDAC I top of range to 1.5 V. 010: sets AUXDAC I top of range to 2.0 V. 011: sets AUXDAC I top of range to 2.5 V. 100: sets AUXDAC I top of range to 2.9 V. 1:0 IAUXDAC[9:8] AUXDAC I output voltage adjustment word MSBs (default = 00).

Reference Resistor

0x0D 5:0 RREF[5:0] Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 98) twos complement.

000000 (default): sets the value of RREF to 10 kΩ, VREF = 1.0 V. 011111: sets the value of RREF to 12 kΩ, VREF = 1.2 V. 100000: sets the value of RREF to 8 kΩ, VREF = 0.8 V. 111111: sets the value of RREF to 10 kΩ, VREF = 1.0 V. Cal Control 0x0E 7 PRELDQ 0 (default): preload Q DAC calibration reference set to 32.

1: preload Q DAC calibration reference set by user (Cal Address 1). 6 PRELDI 0 (default): preload I DAC calibration reference set to 32. 1: preload I DAC calibration reference set by user (Cal Address 1). 5 CALSELQ 0 (default): Q DAC self-calibration done. 1: select Q DAC self-calibration. 4 CALSELI 0 (default): I DAC self-calibration done. 1: select I DAC self-calibration. 3 CALCLK 0 (default): calibration clock disabled. 1: calibration clock enabled. 2:0 DIVSEL[2:0] Calibration clock divide ratio from DAC clock rate.

000 (default): divide by 256. 001: divide by 128. … 110: divide by 4. 111: divide by 2. Cal Memory 0x0F 7 CALSTATQ 0 (default): Q DAC calibration in progress.

1: calibration of Q DAC complete. 6 CALSTATI 0 (default): I DAC calibration in progress. 1: calibration of I DAC complete. 3:2 CALMEMQ[1:0] Status of Q DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user calibrated. 1:0 CALMEMI[1:0] Status of I DAC calibration memory.

00 (default): uncalibrated. 01: self-calibrated. 10: user calibrated. Memory Address 0x10 5:0 MEMADDR[5:0] Address of static memory to be accessed. Memory Data 0x11 5:0 MEMDATA[5:0] Data for static memory access.


Rev. B | of 80

Register Address Bit Name Description Memory R/W 0x12 7 CALRSTQ 0 (default): no action.

1: clear CALSTATQ. 6 CALRSTI 0 (default): no action. 1: clear CALSTATI. 4 CALEN 0 (default): no action. 1: initiate device self-calibration. 3 SMEMWR 0 (default): no action. 1: write to static memory (calibration coefficients). 2 SMEMRD 0 (default): no action. 1: read from static memory (calibration coefficients). 1 UNCALQ 0 (default): no action. 1: reset Q DAC calibration coefficients to default (uncalibrated). 0 UNCALI 0 (default): no action.

1: reset I DAC calibration coefficients to default (uncalibrated). CLKMODE 0x14 7:6 CLKMODEQ[1:0] Depending on the CLKMODEN bit setting, these two bits reflect the phase

relationship between DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if

needed to better synchronize the DACs (see the Retimer section). 4 Searching Data path retimer status bit. 0 (default): clock relationship established. 1: indicates that the internal data path retimer is searching for clock relationship

(device output is not usable while this bit is high). 3 Reacquire Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship. 2 CLKMODEN 0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and

read back in CLKMODEI[1:0] and CLKMODEQ[1:0]. 1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers. 1:0 CLKMODEI[1:0] Depending on CLKMODEN bit setting, these two bits reflect the phase

relationship between DCLKIO and CLKIN as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if

needed to better synchronize the DACs (see the Retimer section). Version 0x1F 7:0 Version[7:0] Hardware version of the device. This register is set to 0x03 for the latest version of

the device.


Rev. B | of 80

DIGITAL INTERFACE OPERATION Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format. The maximum guaranteed data rate is 250 MSPS with a 125 MHz clock. The order of data pairing and the sampling edge selection is user programmable using the IFIRST and IRISING data control bits, resulting in four possible timing diagrams. These are shown in Figure 89, Figure 90, Figure 91, and Figure 92.

DCLKIO

Z A B C D E F G H

I DATA Z B D F

Q DATA Y A C E

07

26

5-0

47

NOTES:1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717.

DB[n:0]

Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0

DCLKIO

Z A B C D E F G H

I DATA Y A C E

Q DATA X Z B D

07

26

5-0

48


DB[n:0]


DCLKIO

Z A B C D E F G H

I DATA Z B D F

Q DATA A C E G

07

26

5-0

49


DB[n:0]


DCLKIO

Z A B C D E F G H

I DATA Y A C E

Q DATA Z B D F

07

26

5-0

50


DB[n:0]


Ideally, the rising and falling edges of the clock fall in the center of the keep-in-window formed by the setup and hold times, tS and tH. Refer to Table 2 for setup and hold times. A detailed timing diagram is shown in Figure 93.

DCLKIO

072

65-0

51tS tH tS tH

DB[n:0]


Figure 93. Setup and Hold Times for All Input Modes

In addition to the different timing modes listed in Table 2, the input data can also be presented to the device in either unsigned binary or twos complement format. The format type is chosen via the TWOS data control bit.


Rev. B | of 80

4320

D-FF

1

D-FF D-FF

5

D-FFD-FF D-FF

OR

DCLKIO-INT CLKIN-INT

DB[n:0](INPUT)

TO DAC CORE IOUT

IOUT

DEL

AY1

DELAY2

DEL

AY1

RET

IMER

-CLK

IE

IE OE

DCLKIO(INPUT/OUTPUT)

CLKIN(INPUT) 07

265-

052

NOTESD-FFs:0: RISING OR FALLING EDGETRIGGERED FOR I OR Q DATA.1, 2, 3, 4: RISING EDGE TRIGGERED.

RETIMER-CLK

Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing

DIGITAL DATA LATCHING AND RETIMER BLOCK The AD9714/AD9715/AD9716/AD9717 have two clock inputs, DCLKIO and CLKIN. The CLKIN is the analog clock whose jitter affects DAC performance, and the DCLKIO is a digital clock from an FPGA that needs to have a fixed relationship with the input data to ensure that the data is picked up correctly by the flip-flops on the pads.

Figure 94 is a simplified diagram of the entire data capture system in the AD9714/AD9715/AD9716/AD9717. The double data rate input data (DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) is latched at the pads/pins either on the rising edge or the falling edge of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines which channel data is latched first (that is, I or Q). The captured data is then retimed to the internal clock (CLKIN-INT) in the retimer block before being sent to the final analog DAC core (D-FF 4), which controls the current steering output switches. All delay blocks depicted in Figure 94 are noninverting, and any wires without an explicit delay block can be assumed to have no delay.

Only one channel is shown in Figure 94 with the data pads (DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) serving as double data rate pads for both channels.

The default PINMD and SPI settings are IE = high (closed) and OE = low (open). These settings are enabled when RESET/ PINMD (Pin 35) is held high. In this mode, the user has to supply both DCLKIO and CLKIN. In PINMD, it is also recommended that the DCLKIO and the CLKIN be in phase for proper func-tioning of the DAC, which can easily be ensured by tying the pins together on the PCB. If the user can access the SPI, setting Bit 2 of SPI Address 0x02, DCI_EN, to logic low causes the CLKIN to be used as the DCLKIO also.

Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL, respectively, to logic high allows the user to obtain a DCLKIO output from the CLKIN input for use in the user’s PCB system.

It is strongly recommended that DCI_EN = DCOSGL = high or DCI_EN = DCODBL = high not be used even though the device may appear to function correctly. Similarly, do not set DCOSGL and DCODBL to logic high simultaneously.

Retimer

The AD9714/AD9715/AD9716/AD9717 have an internal data retimer circuit that compares the CLKIN-INT and DCLKIO-INT clocks and, depending on their phase relationship, selects a retimer clock (RETIMER-CLK) to safely transfer data from the DCLKIO used at the chip’s input interface to the CLKIN used to clock the analog DAC cores (D-FF 4).

The retimer selects one of the three phases shown in Figure 95. The retimer is controlled by the CLKMODE SPI bits, as shown in Table 15.

0726

5-04

2

1/2 PERIOD

1/4 PERIOD 1/2 PERIOD

DATACLOCK

RETIMER-CLKs

180°

90°

270°

Figure 95. RETIMER-CLK Phases

Note that, in most cases, more than one retimer phase works and ,in such cases, the retimer arbitrarily picks one phase that works. The retimer cannot pick the best or safest phase. If the user has a working knowledge of the exact phase relationship between DCLKIO and CLKIN (and thus DCLKIO-INT and CLKIN-INT because the delay is approximately the same for both clocks and equal to DELAY1), then the retimer can be forced to this phase with CLKMODEN = 1, as described in Table 15 and the following paragraphs.


Rev. B | of 80

Table 15. Timer Register List Bit Name Description CLKMODEQ[1:0] Q data path retimer clock selected output. Valid after the searching bit goes low. Searching High indicates that the internal data path retimer is searching for the clock relationship (DAC is not usable until it is low again). Reacquire Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship. CLKMODEN 0: uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both I and Q retimers (that is, force the retimer). CLKMODEI[1:0] I data path retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both the I and Q automatic retimer values.

Table 16. CLKMODEI/CLKMODEQ Details CLKMODEI[1:0]/CLKMODEQ[1:0] DCLKIO-to-CLKIN Phase Relationship RETIMER-CLK Selected 00 0° to 90° Phase 2 01 90° to 180° Phase 3 10 180° to 270° Phase 3 11 270° to 360° Phase 1

When RESET is pulsed high and then returns low (the part is in SPI mode), the retimer runs and automatically selects a suitable clock phase for the RETIMER-CLK within 128 clock cycles. The SPI searching bit, Bit 4 of SPI Address 0x14, returns to low, indicating that the retimer has locked and the part is ready for use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to reinitiate phase detection in the I and Q retimers at any time. CLKMODEQ[1:0] and CLKMODEI[1:0] of SPI Address 0x14 provide readback for the values picked by the internal phase detectors in the retimer (see Table 16).

To force the two retimers (I and Q) to pick a particular phase for the retimer clock (they must both be forced to the same value), CLKMODEN, Bit 2 of SPI Address 0x14, should be set high and the required phase value is written into CLKMODEI[1:0] and CLKMODEQ[1:0]. For example, if the DCLKIO and the CLKIN are in phase to the first order, the user can safely force the retimers to pick Phase 2 for the RETIMER-CLK. This forcing function may be useful for synchronizing multiple devices.

In pin mode, it is expected that the user tie CLKIN and DCLKIO together. The device has a small amount of programmable functionality using the unused SPI pins (SCLK, SDIO, and CS). If the two chip clocks are tied together, the SCLK pin can be tied to ground, and the chip uses a clock for the retimer that is 180° out of phase with the two input clocks (that is, Phase 2, which is the safest and best option). The chip has an additional option in pin mode when the redefined SCLK pin is high. Use this mode if using pin mode, but CLKIN and DCLKIO are not tied together (that is, not in phase). Holding SCLK high causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (that is, select a suitable RETIMER-CLK phase). The action of taking SCLK high causes the internal phase detector to reexamine the two clocks and determine the relative phase. Whenever the user wants to reevaluate the relative phase of the two clocks, the SCLK pin can be taken low and then high again.

ESTIMATING THE OVERALL DAC PIPELINE DELAY DAC pipeline latency is affected by the phase of the RETIMER-CLK that is selected. If latency is critical to the system and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time.

Consider the case in which DCLKIO = CLKIN (that is, in phase), and the RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, I data is latched on the rising edge and Q data is latched on the falling edge). Then the latency to the output for the I channel is four clock cycles total; one clock cycle from the input interface (D-FF 1, not D-FF0, as it latches data on either edge and does not cause any delay); two clock cycles from the retimer (D-FF 2 and D-FF 4, but not D-FF 3, because it is latched on the half clock cycle or 180°); and one clock cycle going through the analog core (D-FF 5). The latency to the output for the Q channel from the time the falling edge latches it at the pads in D-FF 0 is 3.5 clock cycles (no delay due to D-FF0, 1 clock cycle due to D-FF 1, ½ clock cycle to D-FF 2, 1 clock cycle to D-FF 4, and 1 clock cycle to D-FF 5). This latency for the AD9714/ AD9715/AD9716/AD9717 is case specific and needs to be calcu-lated based on the RETIMER-CLK phase that is automatically selected or manually forced.


Rev. B | of 80

REFERENCE OPERATION The AD9714/AD9715/AD9716/AD9717 contain an internal 1.0 V band gap reference. The internal reference can be disabled by setting Bit 0 (EXTREF) of the power-down register (Address 0x01) through the SPI interface. To use the internal reference, decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable the internal reference, and clear Bit 0 of the power-down register (Address 0x01) through the SPI interface. Note that this is the default configuration. The internal reference voltage is present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA must be used to avoid loading the reference. An example of the use of the internal reference is shown in Figure 96.

CURRENTSCALING

×32

AD9714/AD9715/AD9716/AD9717 I DAC

ORQ DAC

0726

5-21

8

IxOUTFSxRSET

0.1µF

REFIO

IxREFAVSS

FSADJx

VBG1.0V

+

–

Figure 96. Internal Reference Configuration

REFIO serves as either an input or an output, depending on whether the internal or an external reference is used. Table 17 summarizes the reference operation.

Table 17. Reference Operation Reference Mode REFIO Pin Register Setting Internal Connect 0.1 µF

capacitor Register 0x01, Bit 0 = 0 (default)

External Apply external capacitor

Register 0x01, Bit 0 = 1 (for power saving)

An external reference can be used in applications requiring tighter gain tolerances or lower temperature drift. Also, a variable external voltage reference can be used to implement a method for gain control of the DAC output.

Recommendations When Using an External Reference

Apply the external reference to the REFIO pin. The internal reference can be directly overdriven by the external reference, or the internal reference can be powered down to save power consumption

The external 0.1 μF compensation capacitor on REFIO is not required unless specified by the external voltage reference manufacturer. The input impedance of REFIO is 10 kΩ when the internal reference is powered up and 1 MΩ when it is powered down.

REFERENCE CONTROL AMPLIFIER The AD9714/AD9715/AD9716/AD9717 contain a control amplifier that regulates the full-scale output current, IxOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 96. The output current, IxREF, is determined by the ratio of the VREFIO and an external resistor, xRSET, as stated in Equation 4 (see the DAC Transfer Function section). IxREF, is mirrored to the segmented current sources with the proper scale factor to set IxOUTFS, as stated in Equation 3.

The control amplifier allows a 2.5:1 adjustment span of IxOUTFS from 1 mA to 4 mA by setting IxREF between 125 μA and 31.25 μA (set xRSET between 8 kΩ and 32 kΩ). The wide adjustment span of IxOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9714/AD9715/AD9716/AD9717, which is proportional to IxOUTFS (see the DAC Transfer Function section). The second benefit relates to the ability to adjust the output over a 8 dB range with 0.25 dB steps, which is useful for controlling the transmitted power. The small signal bandwidth of the reference control amplifier is approximately 500 kHz. This allows the device to be used for low frequency, small signal multiplying applications.

When an external resistor greater than 16 kΩ is used on the FSADJx pins, care must be taken to maintain the high frequency equivalent circuit to an impedance lower than 16 kΩ by splitting the resistor into two resistors in series with a 10 nF capacitor in parallel with the resistor to AVSS (see Figure 97).

AD9714/AD9715/AD9716/AD9717

0726

5-21

9

xRSET

0.1µF

R < 16kΩ

REFIO

AVSS

FSADJx

10nF

Figure 97. xRSET Configuration for Values > 16 kΩ


Rev. B | of 80

DAC TRANSFER FUNCTION The AD9714/AD9715/AD9716/AD9717 provide two differen-tial current outputs, IOUTP/IOUTN and QOUTP/QOUTN. IOUTP and QOUTP provide a near full-scale current output, IxOUTFS, when all bits are high (that is, DAC CODE = 2N − 1, where N = 8, 10, 12, or 14 for the AD9714, AD9715, AD9716, and AD9717, respectively), while IOUTN and QOUTN, the complementary outputs, provide no current. The current outputs appearing at the positive DAC outputs, IOUTP and QOUTP, and at the negative DAC outputs, IOUTN and QOUTN, are a function of both the input code and IxOUTFS and can be expressed as follows:

IOUTP = (IDAC CODE/2N) × IIOUTFS (1)

QOUTP = (QDAC CODE/2N) × IQOUTFS

IOUTN = ((2N − 1) − IDAC CODE)/2N × IIOUTFS (2)

QOUTN = ((2N − 1) − QDAC CODE)/2N × IQOUTFS

where: IDAC CODE and QDAC CODE = 0 to 2N − 1 (that is, decimal representation). IIOUTFS and IQOUTFS are functions of the reference currents, IIREF and IQREF, respectively, which are nominally set by a reference voltage, VREFIO, and external resistors, IRSET and QRSET, respec-tively. IIOUTFS and IQOUTFS can be expressed as follows:

IIOUTFS = 32 × IIREF (3)

IQOUTFS = 32 × IQREF

where:

IIREF = VREFIO/IRSET (4)

IQREF = VREFIO/QRSET

or

IIOUTFS = 32 × VREFIO/IRSET (5)

IQOUTFS = 32 × VREFIO/QRSET

A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically drives a resistive load directly or via a transformer. If dc coupling is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN) should be connected to matching resistive loads, xRLOAD, that are tied to analog common, AVSS. The single-ended voltage output appearing at the positive and negative nodes is

VIOUTP = IOUTP × IRLOAD (6)

VQOUTP = QOUTP × QRLOAD

VIOUTN = IOUTN × IRLOAD (7)

VQOUTN = QOUTN × QRLOAD

To achieve the maximum output compliance of 1 V at the nominal 4 mA output current, IRLOAD = QRLOAD must be set to 250 Ω.

Substituting the values of IOUTP, IOUTN, and IxREF, VIDIFF can be expressed as

VIDIFF = (2 × IDAC CODE – (2N − 1))/2N × (8)

(32 × VREFIO/IRSET) × IRLOAD

Equation 8 highlights some of the advantages of operating the AD9714/AD9715/AD9716/AD9717 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VIDIFF, is twice the value of the single-ended voltage output (that is, VIOUTP or VIOUTN), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a single-ended output (VIOUTP and VIOUTN) or differential output (VIDIFF) of the AD9714/AD9715/AD9716/ AD9717 can be enhanced by selecting temperature-tracking resistors for xRLOAD and xRSET because of their ratiometric relationship, as shown in Equation 8.

ANALOG OUTPUT The complementary current outputs in each DAC, IOUTP/ IOUTN and QOUTP/QOUTN, can be configured for single-ended or differential operation. IOUTP/IOUTN and QOUTP/ QOUTN can be converted into complementary single-ended voltage outputs, VIOUTP and VIOUTN, as well as VQOUTP and VQOUTN via a load resistor, xRLOAD, as described in the DAC Transfer Function section by Equation 6 through Equation 8. The differen-tial voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN, and VQOUTP and VQOUTN, can also be converted to a single-ended voltage via a transformer or a differential amplifier configuration. The ac performance of the AD9714/AD9715/AD9716/AD9717 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at IOUTP and IOUTN is limited to ±0.5 V. The distortion and noise performance of the AD9714/AD9715/AD9716/AD9717 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTP/IOUTN and QOUTP/QOUTN can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed wave-form increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTP/IOUTN and QOUTP/QOUTN are complementary, they become additive when processed differentially.


Rev. B | of 80

SELF-CALIBRATION The AD9714/AD9715/AD9716/AD9717 have a self-calibration feature that improves the DNL of the device. Performing a self-calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to provide much benefit. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0] (Register 0x0E, Bits[2:0]) to produce a calibration clock frequency between these values. Separate self-calibration hardware is included for each DAC. The DACs can be self-calibrated individually or simultaneously.

To perform a device self-calibration, the following procedure can be used:

1. Write 0x00 to Register 0x12. This ensures that the UNCALI and UNCALQ bits are reset.

2. Set up a calibration clock between 0.5 MHz and 4 MHz using DIVSEL[2:0], and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3).

3. Select the DAC(s) to self-calibrate by setting either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent calibration hardware so that they can be calibrated simultaneously.

4. Start self-calibration by setting the CALEN bit (Register 0x12, Bit 4). Wait approximately 300 calibration clock cycles.

5. Check if the self-calibration has completed by reading the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in Register 0x0F. Logic 1 indicates that the calibration has completed.

6. When the self-calibration has completed, write 0x00 to Register 0x12.

7. Disable the calibration clock by clearing the CALCLK bit (Register 0x0E, Bit 3).

The AD9714/AD9715/AD9716/AD9717 allow reading and writing of the calibration coefficients. There are 32 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device.

To read the calibration coefficients, use the following steps:

1. Select which DAC core to read by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Write the address of the first coefficient (0x01) to Register 0x10.

2. Set the SMEMRD bit (Register 0x12, Bit 2) by writing 0x04 to Register 0x12.

3. Read the 6-bit value of the first coefficient by reading the contents of Register 0x11.

4. Clear the SMEMRD bit by writing 0x00 to Register 0x12. 5. Repeat Step 2 through Step 4 for each of the remaining 31

coefficients by incrementing the address by 1 for each read. 6. Deselect the DAC core by clearing either Bit 4 (CALSELI)

for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.

To write the calibration coefficients to the device, use the following steps:

1. Select which DAC core to write to by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.

2. Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08 to Register 0x12.

3. Write the address of the first coefficient (0x01) to Register 0x10.

4. Write the value of the first coefficient to Register 0x11. 5. Repeat Step 2 through Step 4 for each of the remaining 31

coefficients by incrementing the address by one for each write.

6. Clear the SMEMWR bit by writing 0x00 to Register 0x12. 7. Deselect the DAC core by clearing either Bit 4 (CALSELI)

for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.


Rev. B | of 80

COARSE GAIN ADJUSTMENT Option 1

A coarse full-scale output current adjustment can be achieved using the lower six bits in Register 0x0D. This adds or subtracts up to 20% from the band gap voltage on Pin 34 (REFIO), and the voltage on the FSADJx resistors tracks this change. As a result, the DAC full-scale current varies by the same amount. A secondary effect to changing the REFIO voltage is that the full-scale voltage in the AUXDAC also changes by the same magnitude. The register uses twos complement format, in which 011111 maximizes the voltage on the REFIO node and 100000 minimizes the voltage.

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.800 8 16 24 32 40 48 56

CODE

VR

EF

072

65-0

54

Figure 98. Typical VREF Voltage vs. Code

Option 2

While using the internal FSADJx resistors, each main DAC can achieve independently controlled coarse gain using the lower six bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. The register uses twos complement format and allows the output current to be changed in approximately 0.25 dB steps.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00 10 20 30 40 50 60

xRSET CODE

OU

TP

UT

OF

I/V

CO

NV

ER

TE

R (

V)

072

65-

055

VOUT_Q OR VOUT_I

Figure 99. Effect of xRSET Code

Option 3

Even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the FSADJx pins. Any noise injected here appears as amplitude modulation of the output. Thus, a portion of the required series resistance (at least 20 kΩ) must be installed right at the pin. A range of ±10% is quite practical using this method.

Option 4

As in Option 3, when the device is in pin mode, both full-scale values can be adjusted by sourcing or sinking current from the REFIO pin. Noise injected here appears as amplitude modulation of the output; therefore, a portion of the required series resis-tance (at least 10 kΩ) must be installed at the pin. A range of ±25% is quite practical when using this method.

Fine Gain

Each main DAC has independent fine gain control using the lower six bits in Register 0x03 (I DAC gain) and Register 0x06 (Q DAC gain). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. These registers use straight binary format. One application in which straight binary format is critical is for side-band suppression while using a quadrature modulator. This is described in more detail in the Applications Information section.

2.22

2.20

2.18

2.16

2.14

2.12

2.100 8 16 24 32 40 48 56 64

GAIN DAC CODE

I OU

TF

S (

mA

)

072

65-0

56

3.3V DAC13.3V DAC21.8V DAC11.8V DAC2

Figure 100. Typical DAC Gain Characteristics


Rev. B | of 80

USING THE INTERNAL TERMINATION RESISTORS The AD9717/AD9716/AD9715/AD9714 have four 500 Ω termination internal resistors (two for each DAC output). To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent load pin. For example, on the I DAC, IOUTP must be shorted to RLIP and IOUTN must be shorted to RLIN. In addition, the CMLI or CMLQ pin must be connected to ground directly or through a resistor. If the output current is at the nominal 2 mA and the CMLI or CMLQ pin is tied directly to ground, this produces a dc common-mode bias voltage on the DAC output equal to 0.5 V. If the DAC dc bias must be higher than 0.5 V, an external resistor can be connected between the CMLI or CMLQ pin and ground. This part also has an internal common-mode resistor that can be enabled. This is explained in the Using the Internal Common-Mode Resistor section.

0726

5-05

7

I DACOR

Q DAC

RCML

CML

RLIN

IOUTN

IOUTP

RLIP

500Ω

500Ω

Figure 101. Simplified Internal Load Options

Using the Internal Common-Mode Resistor

These devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the DAC outputs. By default, the common-mode resistor is not con-nected. When enabled, it can be adjusted from ~250 Ω to ~1 kΩ. Each main DAC has an independent adjustment using the lower six bits in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]).

1200

1100

1000

900

800

700

600

500

400

300

2000 8 16 24 32 40 48 56

CODE

RE

SIS

TA

NC

E (Ω

)

072

65-0

58

Figure 102. Typical CML Resistor Value vs. Register Code

Using the CMLx Pins for Optimal Performance

The CMLx pins also serve to change the DAC bias voltages in the parts allowing them to run at higher dc output bias voltages. When running the bias voltage below 0.9 V and an AVDD of 3.3 V, the parts perform optimally when the CMLx pins are tied to ground. When the dc bias increases above 0.9 V, set the CMLx pins at 0.5 V for optimal performance. The maxi-mum dc bias on the DAC output should be kept at or below 1.2 V when the supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close to 0 V and connect the CMLx pins directly to ground.


Rev. B | of 80

APPLICATIONS INFORMATION OUTPUT CONFIGURATIONS The following sections illustrate some typical output confi-gurations for the AD9714/AD9715/AD9716/AD9717. Unless otherwise noted, it is assumed that IxOUTFS is set to a nominal 2 mA. For applications requiring the optimum dynamic perfor-mance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high fre-quency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance.

A single-ended output is suitable for applications in which low cost and low power consumption are primary concerns.

DIFFERENTIAL COUPLING USING A TRANSFORMER An RF transformer can be used to perform a differential-to-single-ended signal conversion, as shown in Figure 103. The distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. Transformer coupling provides excellent rejection of common-mode distortion (that is, even-order harmonics) over a wide frequency range. It also provides electrical isolation and can deliver voltage gain without adding noise. Transformers with different impedance ratios can also be used for impedance matching purposes. The main disadvantages of transformer coupling are low frequency roll-off, lack-of-power gain, and high output impedance.

AD9714/AD9715/AD9716/AD9717

IOUTN

IOUTP

29

28

OPTIONAL RDIFF

RLOAD

0726

5-0

59

Figure 103. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on IOUTP and IOUTN within the output common-mode voltage range of the device. Note that the dc component of the DAC output current is equal to IxOUTFS and flows out of both IOUTP and IOUTN. The center tap of the transformer should provide a path for this dc current. In most applications, AGND provides the most convenient voltage for the transformer center tap. The complemen-tary voltages appearing at IOUTP and IOUTN (that is, VIOUTP and VIOUTN) swing symmetrically around AGND and should be maintained with the specified output compliance range of the AD9714/AD9715/AD9716/AD9717.

A differential resistor, RDIFF, can be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF, as reflected by the transformer, is chosen to provide a source termination that results in a low voltage standing wave ratio (VSWR). Note that approximately half the signal power is dissipated across RDIFF.

SINGLE-ENDED BUFFERED OUTPUT USING AN OP AMP An op amp such as the ADA4899-1 can be used to perform a single-ended current-to-voltage conversion, as shown in Figure 104. The AD9714/AD9715/AD9716/AD9717 are config-ured with a pair of series resistors, RS, off each output. For best distortion performance, RS should be set to 0 Ω. The feedback resistor, RFB, determines the peak-to-peak signal swing by the formula

VOUT = RFB × IFS

The common-mode voltage of the output is determined by the formula

21 FSFB

B

FBREFCM

IR

R

RVV

The maximum and minimum voltages out of the amplifier are, respectively,

B

FBREFMAX R

RVV 1

VMIN = VMAX – IFS × RFB

+5VAD9714/AD9715/AD9716/AD9717

IOUTP

IOUTN 29

RFB

VOUT

REFIO 34

28

RS

AVSS 25

CF

C

RS

RB

0726

5-06

0+

–

ADA4899-1

–5V

Figure 104. Single-Supply Single-Ended Buffer

http://www.analog.com/ADA4899-1?doc=AD9174_9715_9716_9717.pdf


Rev. B | of 80

DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP A dual op amp (see the circuit shown in Figure 105) can be used in a differential version of the single-ended buffer shown in Figure 104. The same RC network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the DAC outputs. The feedback resistors, RFB, determine the differential peak-to-peak signal swing by the formula

VOUT = 2 × RFB × IFS

The maximum and minimum single-ended voltages out of the amplifier are, respectively,

B

FBREFMAX R

RVV 1

VMIN = VMAX − RFB × IFS

The common-mode voltage of the differential output is determined by the formula

VCM = VMAX − RFB × IFS

072

65-0

61

AD9714/AD9715/AD9716/AD9717

IOUTP

IOUTN

RFB

VOUT

REFIO 34

28

RS

AVSS 25

CF

C

RFBRB

CF

RS

RB

29

+

–ADA4841-2

+

–

ADA4841-2

Figure 105. Single-Supply Differential Buffer

AUXILIARY DACs The DACs of the AD9714/AD9715/AD9716/AD9717 feature two versatile and independent 10-bit auxiliary DACs suitable for dc offset correction and similar tasks.

Because the AUXDACs are driven through the SPI port, they should never be used in timing-critical applications, such as inside analog feedback loops.

To keep the pin count reasonable, these auxiliary DACs each share a pin with the corresponding FSADJx resistor. They are, therefore, usable only when enabled and when that DAC is operated on its internal full-scale resistors. A simple I-to-V converter is implemented on chip with selectable shunt resistors (3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2 equals 0.5 V and the following equation describes the no load output voltage:

k165.1V5.0

SDACOUT R

IV

Figure 106 illustrates the function of all the SPI bits controlling these DACs with the exception of the QAUXEN (Register 0x0A, Bit 7) and IAUXEN (Register 0x0C, Bit 7) bits and gating to prohibit RS < 3.2 kΩ.

0726

5-0

43

+

–

OP AMP

AUXDAC[9:0]

AVDDRNG0RNG1

REFIO2

16kΩ 16kΩ

16kΩ

4kΩ 8kΩ

OFS2OFS1OFS0

(OFS > 4 = 4)

AUXPIN

RNG: 00 = > 125µA fS01 = > 62µA fS10 = > 31µA fS11 = > 16µA fS

Figure 106. AUXDAC Simplified Circuit Diagram

The SPI speed limits the update rate of the auxiliary DACs. The data is inverted such that IAUXDAC is full scale at 0x000 and zero at 0x1FF, as shown in Figure 107.

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

00 10 20 30 40 50 60 70 80 90 100 120 130

IAUXDAC (µA)

OU

TP

UT

(V

)

0726

5-0

45

110

ROFFSET = 3.3kΩROFFSET = 4kΩROFFSET = 5.3kΩROFFSET = 8kΩROFFSET = 16kΩ

OP AMP OUTPUT VOLTAGE vs. CHANGESIN ROFFSET AND DAC CURRENT IN µA

Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V, No Load,

AUXDAC 0x1FF to 0x000


Rev. B | of 80

Two registers are assigned to each DAC with 10 bits for the actual DAC current to be generated, a 3-bit offset (and gain) adjust-ment, a 2-bit current range adjustment, and an enable/disable bit. Setting the QAUXOFS (Register 0x0A, Bits[4:2]) and IAUXOFS (Register 0x0C, Bits[4:2]) bits to all 1s disables the respective op amp and routes the DAC current directly to the respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is especially useful when the loads to be driven are beyond the limited capability of the on-chip amplifier.

When not enabled (QAUXEN or IAUXEN = 0), the respective DAC output is in open circuit.

DAC-TO-MODULATOR INTERFACING The auxiliary DACs can be used for local oscillator (LO) cancella-tion when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 108 and Figure 109, with the series resistor value chosen to give an appropriate adjustment range. Figure 108 also shows external load resistors in use. Often, the input common-mode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling or a dc level shift is necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, the dc blocking capacitors in Figure 108 can be removed and the on-chip resistors can be connected.

AD9714/AD9715/AD9716/AD9717

I OR Q DAC

AD9714/AD9715/AD9716/AD9717

AUX DAC

OPTIONALPASSIVE

FILTERING

MODULATORV+

QUADRATUREMODULATOR

I OR QINPUTS

499Ω

0.1µF

5kΩTO

100kΩ

0.1µF

499Ω

072

65-1

66

Figure 108. Typical Use of Auxiliary DACs and External Components for

Coupling to Quadrature Modulators

Figure 109 shows a greatly simplified circuit that takes full advantage of the internal components supplied in the DAC. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. In the example shown in Figure 109, the filter must be able to pass dc to properly bias the modulator. Placing the filter at the location shown in Figure 108 and Figure 109 allows easy design of the filter because the source and load imped-ances can easily be designed close to 500 Ω for a 2 mA full-scale output. Once the resistance at the modulator inputs is known, the user can easily look up the range of input offsets that may be encountered and compute a value for the series resistor on the AUXDAC output.

AD9714/AD9715/AD9716/AD9717

I OR Q DAC

AD9714/AD9715/AD9716/AD9717

AUX DAC

OPTIONALLOW-PASSFILTERING

ADL537xFAMILYI OR Q

INPUTS

50kΩ

500Ω 500Ω

1kΩ

0726

5-16

7

Figure 109. Simplified DC Coupling to Quadrature Modulator ADL537x

Family or Equivalent Is Enabled By Using Internal Components

CORRECTING FOR NONIDEAL PERFORMANCE OF QUADRATURE MODULATORS ON THE IF-TO-RF CONVERSION Analog quadrature modulators make it very easy to realize single sideband radios. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are gain mismatch and LO feedthrough.

Gain Mismatch

The gain in the real and imaginary signal paths of the quad-rature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect.

LO Feedthrough

The quadrature modulator has a finite dc referred offset, as well as coupling from its LO port to the signal inputs. These can lead to a significant spectral spur at the frequency of the quadrature modulator LO.

The AD9714/AD9715/AD9716/AD9717 have the capability to correct for both of these analog degradations. However, understand that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting them may be necessary.

I/Q-CHANNEL GAIN MATCHING Fine gain matching is achieved by adjusting the values in the DAC fine gain adjustment registers. For the I DAC, these values are in the I DAC gain register (Register 0x03). For the Q DAC, these values are in the Q DAC gain register (Register 0x06). These are 6-bit values that cover ±2% of full scale. To perform gain compensation starting from the default values of zero, raise the value of one of these registers a few steps until it can be deter-mined if the amplitude of the unwanted image is increased or decreased. If the unwanted image increases in amplitude, remove the step and try the same adjustment on the other DAC control register. Iterate register changes until the rejection cannot be improved further. If the fine gain adjustment range is not sufficient to find a null (that is, the register goes full scale with no null apparent), adjust the course gain settings of the two DACs accordingly and try again. Variations on this simple method are possible.


Rev. B | of 80

Note that LO feedthrough compensation is independent of phase compensation. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. Therefore, it is recommended that the gain adjustment be performed prior to LO compensation.

LO FEEDTHROUGH COMPENSATION To achieve LO feedthrough compensation in a circuit, each output of the two AUXDACs must be connected through a 100 kΩ resistor to one side of the differential DAC output. See the Auxiliary DACS section for details of how to use AUXDACs. The purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, thereby adding a slight dc bias to one or the other of the quadrature modulator signal inputs.

To achieve LO feedthrough compensation, the user should start with the default conditions of the AUXDAC registers, and then increment the magnitude of one or the other AUXDAC output voltages. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either decreasing the output voltage of the AUXDAC being adjusted, or try adjusting the output voltage of the other AUXDAC. It may take practice before an effective algorithm is achieved. The AD9714/AD9715/AD9716/AD9717 evaluation board can be used to adjust the LO feedthrough down to the noise floor, although this is not stable over temperature.

RESULTS OF GAIN AND OFFSET CORRECTION The results of gain and offset correction can be seen in Figure 110 and Figure 111. Figure 110 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 111 shows the output spectrum after correction. The LO feedthrough spur at 450 MHz has been suppressed to the noise level. This result can be achieved by applying the correc-tion, but the correction must be repeated after a large change in temperature.

Note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. It can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the DACs and quadrature modulators. Phase mismatch is frequency depen-dent; therefore, routines must be developed to adjust it if wideband signals are desired.

5

–5

–15

–25

–35

–45

–55

–65

–75

–85

–95

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

447.5 449.0 450.0 451.0 452.5

072

65-0

64

FREQUENCY (MHz)

(dB

)

Figure 110. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single-

Tone Signal at 450 MHz, No Gain or LO Compensation

5

–5

–15

–25

–35

–45

–55

–65

–75

–85

–95

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

447.5 449.0 450.0 451.0 452.5

072

65-0

65

FREQUENCY (MHz)

(dB

)

Figure 111. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single-

Tone Signal at 450 MHz, Gain and LO Compensation Optimized


Rev. B | of 80

MODIFYING THE EVALUATION BOARD TO USE THE ADL5370 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/ AD9716/AD9717 and the ADL5370 provide an easy-to-interface DAC/modulator combination that can be easily characterized on the evaluation board. Solderable jumpers can be configured to evaluate the single-ended or differential outputs of the AD9714/AD9715/AD9716/AD9717. This setup is the default configuration from the factory and consists of the following population of the components:

• JP55, JP56, JP76, JP82—unsoldered • R13, R14, R52, R53—unpopulated • R50, R57, T1, T2—populated

To evaluate the ADL5370 on this board, the population of these same components should be reversed so that they are in the following positions:

• JP55, JP56, JP76, JP82—soldered • R13, R14, R52, R53—populated • R50, R57, T1, T2—unpopulated

The AUXDAC outputs can be connected to Test Point TP44 and Test Point TP45 if LO feedthrough compensation is necessary.

http://www.analog.com/ADL5370?doc=AD9714_9715_9716_9717.pdf


Rev. B | of 80

EVALUATION BOARD SHEMATICS AND ARTWORK SCHEMATICS

5V

FBG

ND

IN3

NC

OU

T5

SD AD

P333

4

IN4

OU

T6

5V5V

CC

0603

CC0603

CC

0603

RC0603

RC

0603

RC

0603

B

A

B

A

B

A

BA

CC

0603

CC

0603

AC

ASE

CC

0603

AC

ASE

5V

5V

5V 5V

5V

RC

0603

RC

0603

5V

5V 5V

5V5V

5V

RC

0603

RC

0603

RC0603RC0603

RC0603RC0603

CC0603CC0603 CC0603

CC

0603

CC

0603

CC0603

CC

0603

CC

0603

CC

0603

CC

0603C

C06

03

CC

0603

5V

5V

5V

5V

5V 5V

5V5V AD

P333

4

AD

P333

4

BA

GN

D

IN4

SD

AD

P333

4

IN3

GN

D

IN4

SDIN3

FBG

ND

IN4

NC

OU

T5

SDIN3

OU

T6

CC

0603

CC

0603

AC

ASE

CC

0603

AC

ASE

CC

0603

BA

CC

0603

AC

ASE

CC

0603

CC

0603

FBG

ND

IN3

NC

OU

T5

SD

AD

P333

4

IN4

OU

T6

FB NC

OU

T5O

UT6

FB NC

OU

T5O

UT6

BA

SMA

EDG

E

5V

SMA

EDG

E

SMA

EDG

E

SMA

EDG

E

SMA

EDG

E

C C

5V

LC18

12

LC18

12

LC18

12

LC18

12

LC18

12

LC18

12

LC18

12

LC18

125V5V5V5V

LC18

12B

A

RC

0603

RC

0603

BA

5V

RC

0603

BA

1.8

3.3

1.8

3.3

1.8

3.3

1.8

3.3

3.3

1.8

23

1JP

88

64.9

KR

32

R9 2

64.9

K

78.7

KR

4

13

2 JP89

R3

78.7

K

78.7

KR

291

32 JP

29

DVD

DX_

INC

VDD

X_IN

AVD

D_I

N

DVD

D_I

N

CVD

D_I

N

L3

EXC

-CL4

532U

1

EXC

-CL4

532U

1

L16

L19

EXC

-CL4

532U

1

BLK

TP23

TP24

RED

CVD

DX_

INC

VDD

X

L4

EXC

-CL4

532U

1

EXC

-CL4

532U

1L1

2

RED

TP8

TP9

BLK

DVD

DX_

IND

VDD

X

EXC

-CL4

532U

1L7

TP6

BLK

RED

TP5

AVD

D_I

NA

VDD

L1

EXC

-CL4

532U

1

EXC

-CL4

532U

1L5

EXC

-CL4

532U

1L6

BLK

TP4

TP13

RED

DVD

D_I

N

BLK

TP14

RED

TP12

C10

0.1U

F

DVD

D

CVD

DC

VDD

_IN

2

15VG

ND

;3,4

,5 J8

1

2

J5

5VG

ND

;3,4

,5

1

2

5VG

ND

;3,4

,5 J2

2

1J4

5VG

ND

;3,4

,5

31

2

JP6

875

12346

U2

C2

6.3V

10U

F

C7

0.1U

F

0.1U

F

C3

13

2 JP22

C8

0.1U

F

0.1U

F

C6

0.1U

F

C9

10U

F6.

3V

C4

C5

6.3V

10U

F

C16

0.1U

F0.

1UF

0.1U

F0.

1UF

C15

C1

6.3V

10U

F

L2

EXC

-CL4

532U

1

64 3 2 1

5 7 8

U4

23

1JP

26

875

12346

U6

64 3 2 1

5 7 8

U7

C14

1UF

1UF

C17

C20

1UF

1UF

C31

C37

1UF

1UF

C21C

18

1UF1U

F

C12

C38

100P

F

100P

FC

30C19

100P

F

100P

FC

13

R36

76.8

K

76.8

KR

31R23

76.8

K

76.8

KR

2

R30

64.9

K

64.9

KR

12R8

64.9

K

R10

78.7

K

78.7

KR

5

10U

F6.

3V

C57

C61

C60

21

3JP

10

31

2

JP54 2

13

JP15

31

2

JP78

76.8

KR

2510

0PF

C89

1UF

C88

C86

1UF

875

12346

U11

1

2

J11

5VG

ND

;3,4

,5

07265-184

SMA

EDG

E

5V

5VIN

T

5VIN

JP3

5VU

SB1

2J3

5VG

ND

;3,4

,5JP

28

LC18

12

Figure 112. Power Supplies and Filters


Rev. B | of 80

RN

ETC

TS74

3-8

RC

0402

RN

ETC

TS74

3-8

2

22 22

RNETCTS743-8

RNETCTS743-8

of U

1.S5

to P

in 1

8

No

stub

Mat

ch le

ngth

to p

ath

from

101112131415 2

345678

116

9

DNPRP1

1011121314152

345678

1 16

9

DNPRP5

DB

13D

B12

DB

11

DB

9D

B8

DB

7

DB

0XD

B1X

DB

2XD

B3X

DB

4XD

B5X

DB

6XD

B6

1011121314152 3 4 5 6 7 81

16 9

RP3

1

R6

0M

SB

TP22

TP10

BLK

WH

T

DB

13X

DB

7XD

B8X

DB

9XD

B10

XD

B11

XD

B12

X

DB

10

DB

5D

B4

DB

3D

B2

DB

1D

B0

9161 8765432

15 14 13 12 11 10

RP4

07265-185

SSW

-120

-02-

SM-D

-R-A

HEADERRIGHTANGLEFEMALE

PCB

Bot

tom

Sid

e

1 3 75 9 1 1 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

J11

DIG

I TA

L IN

PUTS

DB

13X

DB

12X

DB

11X

DB

10X

DB

9XD

B8X

DB

7XD

B6X

DB

5XD

B4X

DB

3XD

B2X

DB

1XD

B0X

1 IN

J1

AN

D R

P3, T

HE

MSB

IS D

B13

, DB

11, D

B9,

OR

DB

7, D

EPEN

DIN

G O

N T

HE

PAR

T.

Figure 113. Digital Inputs


Rev. B | of 80

07265-186

RC

0402

RC

0402

RC

0402

RC

0402

C

C

C

CC

RC

0402

RC

0402

RC

0402

CC

0603

CC

0603

RC0603

RC0402

SN74

LVC

1G34

DC

K

CC

0603

CC

0603

CC

0603

CC

0603

CC

0603

CC

0402

CC

0402

CC

0603

AC

ASE

RC0402

CC

0402

CC

0402

C

RC

0402

GN

DO

UT

ENO

VCC

40-L

EAD

LFC

SPA

D97

17

DB

10D

B9

DB

8D

VDD

IOD

VSS

DVD

DD

B7

DB

6D

B5

DB

4D

B3

DB

2D

B1

DB

0 (L

SB)

DC

LKIO

CVD

DC

LKIN

CVS

SC

MLQ

DB

12D

B13

(MSB

)C

S/PW

RD

N

SCLK

/CLK

MD

RES

ET/P

INM

DR

EFIO

FSA

DJI

/AU

XIFS

AD

JQ/A

UXQ

CM

LIR

LIN

IOU

TNIO

UTP

RLI

PA

VDD

AVS

SR

LQP

QO

UTP

RLQ

N

DB

11

QO

UTN

SDIO

/FO

RM

AT

RC

0402

CC0402 CC0402

RC0402

RC0402

RC0402

RC0402

RC04

02

RC04

02

RC0402

C

= S

HA

RE

CO

MPO

NEN

T PA

D.

Kee

p pa

ralle

lWH

TTP

25

IOTC

QO

TC

DN

P

R

80

CVD

DC

LKIN

DC

LKIO

R17

DN

P

DVD

DX

49.9

R18

10K

R71

TP26

WH

TC

3400

.1U

F

WH

TTP

30

CVD

DX

AVD

D

REF

IO

R65

DC

LKIO

CLK

IN

R33

134

2SW

1

DG

ND

;5

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 36 35 34 33 32 31 30 29 28 27 26 25 24 23 21

1

2237

U1

AG

ND

;41

1 234

U12

OSC

-S17

03

R11

0D

NP

DN

PR

69

DG

ND

;3,4

,5

S11

OU

T2R

00

0

0O

UT0

R

00.1

UF

C77

C7800

.01U

F

R10

7D

NP

10K

R10

8

1NF

C56

C55

00.1

UF

TP3

WH

T1U

F

C39

JP11

JP32

JP33

JP34

JP35

4.7U

F6.

3V

C59

0.1U

FC

11

0.01

UF

32C

82C 0.

01U

F

24

U8

DVD

DX;

5D

GN

D;3

R70

10K

DN

PR

68C

GN

D;3

,4,5

S5

R34

0DN

P

DVD

D

AVD

D C24

0.1U

F

CVD

D

R7

10K

0.01

UF

C25

0.1U

F

C260.1U

F

C27

R64

DN

PR

66

R67

0

R

72

00.1

UF

C10

1

MO

DE-

SDIO

DB

11

FSA

DJ2

FSA

DJ1RM

OD

E-SC

LK

SLEE

P-C

SBD

B13

DB

12

DB

0 (L

SB)

DB

1D

B2

DB

3D

B4

DB

5D

B6

DB

7

DVD

DIO

DB

8D

B9

DB

10

IOU

TBIO

UTA

QO

UTA

QO

UTB

DVD

D

R12

2

DVD

DX

R19

R20

0

DN

P

R21

0

DN

PR

26

IOTC

QO

TC

IOT_

CM

L

QO

T_C

ML

RC

0402

C

RC

0402

RC

0402

R47

0

0R

46

0R

48

THE

AD

9714

/AD

9715

/AD

9716

CA

N B

E U

SED

IN U

1.

Figure 114. Clock Input and DUT


Rev. B | of 80

07265-187

RC0603

RC

0603

RC

0603

CC0402

AC

ASE

DN

P

RC0805

RC0805

RC0805

RC0603

RC0603

RC0603

RC0603

AD

TL1-

12

PS

AD

T9-1

T

SP

RC0603

RC0603

AC

ASE

CC0603

CC0805

CC0603

CC

0603

CC

0603

CC

0603

RC

0402

RC

0402

RC

0402

RC

0402

RC

0402

+IN+V

-IND

ISFB

-V2

-V1

OU

T

RC

0603

RC

0603

RC0603

RC

0603

RC0603

RC

0603

RC

0603

RC0603

RC0603

RC0603

FSA

DJ

resi

stor

s m

ust h

ave

low

TC

IOU

T N

ETW

OR

K A

ND

FSA

DJ1

WH

TTP

31

R14

DN

P

WH

EN R

13 A

ND

R14

AR

E N

OT

DN

P, 4

99 IS

REC

OM

MEN

DED

WH

EN C

95 IS

NO

TD

NP,

10p

F TO

1nF

IS R

ECO

MM

END

ED

R13 DN

P

IOU

TA

IOU

TB

JP90

FSA

DJ1

0R

79

R12

30-

DN

PD

NP

R37

S3

R9

DN

P

R11

0A

GN

D;3

,4,5

AG

ND

;3,4

,5

AG

ND

;3,4

,5

AG

ND

;3,4

,5

R94

0

10-D

NP

R11

1

0

R93

S4

17 4

532

6

8

AD

A48

99-1

AG

ND

;9D

NP

C10

51U

F

CER

AM

IC

R11

60 49

9R

115

0R

117

REF

IO

OPA

MPI

N

C10

7

0.1U

F

C10

60.

1UF

0.1U

FC

108

P5V

P5V N5V

C10

3

10V

10U

F

OR

GTP

40TP

39R

ED

TP41

BLK

0.1U

FC

22

OPA

MPI

N

R57

453

25

316 4

T8

134 6

T2

WH

TTP

34

R99

100K

D1N

D1P

C95

DN

P

TP1

WH

T

DN

PR

98

R97

DN

P

JP7

0.1%

32K

R1

DN

PTP

33

R22

DN

P R51 8K 0.

1%

R49 16

K0.

1%

JP9

JP8

S9

DN

P

TP32

DN

P

JP12

10U

F10

V

C10

4

N5V

R11

349

9

C10

20.

2NF

15R

114

R11

8DN

P

DN

P

R11

9

JP55

JP56

100K

R35

TP44

WH

T

1

2S1

2

0-D

NP

R15

IOT_

CM

L

ERA6YEB323V, ERA6Y

ERA6YEB323V, ERA6Y

ERA6YEB323V, ERA6Y

U13

Figure 115. IOUT Network and FSADJ1


Rev. B | of 80

07265-188

RC0603

RC

0603

RC

0603

RC

0603

RC0603

CC

0603

AD

T9-1

T

SP

AD

TL1-

12

P

S

RC0805

RC0805

ERA6YEB323V, ERA6Y

ERA6YEB323V, ERA6Y

ERA6YEB323V, ERA6Y

RC0603

RC0603

RC0603

RC0805

RC0603

RC0603

RC

0603

RC

0603

RC

0603

RC0603

RC0603

RC

0603

RC0603

RC0603

RC0603

RC0603

CC

0603

FSA

DJ

resi

stor

s m

ust h

ave

low

TC

QO

UT

NET

WO

RK

AN

D F

SAD

J2

R54

DN

P

TP17

WH

TFS

AD

J2JP

91

JP82

WH

TTP

38

R53

DN

PR

52 DN

P

QO

UTA

QO

UTB

D2N

DN

PR

56R42

DN

P

0R

83

0 R12

4

0

S8

R38

0

R10

600

R10

5

OPA

MPI

N

DN

PR

112

R50

453

R59 16

K0.

1%

R60 8K 0.

1%

D2P

TP37

DN

P

DN

PR

101

0.1U

FC

48

S6

JP21

JP20

JP16

0.1%

32K

R58

16

34

T1

S10

DN

P1

2A

GN

D;3

,4,5

AG

ND

;3,4

,5

AG

ND

;3,4

,5

1234 5 6

T5

WH

TTP

35

R10

210

0K

C96

WH

EN C

96 IS

NO

T D

NP,

10pF

TO

1nF

IS R

ECO

MM

END

ED

DN

PR

100

DN

P

JP77

DN

PTP

36

R12

0D

NP

DN

PR

121

JP76

100k

R55

TP45

WH

T

R16

QO

T_C

ML

WH

EN R

52 A

ND

R53

AR

E N

OT

DN

P, 4

99 IS

REC

OM

MEN

DED

WH

EN R

112

IS N

OT

DN

P,10

IS R

ECO

MM

END

ED

Figure 116. QOUT Network and FSADJ2


Rev. B | of 80

07265-189

5V

5V

5V

5V

5V

RC

040

2

RC

0402

CC

0603

CC

0603

RC

040

2

RC

1206

CC

060

3C

C0

603

CC

060

3C

C0

603

MLX-0532610571

CC

060

3

CC

0603

CC

0603

GRN

CC

060

3

RC

0402

RC

0402

CC

0603

CC

060

3

RC

040

2

RC

040

2

2

VB

US

D-

D+

ID-X

GN

D-4

AV

DD

1

AV

DD

2

AV

SS

MC

LR

-VP

P-R

E3

OS

C1-

CL

K1

N31

C

OS

C2-

CL

KO

-RA

6

RA

0-A

N0

RA

1-A

N1

RA

2-A

N2-

VR

EF

-

RA

3-A

N3-

VR

EF

+R

A5-

AN

4-H

LV

DIN

RA

4-T

0CK

I-R

CV

RB

0-A

N12

-IN

T0

RB

1-A

N10

-IN

T1

RB

2-A

N8-

INT

2-V

MO

RB

3-A

N9-

VP

O

RB

4-A

N11

-KB

I0

RB

5-K

BI1

-PG

M

RB

6-K

BI2

-PG

C

RB

7-K

BI3

-PG

D

RC

0-T

IOS

O-T

1CK

I

RC

1-T

1OS

I-U

OE

RC

2-C

CP

1

RC

4-D

--V

M

RC

5-D

+-V

P

RC

6-T

X-C

KR

C7-

RX

-DT

RD

0

RD

1

RD

2

RD

3

RD

4

RD

5

RD

6

RD

7

RE

0-A

N5

RE

1-A

N6

RE

2-A

N7

VD

D1

VD

D2

VS

S1

VS

S2

VU

SB

PIC

18

F4

45

0

A1

A2

A3

A4

EN

GN

D

NC

A

VC

CA

VC

CY Y1

Y2

Y3

Y4

AD

G33

04

A1

A2

A3

A4

EN

GN

D

NC

A

VC

CA

NC

Y

VC

CY

Y1

Y2

Y3

Y4

AD

G33

04

pcb

bo

tto

m s

ide

pcb

Top

sid

e

2 3 4 5

871

14 13 12 11 10

69

U5

10111213141

9 8

6 75432

U14

7

2830

18

3213

33

19 20 21

2322

24

9

10 11 12 14 15 16 17

3435364243441

38394041

2 3 4 5

252627

8

29

6

3137

U3

5VG

ND

;45

R28

S1

S3

12345

P1

R43

0M

OS

IM

ISO

22

R10

3

MO

SI

MIS

O

CS

B

EN

2

L15

EX

C-C

L32

25U

1

WH

TT

P20

WH

TT

P18

TP

2D

NP

R

4422

SC

LK

3

Y1

20.0

00M

HZ

5VG

ND

;2

5VU

SB

5VU

SB

0.1U

F

C11

4

C10

0

0.1U

F

0R

82 R62

0 MO

DE

-SD

IO

R87

0

DV

DD

SS

EL

2

10P

F-1

%

C49

R63

499

2 1D

1

LN

J312

G8T

RA

R27

1M

5VU

SB

0.1U

F

C10

9

5VU

SB

C32

6.3V

10U

F

C33

10P

F-1

%

470N

F

C11

0

2 3 4 51

MP

1

MP

2

P3

MO

SI

EN

1

EN

2

SC

K

SS

EL

1

5VU

SB

C84

0.1U

F0.

1UF

C97

C98

0.1U

F0.

1UF

C99

MIS

O

MO

SI

SC

K

SS

EL

1S

SE

L2

SC

K

MIS

O

C11

2

0.1U

F0.

1UF

C11

1

5VU

SB

R39

2222

R40

R41

2222R

MO

DE

-SC

LK

22

R45

RA

0

MO

DE

-SD

O

5VU

SB

BL

KT

P7

TP

19W

HT

DV

DD

X

EN

1

SL

EE

P-C

SB

SD

IO

CC

0603

RC

0403

Figure 117. SPI Port


Rev. B | of 80

CC

0402

CC

0402

AC

ASE

CC

0402

CC

0402

ETC1-1-13

S P

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

AC

ASE

AC

ASE

AC

ASE

CC

0402

RC0603

RC

0603

RC

0603

SMA

EDG

EA

GN

D;3

,4,5

SMA

EDG

EA

GN

D;3

,4,5

CC

0805

CC

0805

CC

0805

CC

0805

LC10

08

AD

TL1-

12

NC

=2,5

PS

PS

NC

=2,5

RC

0603

VPS1

BVP

S1C

VPS1

DC

OM

2ALO

IPLO

INC

OM

2BC

OM

3AC

OM

3BVO

UT

VPS2

AVP

S2B

VPS3

VPS4

VPS5

IBB

PIB

BN

CO

M4A

QB

BN

QB

BP

VPS1

A

CO

M1A

CO

M1B

CO

M4B

AD

TL1-

12RC

0603

RC0603

CC

0402

CC

0402

VDD

M

100P

F

C87

C53100PF

100PFC54

R73

R746 4

31T6

0 0 0 0

MO

D_I

N

MO

D_I

P

4 5 6 7 8 9 10 1131

1214151617181920212324

31 222

U9

AD

L537

0

AG

ND

;25

DN

P

R78

R75

1 346

T3

L17

DN

P

LC10

08

RED

TP42

BLK

TP21

TP16

RED

VDD

M

DN

PL1

4

VDD

M_I

N

C91

DN

P

C79

7.5P

F

CC

0805 C

804.

7PF

CC

0805 C

81

4.7P

F

C92

DN

P

C82

LC10

08

L10

LC10

08

1.8U

H

1.8U

H

L11

7.5P

F

1

2

J71

2

J6

1k 1k

R24 R610.

1UF

C90

C83

100P

F

C63

100P

F0.

1UF

C72

10V

10U

F

C41

C44 10

UF

10V

C52 0.

1UF

0.1U

FC

47C

5010

0PF

10V

10U

FC

43

123 4

5

T4

C73 100PF

100P

F

C51

0.1U

F

C36

22U

F16

V

C35

EXC

-CL4

532U

1

L13 LC

1812

C29

0.1U

F

TP43

BLK

MO

D_Q

PM

OD

_QN

MO

D_I

NM

OD

_IP

VDD

M

MO

DU

LATE

D O

UTP

UT

VDD

M

VDD

M

D1P

D1N

CC

0805

CC

0805

CC

0805

CC

0805

LC10

08

L20

DN

P

LC10

08

DN

PL1

8

C93

DN

P

C64

7.5P

F

CC

0805 C

654.

7PF

CC

0805 C

74

4.7P

F

C94

DN

P

C75

LC10

08

L8

LC10

08

1.8U

H

1.8U

H

L9

7.5P

F

D2P

D2N

MO

D_Q

P

MO

D_Q

N

07265-190

Figure 118. Modulated Output


Rev. B | of 80

CC

0402

CC

0402

CC

0402

CC

0402

C11

3

0.1U

F0.

1UF

C85

C58

0.1U

F0.

1UF

C40

CC

C

C

C

C

C C

C

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

CC

0402

JTX-

4-10

T+SP

HSMS-281C

RC0805

CC0402CC0402

RC

0402

RC

0402

RC

0402

RC

0402

RC

0402

RC

0402

RC

0402

CC

0402

1:4

C42

0.1U

F

1NF

C62

OU

T0R

R88

0

R89

0

DN

P R

90

CVD

DX

4.12

KR

81

R76

1.8K

134

2SW

2 CG

ND

;5

CVD

DX

1.8K

R77

0.1U

FC

46

C45

0.1U

F

R91

49.9

12

3

D3

2 3156 4

T9

0.1U

F

C66

C670.1U

F0.

1UF

C68

C76

0.1U

F0.

1UF

C71

C70

0.1U

F0.

1UF

C69

OU

T2R

R10

9D

NP

J10

07265-191

RC

0402

0R

86R

A0

CC

AD

9512

BC

PZ

DSY

NC

BVS

1VS

2N

C1

VS3

CLK

2C

LK2B

VS4

CLK

1C

LK1B

FUN

CST

ATU

SSC

LKSD

IOSD

OC

SBVS

5G

ND

1O

UT2

BO

UT2

VS6

VS7

VS18

VS17

GN

D6

RSE

TVS

16G

ND

5O

UT0

OU

T0B

VS15

VS14

GN

D4

GN

D3

VS13

OU

T3O

UT3

BVS

12VS

11O

UT4

OU

T4B

VS10

VS9

OU

T1O

UT1

BVS

8G

ND

2

DSY

NC

MO

DE-

SDIO

MO

DE-

SDO

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 52421

U10

CG

ND

;49

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

RM

OD

E-SC

LK

SLEE

P-C

SBC

VDD

X

CVD

DX

CVD

DX

CLO

CK

DR

IVER

CH

IP

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CVD

DX

CG

ND

;3,4

,5

WH

EN R

90 A

ND

R10

9A

RE

NO

T D

NP,

49.

9IS

REC

OM

MEN

DED

Figure 119. Clock Driver Chip


Rev. B | of 80

SILKSCREENS

0726

5-20

3

Figure 120. Layer 2, Ground Plane


Rev. B | of 80

0726

5-20

4

Figure 121. Layer 3, Power Plane


Rev. B | of 80

0726

5-2

05

Figure 122. Assembly—Primary Side


Rev. B | of 80

072

65-2

06

Figure 123. Assembly—Secondary Side


Rev. B | of 80

0726

5-21

7

Figure 124. Solder Mask—Primary Side with Socket


Rev. B | of 80

0726

5-20

7

Figure 125. Solder Mask—Secondary Side


Rev. B | of 80

0726

5-20

8

Figure 126. Hard Gold Plated with Bumps and Socket


Rev. B | of 80

072

65-2

09

Figure 127. Primary Side Paste


Rev. B | of 80

0726

5-21

0

Figure 128. Secondary Side Paste


Rev. B | of 80

0726

5-21

1

Figure 129. Silkscreen—Primary Side


Rev. B | of 80

072

65-2

12

Figure 130. Silkscreen—Secondary Side


Rev. B | of 80

0726

5-2

13

Figure 131. Layer 1—Primary Side


Rev. B | of 80

0726

5-2

14

Figure 132. Layer 4—Secondary Side


Rev. B | of 80

0726

5-2

15

Figure 133. Immersion Gold, No Socket, No Bumps


Rev. B | of 80

0726

5-21

6

Figure 134. Solder Mask—Primary Side, No Socket


Rev. B | of 80

BILL OF MATERIALS Table 18.

Qty Reference Designator Device Package Description Part No./ Manufacturer

6 C1, C2, C4, C5, C32, C57 CAPSMDA ACASE 10 µF, 6.3 V capacitor 17 C3, C6, C7, C8, C9, C10, C11,

C15, C16, C22, C24, C26, C27, C48, C60, C61, C107

CC0603 CC0603 0.1 µF capacitor

11 C12, C14, C17, C18, C20, C21, C31, C37, C39, C86, C88

CC0603 CC0603 1 µF capacitor

5 C13, C19, C30, C38, C89 CC0603 CC0603 100 pF capacitor 3 C23, C25, C28 CC0603 CC0603 0.01 µF capacitor 6 C29, C36, C47, C52, C72, C90 CC0402 CC0402 0.1 µF capacitor 2 C33, C49 CC0603 CC0603 10 pF, 1% capacitor 18 C34, C40, C42, C45, C46,

C55, C58, C66, C67, C68, C69, C70, C71, C76, C77, C85, C101, C113


1 C35 CAPSMDA ACASE 22 µF,16 V capacitor 3 C41, C43, C44 CAPSMDB ACASE 10 µF, 10 V capacitor 8 C50, C51, C53, C54, C63,

C73, C83, C87 CC0402 CC0402 100 pF capacitor

2 C56, C62 CC0402 CC0402 1 nF capacitor 1 C59 CAPSMDA ACASE 4.7 µF, 6.3 V capacitor 4 C64, C75, C79, C82 CC0805 CC0805 7.5 pF, 1% capacitor 4 C65, C74, C80, C81 CC0805 CC0805 4.7 pF, 1% capacitor 1 C78 CC0402 CC0402 0.01 µF capacitor 11 C84, C97, C98, C99, C100,

C106, C108, C109, C111, C112, C114


4 C91, C92, C93, C94 CC0805 CC0805 DNP 2 C95, C96 CC0603 CC0603 DNP 1 C102 CC0402 CC0402 0.2 nF capacitor 2 C103, C104 CAPSMDA ACASE 10 µF, 10 V capacitor 1 C105 CC0805 CC0805 1 µF ceramic capacitor 1 C110 CC0603 CC0603 470 nF capacitor 1 D1 Panasonic LNJ312G8TRA 1.6 mm x 0.8 mm LED-SMD-TSS-GRN LNJ312G8TRA 1 D3 HSMS-281C SOT323-3 HSMS-281C HSMS-281C 1 J1 Samtec

SSW-120-02-SM-D-RA 40-pin through hole

40-pin right angle header female

SSW-120-02-SM-D-RA/ Samtec

6 J2, J3, J4, J5, J8, J11 SMAEDGE SMAEDGE DNP SMA connector edge right angle

2 J6, J7 SMAEDGE SMAEDGE SMA connector edge right angle

5 J10, S3, S5, S6, S11 SMAUPA04 SMA200UP SMA connector RF 5-pin upright

5 S4, S8, S9, S10, S12 SMAUPA04 SMA200UP DNP 11 JP3, JP7, JP8, JP9, JP11, JP12,

JP16, JP20, JP21, JP28, JP77 JPRBLK02 JPRBLK02 2-pin jumper header

10 JP6, JP10, JP15, JP22, JP26, JP29, JP54, JP78, JP88, JP89

JPRBLK03 JPRBLK03 3-pin jumper header

10 JP32, JP33, JP34, JP35, JP55, JP56, JP76, JP82, JP90, JP91

JPRSLD02 JPRSLD02 Solder jumper


Rev. B | of 80


11 L1, L2, L3, L4, L5, L6, L7, L12, L13, L16, L19

IND1812 LC1812 EXC-CL4532U1 EXC-CL4532U1

4 L8, L9, L10, L11 IND1008 LC1008 1.8 µH, 10% 4 L14, L17, L18, L20 IND1008 LC1008 DNP 1 L15 IND1210 LC1210 EXC-CL3225U1 EXC-CL3225U1 1 P1 USB-MINIB USB-MINIB USB mini 5-pin 1 P3 Molex 0532610571 Molex 0532610571 1.25 mm, 5-pin wire-

to-board connector 0532610571/ Molex

2 R1, R58 RC0805 RC0805 32 kΩ, 0.1% resistor ERA6YEB323V, ERA6Y

5 R2, R23, R25, R31, R36 RC0603 RC0603 76.8 kΩ resistor 5 R3, R4, R5, R10, R29 RC0603 RC0603 78.7 kΩ resistor 6 R6, R33, R34, R64, R65, R67 RC0402 RC0402 0 Ω resistor 7 R17, R66, R68, R69, R107,

R110, R122 RC0402 RC0402 DNP

1 R7 RC0603 RC0603 10 kΩ resistor 5 R8, R12, R30, R32, R92 RC0603 RC0603 64.9 kΩ resistor 8 R9, R37, R42, R56, R97, R98,

R100, R101 RC0603 RC0603 DNP

4 R11, R38, R79, R83 RC0603 RC0603 0 Ω resistor 4 R13, R14, R52, R53 RC0603 RC0603 DNP 10 R15, R16, R123, R124,

R73 to R75, R78, R93, R94, R105, R106

RC0603 RC0603 0 Ω resistor

6 R22, R54, R118, R119, R120, R121

RC0603 RC0603 DNP

1 R18 RC0402 RC0402 49.9 Ω resistor 2 R19, R21 RC0402 RC0402 0 Ω resistor 3 R20 , R26, R80 RC0402 RC0402 DNP 2 R24, R61 RC0603 RC0603 1 kΩ resistor 1 R27 RC0603 RC0603 1 MΩ resistor 7 R28, R39, R40, R41, R44,

R45, R103 RC0402 RC0402 22 Ω resistor

4 R35, R55, R99, R102 RC0603 RC0603 100 kΩ resistor 1 R43 RC0402 RC0402 0 Ω resistor 8 R46, R47, R48, R62, R82,

R86, R116, R117 RC0402 RC0402 0 Ω resistor

2 R49, R59 RC0805 RC0805 16 kΩ, 0.1% resistor ERA6YEB323V, ERA6Y

2 R50, R57 RC0603 RC0603 453 Ω resistor 2 R51, R60 RC0805 RC0805 8 kΩ, 0.1% resistor ERA6YEB323V,

ERA6Y 3 R63, R113, R115 RC0402 RC0402 499 Ω resistor 3 R70, R71, R108 RC0402 RC0402 10 kΩ resistor 1 R72 RC0402 RC0402 25 Ω resistor 2 R76, R77 RC0402 RC0402 1.8 kΩ resistor 1 R81 RC0402 RC0402 4.12 kΩ resistor 1 R87 RC1206 RC1206 0 Ω resistor 2 R88, R89 RC0402 RC0402 0 Ω resistor 2 R90, R109 RC0402 RC0402 DNP 1 R91 RC0805 RC0805 49.9 Ω resistor 2 R111, R112 RC0603 RC0603 DNP 1 R114 RC0402 RC0402 15 Ω resistor 2 RP1, RP5 RNETCTS743-8 RNETCTS743-8 DNP


Rev. B | of 80


2 RP3, RP4 RNETCTS743-8 RNETCTS743-8 22 Ω resistor 2 SW1, SW2 KEYBDSWG OMRONB3SG B3S-1100 push-button 4 T1, T2, T3, T6 ADTL1-12 MINI_CD542 DNP 1 T4 ETC1-1-13 SM-22 M/A COM ETC1-1-13 ETC1-1-13/

M/A-COM 2 T5, T8 ADT9-1T MINI_CD542 ADT9-1T ADT9-1T/

Mini-Circuits 1 T9 JTX-4-10T MINI_BH292 JTX-4-10T+ JTX-4-10T/

Mini-Circuits 16 TP1, TP3, TP17, TP18,

TP19, TP20, TP22, TP25, TP26, TP30, TP31, TP34, TP35, TP38, TP44, TP45

LOOPMINI LOOPMINI White test point

4 TP32, TP33, TP36, TP37 LOOPMINI LOOPMINI DNP 8 TP5, TP8, TP12, TP13,

TP16, TP24, TP39, TP42 LOOPMINI LOOPMINI Red test point

1 TP2 LOOPMINI LOOPMINI DNP 12 TP4, TP6, TP7, TP9, TP10,

TP11, TP14, TP15, TP21, TP23, TP41, TP43

LOOPMINI LOOPMINI Black test point

1 TP40 LOOPMINI LOOPMINI Orange test point 1 U1 40-lead LFCSP, AD9717 LFCSP040-CP1 40-lead LFCSP,

AD9717 AD9717/ Analog Devices

5 U2, U4, U6, U7, U11 ADP3334 8-lead SOIC ADP3334 voltage regulator

ADP3334/ Analog Devices

1 U3 USB-PIC18F4550-I/ML-ND QFN044P65MM-EP1 PIC18F4550, microchip USB port chip QFN44 8X8MM

PIC18F4550

2 U5, U14 ADG3304BRUZ 14-lead TSSOP ADG3304, 14-lead TSSOP

ADG3304BRUZ/ Analog Devices

1 U8 74LVC1G34 SC70-05 SN74LVC1G34DCK, TI buffer

TI-DCK = SC70_05 PKG

1 U9 ADL5370 LFCSP024P5MM-EP1 ADL5370ACPZ ADL5370ACPZ/ Analog Devices

1 U10 AD9512 LFCSP048-CP1 AD9512BCPZ AD9512BCPZ/ Analog Devices

1 U12 OSC-S1703 OSC-S1703 DNP 1 U13 8-lead SOIC, ADA4899-1 SOIC8-N-EP Op amp, ADA4899-1 ADA4899-1/

Analog Devices 1 Y1 ABM3B-20.000MHZ-10-1-U-T SMD 3.2 mm × 5.0 mm 20 MHz 300-8214-1-ND/

Digi-Key


Rev. B | of 80

OUTLINE DIMENSIONS

140

1011

3130

2120

4.254.10 SQ3.95

TOPVIEW

6.00BSC SQ

PIN 1INDICATOR

5.75BSC SQ

12° MAX

0.300.230.18

0.20 REFSEATINGPLANE

1.000.850.80

0.05 MAX0.02 NOM

COPLANARITY0.08

0.80 MAX0.65 TYP

4.50REF

0.500.400.30

0.50BSC

PIN 1INDICATOR

0.60 MAX0.60 MAX

0.25 MIN

EXPOSEDPAD

(BOT TOM VIEW)

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 0721

08-A

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

Figure 135. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm and 0.85 mm Package Height (CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9714BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9714BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9715BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9715BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9716BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9716BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9717BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9717BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9714-DPG2-EBZ Evaluation Board AD9715-DPG2-EBZ Evaluation Board AD9716-DPG2-EBZ Evaluation Board AD9717-DPG2-EBZ Evaluation Board 1 Z = RoHS Compliant Part.

dual, low power, 8-/10-/12-/14-bit txdacdigital-to-analog ... · ad9717 nsd @ 1 mhz output, 125...

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