ECE 448 – FPGA and ASIC Design with VHDL George Mason University

ECE 448Lab 1

Implementing Combinational Logic in VHDL

Part 1: General Lab Rules

Part 2: Introduction to Experiment 1: ALU of MIPS

Part 3: Hands-on Session: Simulation and Synthesis in the Aldec Active HDL Environment

Agenda for today

Part 1

General Lab Rules

See the Rules posted at the Course Web Page.

Follow this link.

Part 2

Introduction to Experiment 1ALU of MIPS

Overview of MIPS datapath

Source: Source: http://cseweb.ucsd.edu/~carter/141/c09oneCycle.pdf

MIPS overview

32 bit addresses 32 registers/5 bit register addresses 3 basic types of instructions

Register (R) -type Immediate (I)-type Jump (J)-type

R-type Instruction Format

• opcode: 6 bit field identifying the instruction. For all R-type instructions field is “000000”.

• Rs: 5 bit field identifying the first source register for the operation.

• Rt: 5 bit field identifying the second source register.• Rd: 5 bit field identifying the destination register for

the operation.• shamt: the shift amount for any shift operation.• func: A more specific function operation code, i.e.,

add, subtract.

opcode Rs Rt Rd shamt func

I-type Instruction Format

• opcode: 6 bit field identifying the instruction. • Rs: 5 bit field identifying the source register for the

operation.• Rt: 5 bit field identifying the destination register.• Imm: 16 bit immediate value for this operation.

opcode Rs Rt Imm

J-type Instruction Format

opcode: 6 bit field identifying the instruction; either 0x02 (JUMP) or 0x03 (Jump And Link, JAL) address: 26 bit address to jump to

opcode address

Instructions to ImplementRequired

R-type ADD AND OR SUB XOR SLT (Set Less Than) SLTU (Set Less Than Unsigned)

I-Type ADDI ANDI ORI

Instructions to ImplementExtra Credit

R-type SLL (Shift Left Logical) SRL (Shift Right Logical) SLLV (Shift Left Logical Variable) SRLV (Shift Right Logical Variable)

Block Diagram

BehavioralBehavioral

Required TasksExample of a Similar Problem

Mini ALU

opcode

A

B

M

RMini ALU

4

4

4

4

4

Mnemonic Operation Opcode

ADDAB R= A + B 0000

ADDAM R = A + M 0001

SUBAB R = A - B 0010

SUBAM R = A - M 0011

NOTA R = NOT A 0100

NOTB R = NOT B 0101

NOTM R = NOT M 0110

ANDAB R = A AND B 0111

ANDAM R = A AND M 1000

ORAB R = A OR B 1001

ORAM R = A OR M 1010

XORAB R = A XOR B 1011

XORAM R = A XOR M 1100

Block diagram

Unsigned and Signed Arithmeticin VHDL

19ECE 448 – FPGA and ASIC Design with VHDL

Operations on Unsigned NumbersFor operations on unsigned numbers

USE ieee.numeric_std.alland signals of the typeUNSIGNEDand conversion functions: std_logic_vector(), unsigned()

OR

USE ieee.std_logic_unsigned.alland signals of the typeSTD_LOGIC_VECTOR

(recommended)

(permitted)

20ECE 448 – FPGA and ASIC Design with VHDL

Operations on Signed Numbers

For operations on signed numbers

USE ieee.numeric_std.all,signals of the type SIGNED,and conversion functions: std_logic_vector(), signed()

OR

USE ieee.std_logic_signed.alland signals of the type STD_LOGIC_VECTOR

(recommended)

(permitted)

21ECE 448 – FPGA and ASIC Design with VHDL

Signed and Unsigned Types

Behave exactly like STD_LOGIC_VECTORplus, they determine whether a given vectorshould be treated as a signed or unsigned number.Require USE ieee.numeric_std.all;

22ECE 448 – FPGA and ASIC Design with VHDL

Multiplication of unsigned numbers

LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all ;

entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) );

end multiply;

architecture dataflow of multiply is

c <= a * b;

end dataflow;

23ECE 448 – FPGA and ASIC Design with VHDL

Multiplication of signed numbers

LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all ;

entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) );

end multiply;

architecture dataflow of multiply is

c <= a * b;

end dataflow;

24ECE 448 – FPGA and ASIC Design with VHDL

Multiplication of signed and unsigned numbers

LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ;

entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(15 downto 0); cs : out STD_LOGIC_VECTOR(15 downto 0) );

end multiply;

architecture dataflow of multiply isbegin

-- signed multiplicationcs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b));

-- unsigned multiplicationcu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b))

end dataflow;

Extra CreditExample of a Similar Problem

Variable Rotator

Function

C = A <<< B

A – 4-bit data inputB – 2-bit rotation amount

Interface

4

4

2

A

B

C

Block diagram

C

Fixed Rotation in VHDL

A(3) A(2) A(1) A(0)

A(2) A(1) A(0) A(3)

A<<<1

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);

ArotL <= A(2 downto 0) & A(3);

ArotL

A

Part 3

Hands-on SessionSimulation and Synthesis

in the Aldec Active HDL Environment

Example for the Hands-on SessionMLU Block Diagram

B

A

NEG_A

NEG_B

IN0

IN1

IN2

IN3

OUTPUT

SEL1SEL0

MUX_4_1

L0L1

NEG_Y

Y

Y1

A1

B1

MUX_0

MUX_1MUX_2

MUX_3

0

1

0

1

0

1