1

ECE 7366 Advanced Process Integration

The CMOS Traasistors

Dr. Wanda Wosik

Text Book: B. El-Karek, “Silicon Devices and Process Integration”, Chapter 5

2

FET Structures

3

4

Non-Ideal MOS Structure

Work function difference vs doping for Al gates and degenerate poly-silicon p+ and n+ type.

Note the symmetry of fms for poly-Si and asymmetry for Al gates

Band bending due to work function differences. No charge in the oxide assumed

5

Polysilicon Workfunction

Intrinsic Si

The role of Ge in regulating work function of polysilicon: p+ polySi by 0.4eV (strain for higher Ge x>0.45). Less doping (VG )– higher mobility

6

Scaled down NMOS device with poly-Si gate Poly-Si depletion Inversion capacitance decreases

Charging at the metal dielectric interfaceDipol EF,m aligns more with ECNL,d it is increasingly more (S to 0 for perfect pinning) with increasing e of dielectric Effective work function Fm changes from the metal vaccuum level

Yeo,IEEE, 2002

7

Selection of Metal Gates and High-K Dielectric

Y-C Yeo et al.

Use dual work function metal gates Stability of work function on dielectric: Silicon Nitrides of Ti, TaWatch for resistivity.

required

obtained

8

Metal F-level pinned to ECNL of the dielectric.

Effect of Fermi level pinning is smaller for poly-si gates – less changes of effective work function

Yeo, IEEE 2002

9

Metal Gates

Midgap work function: W, TiN, W/TiN ~4.8 eV

Disadvantage in small devices: high concentrations in the channel ~1018cm-3

(fb~0.5eV ) VT~0.5V but VT required ~ 0.2-0.25V (VG-VT). To lower VT use implant (buried channel devices)– bad for mobility & SCE so midgap gates are not good for scaled down devices.

Dual work function: c+0.2V (NMOS) ~ 4.35eV and c+Eg/q-0.2V (PMOS) 5.07 eV

~4.7 eV

Y-C Yeo et al.

Yang et al.

10

11

Verghese, SST, 2012

~0.4 eV for UT SOI

Work Function Requirements and

Options

12

Polishchuk, 2001

Metal gates – challenge to control work function and stability

13

Fermi Level Pinning

Fully Silicided Gate FUSI

NiSi doped with As (4.58 eV), B (5.1. eV), or undoped poly_Si (4.87 eV) – doping changes the workfunctionNixSiy &phase change the workfuction as well 4.44 eV 5.0 eV

For metal gates metal induced surface states MIGS

14Frank&Taur, SSE, 2002

15

Process Flow for ICs

Define;• components• their parameters • tolerances• limitations

• range of operating T• reliability• tools and limitations in production• overall costs

Define process flow• simulate devices and processes• run experimental short-loops

• use test structures• design, simulate and process complete test structure that

includes• process monitoring• components’ parameters testing• their tolerances & reliability• yield structure

16

A Conventional CMOS Logic Process Flow - STI

1019cm-3 (100)

1015-1016cm-3 epi

Depth~0.25-0.5µm

10-15nm

100-150nm

10-20nmEtch oxide for easier CMP

Nitride is the stop layer

17

A Conventional CMOS Logic Process Flow – Well implantsOxide&nitride pads removed;

grow

Oxide is used to decrease channeling effect in implantation &protect the surface

P-well for NMOS will be similarly done by Implantation

Tailored profile in Implantation

18

• Sacrificial oxide etched

• Gate oxide grown 3-4 nm

• Undoped poly-Si grown

• PolySi patterned by RIE

• Pattern NMOS vs PMOS

• Implant S/D & gate• Thin oxide on poly

removes RIE damage and protects gate in P/As implant

• Halo implants

ox~10-15 nm

CVD deposition and etch back of nitride 100-150nm

Poly-Si gate doping: • single workfunction (ex. P – watch for VT in PMOS that gives buried channel)• dual workfunction (ex. B outdiffusioncan also lead to buried channels PMOS)• watch for poly-Si depletion

Watch for junction leakage due to silicon consumption during silicidation

Remove oxide and sputter deposit ~20-30nm metal: Ti, Co Ni

A Conventional CMOS Logic Process Flow – gates/junctions/contacts

19Park &Hu

A Few Notes on Spacers

20

21Niwa, Sematech Symposium

22

What we Gain by Using Metal Gates

Hoffmann,SST, 2010

23

Metal Gates

Gate first or gate last=replacement-gate?

CMP

24

Dual Metal Gate for High CMOS Performance Process Flow

Yeo, IEEE, 2004

Niwa, Sematech Symposium

25

Dual Work Function Gates

20 nm

10 nm

5 nm

20 nm

LOCOS replaced by STI

For PMOS use Ru as a gate electrode

26

Metal Interdiffusion Approach

Yeo, IEEE, 2004

(Ti~4eV)(Ni~5eV)

Single Metal Doping Approach

~5eVDecreased to~4.5eV

27

Dual Workfunction Metal Gate Process

ALD

Reactive sputtering TiN wet

etch

Reactive Sputtering of TaSiN

Heavy doped

28

Niwa, Sematech Symposium

Gate Stacks in High-K/Metal Gate System

29

Fully Silicided Polysilicon FUSI

Earlier shown for CoSi2 - 100nm

Workfunction modified by Ni/Si ratio: • Si-rich fm~4.5 eV (NMOS)•Ni-rich fm~4.85 eV (PMOS)

• Silicidation can be done for NMOS and PMOS

• Dopant concentration changes work function

• Use M1 at the gate & other metal M2 on top

30

FUSI Using Ni-Silicidation on Doped Poly Si

As and B dopingChanges of WF values by As (snow plow) but not by B

Maszara et al. IEEE 2002

31

NMOS for different silicidation

NMOS gate leakage larger for FUSI than for Poly-SI gate

FUSI – Limitations

32

HP Yu et al., 2006

FUSI using Amorphous Si and Ni-Silicide

The role of oxygen (measure profiles) in incomplete silicidation

900°C/20min

6-19nm

400°C/5min

100nm

33Takalashi et al. IEDM, 2004

Phase Controlled FUSI Doped and Undoped Poly-Si (950°/10s)

Dielectrics: HfSiON and SiO2

~4.8eV

~4.5eV

~4.4eV

~4.8eV

~4.4eV~4.5eV

No degradation of h&el mobility

34

Metal Gates - Deposition (ALD) of Metallic Films

H. Kim, Sematech Mtg, 2012

35

FLP effect interface dipoles change EWF

Measurements done on variable oxide thickness

Eizenberg and Kornblum, Sematech Mtg.

36

K=8

Interfacial layer increases EWF of TaAl & P have EWF as in vacuum

Interfacial layers change EWFUse Capping Layers

Rothschild, Sematech Mtg.

HfNx gate (N/Hf ratio 0 to 2)

Another example: Hf NMOS & HfNxPMOS

Interface from processing issues (reactive sputtering etc.)

37

Planar Replacement Gate Device Structure

Capping Layers for Interfacial Charges/WF Control Constrains

Niwa, Sematech Symposium

Verghese, SST, 2012

Caps are added on purpose to set the WF due to dipoles – stability? – reliability?

38

Gate first: Al2O3 for PMOS and LaOx for NMOS used as thin capping layers for dipoles that would determine VT – Instability – roll-off.EWF higher than in MIPS (metal inserted poly-Si)

EWF in PMOS with caps roll to mid-gap upon annealing

Hoffmann,SST, 2010

39Niwa, Sematech Symposium

40

41

Small Size Effects

Important: size calls for N in the substrate fluctuation in doping fluctuation fluctuation in VT – problems for circuits (analog more than digital)

42

Gate Stack

History of gates in MOSFETs: •metal gate Al – not self aligned•polysilicon n+ type• dual poly-gates• silicides poly-gates• fully silicidedpoly-gates• metal gates – midgap• metal gates – dual

43

High-k + Metal Gate Benefits

• High-k gate dielectric – Reduced gate leakage– TOX(e) scaling

• Metal gates– Eliminate polysilicon depletion– Resolves VT pinning and poor mobility for high-k dielectrics

Kawanago, PhD, 08D36028

44

Kawanago, PhD, 08D36028

45

Gate Stack Module

Gate-stack transition from silicides, doped poly-Si on SiO2 to metal gates on high-K dielectric

Gates scaling movie

Hsing-Huang Tseng

•Poly-Si depletion ~1.2 nm CET by ~ 0.4 nm•Poly-Si leaks B to the channel (dielectric and Si)

46Iwai