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Course OverviewThis course covers the verification process used in validating the functional correctness in today's complex Application Specific Integrated Circuits (ASICs). Topics include fundamentals of simulation based functional verification, stimulus generation, results checking, coverage, debug, and assertions. Provides the students with real world verification problems to allow them to apply what they learn.

Instructor

Dr. Meeta Yadav

Email: myadav@ncsu.edu

Office hours: TBD

Prof. Paul Franzon Email: paulf@ncsu.edu Office hours: By e-mail

TAs

TBD

PrerequisiteECE 520 ASIC Design or equivalent. A good working knowledge of Verilog or VHDL is essential. This is not suitable as a first course in a hardware description language.

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Design Complexity

Image Processing Location-Based Services

Telematics

Broadcasting

Computing

Communication Entertainment

Designs become complex as more functionality is added to them

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Technology Scaling

Increased functionality increases the number of transistors in the design thus increasing the possibility of error in the design

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[Collet 2005]

Bug Trends

50% of ASICs require more than one respin 75% of them have logical or functional bugs

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1. Making sure there are no bugs in the design

2. All design functionality has been implemented

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Traditional Verification methods cannot keep up with the verification challenge

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Functional Verification

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Mentors QuestaSim

Tool

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SystemVerilog

Language

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Create a verification plan and list what you are going to verify and how

Verification Plan

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Generate and Apply Stimulus

Testbench Development

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Testbench functionality Generate stimulus Apply stimulus to the Design Under Test (DUT)

Design Under Test S

timul

us

App

licat

ion

Stim

ulus

Gen

erat

ion

Testbench Development

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Capture Response and Check for correctness

Testbench Development

Generate and Apply Stimulus

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Testbench functionality Generate stimulus Apply stimulus to the Design Under Test (DUT) Capture the response Check for correctness

Design Under Test S

timul

us

App

licat

ion

Stim

ulus

Gen

erat

ion

Res

pons

e C

aptu

re

Cor

rect

ness

Che

ck Golden Model

Testbench Development

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Measure Progress (Coverage)

Testbench Development

Capture Response and Check for correctness

Generate and Apply Stimulus

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Testbench functionality Generate stimulus Apply stimulus to the Design Under Test (DUT) Capture the response Check for correctness Measure the progress against the overall verification goals

Design Under Test S

timul

us

App

licat

ion

Stim

ulus

Gen

erat

ion

Res

pons

e C

aptu

re

Cor

rect

ness

Che

ck Golden Model

Progress Check and Control of Verification Process

Testbench Development

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Measure Progress (Coverage)

Testbench Development

Capture Response and Check for correctness

Generate and Apply Stimulus

Write Assertions

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Testbench functionality Generate stimulus Apply stimulus to the Design Under Test (DUT) Capture the response Check for correctness Measure the progress against the overall verification goals

Design Under Test S

timul

us

App

licat

ion

Stim

ulus

Gen

erat

ion

Res

pons

e C

aptu

re

Cor

rect

ness

Che

ck Golden Model

Progress Check and Control of Verification Process

Testbench Development

Assertions

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Projects

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Project 1

Un-pipelined LC3 processor

Stim

ulus

A

pplic

atio

n

Stim

ulus

Gen

erat

ion

Res

pons

e C

aptu

re

Cor

rect

ness

Che

ck Golden Model

Project 1: Perform functional verification on the unpipelined LC3 microprocessor Find bugs in the design Analyze the bugs Include all the tests to recreate the bugs

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Project 2a

Pipelined LC3 processor

Stim

ulus

A

pplic

atio

n

Stim

ulus

Gen

erat

ion

Res

pons

e C

aptu

re

Cor

rect

ness

Che

ck Golden Model

Project 2a: Perform functional verification on pipelined LC3 microprocessor Find bugs in the design Analyze the bugs Include all the tests to recreate the bugs

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Project 2b

Project 2b Perform coverage on pipelined LC3 microprocessor Write assertions Detect bugs Analyze bugs

Design Under Test S

timul

us

App

licat

ion

Stim

ulus

Gen

erat

ion

Res

pons

e C

aptu

re

Cor

rect

ness

Che

ck Golden Model

Progress Check and Control of Verification Process

Assertions

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Course Overview

Topics

1. Introduction to Verification

2. Test Bench Environments

3. Interfaces

4. Stimulus Generation

5. Object Oriented Programming

5. Functional Coverage

6. Assertions

7. SystemVerilog Language Constructs

TextC. Spear, System Verilog for Verification, Springer 2006. "

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References

Comprehensive functional verification the complete industry cycle by Bruce Wile, John C. Goss, Wolfgang Roesner.Elsevier/Morgan Kaufmann, c2005

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear. Springer, 2006

SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart Sutherland, Simon Davidman, Peter Flake and P. Moorby. Springer, 2006

Verification Methodology Manual for SystemVerilog by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale. Springer, 2005

SystemVerilog Assertions Handbook by Ben Cohen, S Venkataramananm, A Kumari. VhdlCohen Publishing, 2005.

SystemVerilog 3.1a , Language Reference Manual Accelleras Extensions to Verilog

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Course Overview

Evaluation

Labs 15% There will be 5 labs

Midterm 15% The exams will be open book and open notes

Project 1 15% Verification of an LC3 microprocessor by developing a test environment using SystemVerilog. Students will be required to find embedded bugs in the design and analyze them.

Project 2a and Project 2b

35% Verification of an LC3 microprocessor by developing a complete test environment using SystemVerilog, writing SVA and gathering functional coverage metrics. Students will be required to find embedded bugs, analyze them and report functional coverage numbers.

Final 20% The exam will be comprehensive and open books and open notes.

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Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

Designers are doing Verification

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Thank You