lec1 course overview
DESCRIPTION
LectureTRANSCRIPT
©2011, Meeta Yadav 1
ASIC Verification
Course Overview
Fall 2011Meeta Yadav
©2011, Meeta Yadav 2
Course Overview
This course covers the verification process used in validating the functional correctness in today's complex ApplicationSpecific Integrated Circuits (ASICs). Topics include fundamentals of simulation based functional verification, stimulusgeneration, results checking, coverage, debug, and assertions. Provides the students with real world verificationproblems to allow them to apply what they learn.
Instructor
Dr. Meeta Yadav
Email: [email protected]
Office hours: 4:00 to 5:00 Fridays, 3:00 to 4:00 Thursday (DE)
TAS
TBD
Prerequisite
ECE 520 ASIC Design or equivalent. A good working knowledge of Verilog or VHDL is essential. This is not
suitable as a first course in a hardware description language.
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What is ASIC Verification?
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Design Complexity Increasing
Image ProcessingLocation-Based Services
Telematics
Broadcasting
Computing
Communication
Entertainment
Designs are becoming more complex as more functionality is added to them
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Increase in Transistors Per Die
Increased functionality increases the number of transistors in the design thus increasing the possibility of error in the design
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[Collet 2005]
Increase in Design Bugs
50% of ASICs require more than one respin
75% of them have logical or functional bugs
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Solution is:
ASIC Verification
Functional Verification Formal Verification
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ASIC Verification is:
1. Making sure there are no bugs in the design
2. All design functionality has been implemented
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What will you learn in this class?
To develop a Verification Plan
What to Verify?
How to Verify it?
Develop a reusable testbench
Write Assertions
Perform Coverage
OOP
VMM Methodology
Think
Get close to the bug
When am I done?
Close the gap
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• Testbench functionality Generate stimulus
Apply stimulus to the Design Under Test (DUT)�
Design
Under
TestStim
ulu
s
App
lication
Stim
ulu
s G
en
era
tion
Testbench Development
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• Testbench functionality Generate stimulus
Apply stimulus to the Design Under Test (DUT)
Capture the response
Check for correctnessA
Design
Under
TestStim
ulu
s
App
lica
tio
n
Stim
ulu
s G
ene
ration
Respo
nse
Cap
ture
Corr
ectn
ess C
heckGolden Model
Testbench Development
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• Testbench functionality Generate stimulus
Apply stimulus to the Design Under Test (DUT)
Capture the response
Check for correctness
Measure the progress against the overall verification goals
Design
Under
TestStim
ulu
s
App
lica
tio
n
Stim
ulu
s G
ene
ration
Respo
nse
Cap
ture
Corr
ectn
ess C
heckGolden Model
Progress Check and Control of Verification Process
Testbench Development
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• Testbench functionality Generate stimulus
Apply stimulus to the Design Under Test (DUT)
Capture the response
Check for correctness
Measure the progress against the overall verification goals
Design
Under
TestStim
ulu
s
App
lica
tio
n
Stim
ulu
s G
ene
ration
Respo
nse
Cap
ture
Corr
ectn
ess C
heckGolden Model
Progress Check and Control of Verification Process
Testbench Development
Assertions
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SystemVerilog
Language and Tools
QuestaSim
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Course Overview
Topics1. Introduction to Verification
2. Test Bench Environments
3. Interfaces
4. Stimulus Generation
5. Object Oriented Programming
5. Functional Coverage
6. Assertions
7. SystemVerilog Language Constructs
TextC. Spear, System Verilog for Verification, Springer 2006
or most recent
http://www.asicverification.org
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Course Overview
Evaluation
Labs 15% There will be 5 labs
Midterm 15% The exam will be open book and open notes
Project 50% Verification of an LC3 microprocessor by developing a reusable test environment using SystemVerilog, and gathering functional coverage metrics. Students will be required to find embedded bugs and validate them against a list provided and report functional coverage numbers.
Final 20% The exam will be comprehensive and open books and open notes.
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Project
Perform Functional Verification on pipelined LC3 microprocessor using a reusable testbench
Validate the bug list
Perform coverage
Demo: Detect bug in the design in 1 hour, analyze the bug
Design
Under
Test
Stim
ulu
s
Applic
atio
n
Stim
ulu
s G
ene
ration
Respo
nse
Captu
re
Corr
ectn
ess C
heck
Golden Model
Progress Check and Control of Verification
Process
Assertions
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References
• Comprehensive functional verification the complete industry cycle by Bruce Wile, John C. Goss, Wolfgang Roesner. Elsevier/Morgan Kaufmann, c2005
• SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear. Springer, 2006 or most recent
• SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart Sutherland, Simon Davidman, Peter Flake and P. Moorby. Springer, 2006
• Verification Methodology Manual for SystemVerilog by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale. Springer, 2005
• SystemVerilog Assertions Handbook by Ben Cohen, S Venkataramananm, A Kumari. VhdlCohenPublishing, 2005.
• SystemVerilog 3.1a , Language Reference Manual Accellera’s Extensions to Verilog®
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Chances of you doing Verification in the industry if you stay in this
field?
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Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission
Designers are doing Verification
Very High
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Thank You