ecse$425$lecture$2:$ trends$in$computer$architecture$ · 2011-09-07 · ecse$425$lecture$2:$...
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![Page 1: ECSE$425$Lecture$2:$ Trends$in$Computer$Architecture$ · 2011-09-07 · ECSE$425$Lecture$2:$ Trends$in$Computer$Architecture$ H&P,$Chapter$1$ ©$2011$Hayward,$Arbel,Gross, Tsikhana,$Vu,$Meyer;$](https://reader030.vdocuments.net/reader030/viewer/2022040506/5e3e9d6d2a1fae078a5dbfaf/html5/thumbnails/1.jpg)
ECSE 425 Lecture 2: Trends in Computer Architecture
H&P, Chapter 1
© 2011 Hayward, Arbel, Gross, Tsikhana, Vu, Meyer;
Textbook figures © 2007 Elsevier Science
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AdministraOve MaPers
• Tutorial – Fridays, 3:35-‐4:25 PM, TR 0060
• Homework 1 – Out today
• WebCT
• hPp://www.info425.ece.mcgill.ca
– Due in class 9/19
2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Today
• Trends in Processor Performance • Defining computer architecture
• Technology Trends – Bandwidth vs. Latency – Transistor and wire scaling – Power
3 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Trends in Processor Performance
4 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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What Made This Improvement Possible?
• From 1986 to 2002, improvements in – Process technology (how computers are fabricated)
– Computer architecture (how computers are designed) – Compilers (how socware is prepared for computers)
• Architecture in this era: RISC – A few, simple instrucOons
– Exploit instrucOon-‐level Parallelism (ILP) – Hide memory latency with mulO-‐level cache hierarchy
5 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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What Happened in 2002?
• Since 2002, 20% / year; new challenges include – Power ⇒ temperature ⇒ reliability
– Related limits in the ILP that can be exposed – Memory latency and bandwidth “wall”
• Architecture now: mulO-‐processors – Integrate many, less complex processors on a chip
– Exploit thread-‐level parallelism (TLP) – Exploit data-‐level parallelism (DLP)
6 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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What is Computer Architecture?
• Computer architecture is the art and science of – selec%ng hardware components, and
– interconnec%ng hardware components, in order to – sa%sfy applica3on requirements.
• Three aspects of computer architecture – InstrucOon set architecture (ISA) – Computer organizaOon – Computer hardware
7 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
SpecificaOon
ImplementaOon
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InstrucOon Set Architecture (ISA) • An ISA is a contract between – Socware developers, and – Hardware designers
• The ISA defines … – FuncOonal behavior of a processor – HW interface exposed to socware
• The ISA typically includes … – Assembly language definiOon – Programming model
• Examples of ISAs – 80x86, ARM, MIPS64, PowerPC, SPARC
8 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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ImplemenOng an ISA • Now, implementaOon >> ISA design – Computer organizaOon – Computer hardware
• OrganizaOon (a.k.a., micro-‐architecture) – Pipelining, funcOonal unit mix, memory hierarchy, branch predicOon, etc.
• Example: AMD Opteron 64 and Intel PenOum 4 – Same ISA, different organizaOons – Opteron: 12 stage int pipe, 1 MB L2 – P4: 20 stage int pipe, Hyper-‐Threading™, 512 KB L2
9 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Computer Hardware • Logic design and packaging – Manufacturing technology – Circuit design strategy – Memory interface
• Has implicaOons for – Clock rate – Power dissipaOon – Die area – Cooling requirements
• Example: PenOum 4, Mobile PenOum 4 – Same organizaOon, with different target applicaOons
10 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Architecture in Context
• Recall that computer architecture is – InstrucOon set architecture – Computer organizaOon – Computer hardware
• An ISA may be used for decades (x86) – Future-‐proof your architecture!
• Architects must therefore be aware of trends in – Use: what do users want – Technology: what can hardware do
11 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Trends in Computer Architecture
• Trends in Technology – Performance: bandwidth vs. latency
– Transistor and wire scaling • Trends in Power • Trends in Cost • Trends in Reliability – This is my area of research
12 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Trends in Technology
• Technologies that impact architecture: – Logic manufacturing technology
• Transistor Density: ~ 35% / yr • Die size: ~ 10-‐20%
• # transistors per chip: ~ 40-‐55%
– Memory (DRAM) manufacturing technology • Capacity ~ 40%
– Storage technology • MagneOc disk density ~ 30% (since 2004)
– Network technology
13 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Bandwidth vs. Latency • Processor: ‘286, ‘386, ‘486,
PenOum, PenOum Pro, PenOum 4 – (21x,2250x)
• Ethernet: 10Mb, 100Mb, 1000Mb, 10000 Mb/s – (16x,1000x)
• Memory: 16bit plain DRAM, Page Mode DRAM, 32b, 64b, SDRAM, DDR – (4x,120x)
• Disk : 3600, 5400, 7200, 10000, 15000 RPM – (8x, 143x)
14 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Bandwidth vs. Latency • Processor: ‘286, ‘386, ‘486,
PenOum, PenOum Pro, PenOum 4 – (21x,2250x)
• Ethernet: 10Mb, 100Mb, 1000Mb, 10000 Mb/s – (16x,1000x)
• Memory: 16bit plain DRAM, Page Mode DRAM, 32b, 64b, SDRAM, DDR – (4x,120x)
• Disk : 3600, 5400, 7200, 10000, 15000 RPM – (8x, 143x)
15 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Bandwidth vs. Latency • Processor: ‘286, ‘386, ‘486,
PenOum, PenOum Pro, PenOum 4 – (21x,2250x)
• Ethernet: 10Mb, 100Mb, 1000Mb, 10000 Mb/s – (16x,1000x)
• Memory: 16bit plain DRAM, Page Mode DRAM, 32b, 64b, SDRAM, DDR – (4x,120x)
• Disk : 3600, 5400, 7200, 10000, 15000 RPM – (8x, 143x)
16 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Bandwidth vs. Latency • Processor: ‘286, ‘386, ‘486,
PenOum, PenOum Pro, PenOum 4 – (21x,2250x)
• Ethernet: 10Mb, 100Mb, 1000Mb, 10000 Mb/s – (16x,1000x)
• Memory: 16bit plain DRAM, Page Mode DRAM, 32b, 64b, SDRAM, DDR – (4x,120x)
• Disk : 3600, 5400, 7200, 10000, 15000 RPM – (8x, 143x)
17 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Scaling: Moore’s Law
18 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
[Credit: Wgsimon, wikepedia.com]
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Transistor and Wires Scaling
• Process technology nodes are defined by their feature size – Minimum width of a transistor or wire
• As feature size decreases linearly … – QuadraOc increase in transistor density – Linear increase in transistor performance
19 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Scaling and Architecture
• Datapath width – 4, 8, 16, 32, and 64 bit architectures (buses, ALU’s)
• Datapath organizaOon – Longer pipelines – More complex branch predicOon
• On-‐chip memory – L1, L2 and L3 caches
• PropagaOon delay is a major problem – P4 dedicates two pipeline stages to propagaOon delay
20 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Trends in IC Power
• Total Power = Dynamic Power + StaOc Power • Dynamic (switching) power – Power consumed charging and discharging capacitances in integrated circuits (ICs)
• StaOc power – Power dissipated when circuits aren’t switching – Also called “leakage” power
21 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Dynamic Power
• – alpha = switching factor – f = clock frequency – C = load capacitance – V = supply voltage
• – Half dissipated during charging – Half stored in the capacitor
22 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
Pdynamic = ↵fCV 2
Edynamic = CV 2
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StaOc Power
• • ContribuOon to P grows with each generaOon • ExponenOally dependent on – JuncOon temperature – VDD, VTh
23 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
Pstatic = Istatic · V
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Power Example
• Many microprocessors have adjustable supply voltage. Suppose a 15% reducOon in voltage results in a 15% reducOon in frequency.
• What is the effect on dynamic power?
24 ECSE 425, Fall 2011, Lecture 2 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science
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Power and Architecture
25 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Summary
• Computer architecture – InstrucOon set architecture – Computer organizaOon – Computer hardware
• Trends – Performance: increasing!
• Processor technology, comp. architecture, compilers
– Bandwidth vs. latency: easier to improve bandwidth
– Power: increasing with scaling, performance • An important limit
26 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Next Time
• More Trends – Cost – Dependability
27 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Backup Slides
28 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2
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Briefly: ImplicaOons of ILP ⇒ TLP
• What are the implicaOons of moving to exploit TLP rather than ILP? – Socware – Hardware
29 © 2011 Hayward, Arbel, Gross, Tsikhana,
Vu, Meyer; © 2007 Elsevier Science ECSE 425, Fall 2011, Lecture 2