ee115c winter 2017 digital electronic...

EE115C – Winter 2017Digital Electronic Circuits

Tue & Thu 4:00-5:50pm

2760 Boelter Hall

Topics Covered: Introduction to Digital ICs

Current equations and parasitic effects of MOS devices

Technology and layout of digital circuits

The CMOS inverter– Static operation (VTC, noise margins)

– Propagation delay, power

Combinational logic and advanced circuit styles– Design and sizing (W/L) of logic gates

– Static, dynamic behavior, and power

Interconnect: R, and C

Arithmetic blocks (data paths)

Sequential logic (latches, flip-flops)

Timing analysis

EE115C – Winter 2017 2

Design Abstraction Levels

n+n+

S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM


Course Objectives

Understand, design, and optimize digital circuits with

respect to different quality metrics:

– Power dissipation

– Speed

Prerequisites:

– EE115A (analog circuits)

– M16 (logic design)


Textbook

Publisher:

Prentice Hall 2003


EE115C Instructors


Office hours

• Thu 1-2pm

• Fri 4-5pm

• CAD tools, labs, project

Prof. Dejan

Marković

Mahmoud

Elhebeary

Office hours

• Tue 10:30am-12pm

• Fri 9:30-11am

• 56-147E Eng-IV Bldg

EE115C Weekly Schedule

Problem

Sets Due

* Discussion sessions cover identical material

Mon

Tue

Wed

Thu

Fri

Lecture2760 Boelter

Lecture2760 Boelter

OH - Prof56-147EEng-IV

DIS*2258A Franz

8 9 10 11 12 1 2 3 4 5 6

OH - Prof56-147EEng-IV

TA

mtg

OH - TA53-145Eng-IV

DIS*A51

Humnts

OH - TA53-145Eng-IV


Online Resources

Three places to bookmark:

• Wiki Course material

• Piazza Q&A

• MyUCLA Grades


http://icslwebs.ee.ucla.edu/dejan/115cwiki


User:we115c_w17

Pass:bruin_ICs

Has links to Piazza and MyUCLA

[email protected]

Submission of assignments

Personal queries

EE115C – Winter 2017 10

Course Material

Lecture notes

Homeworks

CAD tutorials

Class project

EE115C – Winter 2017 11

Schedule and Syllabus

Intro, Scaling

MOS IV Model

MOS RC Model

CMOS Inverter VTC

Delay Analysis

Power Consumption

CMOS Logic

Gate Sizing

Logical Effort Theory

Midterm

Wires, Elmore Delay

Layout: Stick Diagrams

Adder Building Blocks

Pass-Transistor Logic

Basic Tree Adders

Latches and Flip-Flops

Setup and Hold Times

Timing Analysis

Project Presentations

Review for Final Exam

EE115C – Winter 2017 12

Grading Policy & Organization

Homework (7)

Project

Miderm

Final

15%

25%

25%

35%

EE115C – Winter 2017 13

Gantt Chart

Hw #1

Hw #2

Hw #3

Hw #4

Hw #5

Hw #6

Hw #7

Project

Midterm

Final Exam

EE115C – Winter 2017 14

Exams: Closed Book

Midterm: Thu Feb 9, 4:00-5:50pm– 1 page of notes

Final: Wed Mar 22, 11:30am-2:30pm– 1 sheet (2 pages) of notes

EE115C – Winter 2017 15

Lab Sessions

Weeks 8 & 9: extra sessions (project help)

1 2 3 4 5 6 7 8 9 10Week

project

start due

extra labs

EE115C – Winter 2017 16

Software

Cadence software– Online documentation and tutorials

90nm CMOS technology (Cadence GPDK)– 9 metal layers

Important tools / skills– Design Capture: Virtuoso Schematic / Layout Editor

– Circuit Simulation: Spectre / Ocean

– Design Verification (DRC, LVS, Extraction): Assura/QRC

Cadence tutorials are on the wiki

(Courtesy: IBM)

EE115C – Winter 2017 17

EE115C Design Flow

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

EE115C – Winter 2017 18

Anatomy of the Flow:Cadence PDK Database

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

EE115C – Winter 2017 19

Anatomy of the Flow:Virtuoso Schematic and Layout Editor

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

EE115C – Winter 2017 20

Anatomy of the Flow:Assura Design Verification

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

EE115C – Winter 2017 21

Anatomy of the Flow:Spectre Simulation Environment

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

EE115C – Winter 2017 22

Flow Walkthrough:Enter the Flow

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

1

EE115C – Winter 2017 23

Flow Walkthrough:#1: Schematic Capture

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

2

1

EE115C – Winter 2017 24

Flow Walkthrough:#2: Circuit Simulation

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

Spectre

models

simulation

Analog Env.

Spectre

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

2

3

1

EE115C – Winter 2017 25

Flow Walkthrough:#3: Layout Capture

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

schematic

simulation

results

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

2

3

4

1

EE115C – Winter 2017 26

Flow Walkthrough:#4: Design Verification

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

schematic

simulation

results

2

3

4

5

1

EE115C – Winter 2017 27

Flow Walkthrough:#5: Post-Layout Simulation

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

Spectre

models

simulation

Analog Env.

Spectre

compare results

(finish)

schematic

simulation

results

2

3

4

5

6

6

1

EE115C – Winter 2017 28

Flow Walkthrough:#6: Comparison of Results

Vitruoso VXL

layoutlayouts

& pcells

schematic

Virtuoso

schematic

symbols

& CDFs

DRC & LVS

verification

RCX

Assura

database

post-layout

simulation

results

compare results

(finish)

schematic

simulation

results

2

3

4

5

6

6

1

EE115C – Winter 2017 29

Things You Will Learn

Tutorial # Content Learning

Tutorial 1 Account and Tool SetupAccount and Cadence library

setup, transistor IV curves.

Tutorial 2Hierarchical Schematic and

Simulation

Technology calibration (Ring OSC,

FO4), Spectre simulator.

Tutorial 3Virtuoso Layout Editing

(DRC, LVS)

Layout rules (DRC, LVS), custom

standard cell (INVX1).

Tutorial 4Schematic-driven Layout

(Virtuoso XL)

Advanced layout, standard-cell

design (NAND2X1).

Tutorial 5Hierarchical Design and

Post-Layout Verification

Hierarchical design, post-layout

verification.

Tutorial 6Advanced simulation using

OCEAN environment

Automating simulations and data

measurement.

EE115C – Winter 2017 30

EE115C – Winter 2017 31

Assignment 1: Getting Cadence to Work

After setting up Cadence (classwiki / Tool setup): – Complete Tutorial 1.1 posted on classwiki.

– Turn in a screenshot (email [email protected])

We are looking for this

and this

EE115C – Winter 2017Digital Electronic Circuits

Lecture 1:

Introduction

A Bit of History… The First Computer (1832)

The Babbage

Difference Engine– 25,000 parts

– cost: £17,470

EE115C – Winter 2017 33

The First Digital Electronic Computer

Zuse Z3

(1941)

Device: Electromechanical relay

Binary

5 – 10 Hz22b words

2K relays

Google images

EE115C – Winter 2017 34

Five Years Later

ENIAC

(1946)

Device: Vacuum tube

Decimal

5M jointshand-soldered

18K tubes

$500K$6M today

150kW

Google images

EE115C – Winter 2017 35

The First PC

Simon

(1950)

Device: Electromechanical relay

4 ops:

+, −x, >, S2b Reg/ALU

$600Google images

EE115C – Winter 2017 36

What is the Machine’s Future?

Mr. Berkeley's answer:

"Simon has two futures. In first place Simon can grow.

With another chassis and some wiring and engineering, the

machine will be able to compute decimally. Perhaps in six

months more, we may be able to have it working on real

problems. In the second place, Simon may start a fad of

building baby mechanical brains, similar to the hobby of

building crystal radio sets that swept the country in the 1920's."

[1956 Berkeley Enterprises Report]

EE115C – Winter 2017 37

Squee (The Electronic Robot Squirrel)

Eye

[1956 Berkeley Enterprises Report]Hand

Google images

EE115C – Winter 2017 38

The Transistor Revolution (1948)

First transistor

Bell Labs (1948)

EE115C – Winter 2017 39

The First Integrated Circuit (1958)

7/16" wide and containing two transistors, mounted on a bar of germanium

(Image courtesy of Texas Instruments, Inc.)

Texas Instruments (Sep 12, 1958)

EE115C – Winter 2017 40

The First Integrated Circuits (1960’s)

Bipolar logic

(1960’s)

ECL 3-input Gate

Motorola (1966)

EE115C – Winter 2017 41

Integrated Electronics

1948 (Bell Labs)

1958 (TI)

1971 (Intel)

108kHz

BJT

IC

μP

4004

EE115C – Winter 2017 42

Intel 4004 Microprocessor (1971)

2,300 transistors (12mm2)

108 KHz operation (10mm)

EE115C – Winter 2017 43

1965

44EE115C – Winter 2017

Moore’s Law

In 1965, Gordon Moore noted that the number of transistors

on a chip doubled every 18 to 24 months

[G. Moore, Electronics, 1965]

“The complexity for minimum component costs has increased at

a rate of roughly a factor of two per year. Certainly over the

short term, this rate can be expected to continue, if not to

increase. Over the longer term, the rate of increase is a bit more

uncertain, although there is no reason to believe it will not

remain nearly constant for at least 10 years. That means by

1975, the number of components per integrated circuit for

minimum cost will be 65,000.”

EE115C – Winter 2017 45

2005

46EE115C – Winter 2017

Transistors / cm2

2,000,000ximprovement

4B

100M

2M

50K

2K

10μm

19725μm

19821μm

1992130nm

200220nm

2012

40 years

Courtesy: Broadcom

EE115C – Winter 2017 47

Size: W, L, tox

Voltage: VDD, VT

EE115C – Winter 2017 48

Dennard’s Classical MOSFET Scaling (1974)

1/κ

κ

1/κ

1/κ

1/κ

1/κ

1/κ2

1

: Device dimension tox, L, W

: Doping concentration Na

: Voltage V

: Current I

: Capacitance εA/tox

: Delay time/circuit VC/I

: Power dissipation/circuit VI

: Power density VI/A

Scaling Factor Device or Circuit Parameter

R. Dennard, JSSC, Oct 1974.

EE115C – Winter 2017 49

Constant E-field Scaling

Voltage and size scale by the same factor, S (S > 1)

E = V/L = constant

Outcomes:

More transistors/area 1/S2

Faster delay 1/S

Lower energy/op 1/S3

Problem: VT scaling (exponential leakage)

EE115C – Winter 2017 50

Constant E-field Scaling

Ended at the 130nm node

EE115C – Winter 2017 51

Historical Scaling Trends

Pentium Pro

Pentium ®486

3862868086

80858080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Fre

qu

en

cy (

MH

z)

Courtesy:S. Borkar(Intel)

Pentium 4

Const VDD Const E General

Powerdensity

Leakage power

EE115C – Winter 2017 52

Technology Scaling is Power Driven

Bipolar NMOS CMOS ???power

wallpower

wallpower

wall

1970 1985 2000

CMOS delivered better cost performance– It was more energy efficient

– It improved the integration level

EE115C – Winter 2017 53

Bipolar Power Wall CMOS

Technologies: bipolar, nMOS, CMOS

Constant voltage scaling: increasing power

Courtesy: Roger Schmidt (IBM)

Mo

du

le H

eat

Flu

x (

W/c

m2)

EE115C – Winter 2017 54

Scaling Scenarios: Fixed V, Fixed E, General

Parameter Relation Fixed V Fixed E General

W, L, tox 1/S 1/S 1/S

VDD, VT 1 1/S 1/U

Area/Device WL 1/S2 1/S2 1/S2

Cox 1/tox S S S

Cgate Cox WL 1/S 1/S 1/S

kn, kp Cox W/L S S S

Isat Cox WV 1 1/S 1/U

Current Density Isat / Area S2 S S2/U

Ron V / Isat 1 1 1

Intr. Delay Ron Cgate 1/S 1/S 1/S

Power Isat V 1 1/S2 1/U2

P Density Power/Area S2 1 S2/U2

EE115C – Winter 2017 55

General Scaling

Size scaling S > Voltage scaling U

Voltage scaling slowing down

VT determined by leakage

tox also set by leakage

Current increasing by stressing silicon

EE115C – Winter 2017 56

CMOS Scaling is Continuing to Change

1990’s: both VDD and L scaling

2000’s: VDD scaling slowing down, L scaling

2010’s: rate of L scaling slowing down

0.1

1

10

100

250 180 130 90 65 45 32 22

Ene

rgy

Effi

cie

ncy

(G

OP

S/m

W)

Technology Generation (nm)16 12

1

Csw ∙VDD2 ∙ (1+Elk/Esw)

Energy efficiency =

L & VDD

mostly L

L delayed

EE115C – Winter 2017 57

More than Moore: 2010+

[ITRS 2010]

EE115C – Winter 2017 58

Approaching Atomic Limits

Si atom

0.25nm

1x

80x

200,000x

20nm FET

Hair

EE115C – Winter 2017 59

Scaling Toward 10nm Node

Technology: alternative structures and

materials, post-silicon devices

Design: billion transistors, GHz operation

22nm

45nm65nm

32nm

16nm12nm

Bulk/SOI CMOS Multi-gate CMOS Post-Silicon

5 nm5 nm

5 nm

Source:K. Cao(ASU)

EE115C – Winter 2017 60

CMOS Replacement?

Replacing CMOS by another more energy efficient

technology is a distant prospect now

Low-power high-speed CMOS technology is becoming an

indispensable, rather than desirable, technology

Power is the main challenge we need to address

EE115C – Winter 2017 61

ee115c winter 2017 digital electronic...

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