ee414 embedded systems ch 3. general-purpose...

EE414 Embedded Systems

Ch 3. General-Purpose Processors: Software

Part 3/4: Beaglebone

Byung Kook KimSchool of Electrical Engineering

Korea Advanced Institute of Science and Technology

Embedded Systems, KAIST 2

OverviewThe ARM Architecture

3.31 vonNeuman Architcure 3.32 The Reduced Instruction Set Computer (RISC) 3.33 The ARM Architecture 3.34 Architectural Inheritance 3.35 The ARM Programmer’s Model

Beaglebone 3.36 Beaglebone 3.37 AM3359 Processor 3.38 Software in Beaglebone 3.39 Hardware Connection


3.31 Von Neumann Architecture

von Neumann Architecture Separate CPU and memory distinguishes computer

Memory holds data, instructions. Central processing unit (CPU) fetches instructions from memory.

CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc.

Princeton architectureHarvard Architecture

Two sets of Address/Data/Control bus to Program/Data memory


3.32 The Reduced Instruction Set Computer (RISC)

Complex instruction set computer (CISC): many addressing modes; many operations.

Reduced instruction set computer (RISC): load/store; pipelinable instructions.

Berkeley RISC I Incorporated a Reduced Instruction Set Computer (RISC)

architecture. Much simpler than CISC processors.

Order of magnitude less design effort, but similar performance.


The Reduced Instruction Set Computer (II)

RISC architecture A fixed (32-bit) instruction size with few formats

CISC: variable length instruction sets with many formats

A load-store architecture: process data only on registers and are separate from instructions that access memory CISC: allow values in memory to be used as operands in data

processing

A large register bank of thirty-two 32-bit registers, any purpose CISC: different registers for different purposes (Ex: data and address

registers in Motorola 68000)


The Reduced Instruction Set Computer (III)

RISC organization Hard-wired instruction decode logic

CISC processors used large microcode ROMs to decode their instructions

Pipelined execution CISC processors allowed little, if any, overlap between

consecutive instructions (though they do now)

Single-cycle execution CISC processors typically took many clock cycles to complete

a single instruction.


The Reduced Instruction Set Computer (IV) RISC advantages

A smaller die size A shorter development time A higher performance

RISC drawbacks RISCs generally have poor code density compared

with CISCs Due to fixed-length instruction Increasing the cache miss rate

Remark: RISCs don’t execute x86 code For IBM-PC compatible


The Reduced Instruction Set Computer (V) ARM processor

Based on RISC principles Less poor code density than most other RISCs

CISC feature added. Thumb architecture

16-bit compressed form of the original 32-bit ARM Dynamic decompression hardware in the instruction pipeline Code density better than most CISC processors

Beyond RISC No development visible at the time of writing Better instruction set

Efficient implementation Multimedia support


3.33 The ARM Architecture ARM processor

Developed at Acorn Computers Limited of Cambridge, England 1983-1985 The first RISC microprocessor developed for commercial use ARM was born through a serendipitous combination of factors

ARM (Advanced RISC Machine) Limited established in 1990 Licensed to many semiconductor manufacturers Market leader for low-power and cost-sensitive embedded

applications Supported by a toolkit

Instruction set emulator for hardware modeling, software testing, and benchmarking

Assembler, C and C++ compilers, linker, and a symbolic debugger


3.34 Architectural Inheritance Features used in ARM (from Berkeley RISC design)

A load-store architecture Fixed-length 32-bit instructions 3-address instruction formats.

Simplicity in Design Keep the design simple

Full-custom CMOS design Simplicity of ARM

Instruction set architecture & Hardware organization Retain a few CISC features

Significantly better code density than a pure RISC

Result Power-efficiency & Small core size


Architectural Inheritance Features of the ARM instruction set

The load-store architecture 3-address data processing instructions

2 source and destination registers Conditional execution of every instruction Inclusion of very powerful load and store multiple register

instructions Ability to perform a general shift operation and a general ALU

operation in a single instruction that executes in a single clock cycle

Open instruction set extension through the coprocessorinstruction set, including adding new registers and data types to the programmer’s model

A very dense 16-bit compressed representation of the instruction set in the Thumb architecture


3.35 The ARM Programmer’s Model

Visible registers in an ARM processor

r13_und r14_und r14_irq

r13_irq

SPSR_und

r14_abt r14_svc

user mode fiqmode

svcmode

abortmode

irqmode

undefinedmode

usable in user mode

system modes only

r13_abt r13_svc

r8_fiqr9_fiq

r10_fiqr11_fiq

SPSR_irq SPSR_abt SPSR_svc SPSR_fiqCPSR

r14_fiqr13_fiqr12_fiq

r0r1r2r3r4r5r6r7r8r9r10r11r12r13r14r15 (PC)


The ARM Programmer’s Model (II) User-level program

15 general-purpose registers (r0 to r14) Program counter (r15) Current program status register (CPSR) Remaining registers: only for system–level programming and

handling exceptions CPSR

Stores the condition code bits N: Negative. Bit 31 Z: Zero. Bit 30 C: Carry. Bit 29 V: oVerflow. Bit 28

N Z C V unused mode31 28 27 8 7 6 5 4 0

I F T


The ARM Programmer’s Model (III)

Memory system Linear array of bytes from 0 to 232 -1

Data items: 8-bits, 16-bits, 32-bits Words are always aligned on 4-byte boundaries Half-words are aligned on even byte boundaries

Memory organization Little endian

MS byte of data in higher byte addr. Big endian.

MS byte of data in lower byte addr.

half-word4

word16

0123

4567

891011

byte0byte

12131415

16171819

20212223

byte1byte2

half-word14

byte3

byte6

address

bit 31 bit 0

half-word12

word8


3.36 BeagleboneBeaglebone Overview

The latest addition to the BeagleBoard.org family

Designed to address the Open Source Community, early adopters, and anyone interested in a low cost ARM Cortex A8 based processor.

Equipped with a minimum set of features to allow the user to experience the power of the processor

Not intended as a full development platform

Credit-card size Expandable

Ref. Beaglebone System Reference Manual. www.beagleboard.org

Beaglebone Specification Processor: AM3359.

500MHZ-USB Powered. 720MHZ-DC Powered. Memory: 256MB DDR2 400MHZ (128MB Optional) SD/MMC Connecto:r microSD, 3.3V

PCB: 3.4” x 2.1” 6 layers. Credit-card size. Power: USB 5VDC External jack Weight: 1.4 oz (39.68 grams)

Embedded Systems, KAIST 16Ref. Beaglebone System Reference Manual. www.beagleboard.org

Beaglebone Spec: Input/Output User Input: 1-Reset Button User Indicators: Power, 4-User Controllable LEDs HS USB 2.0 Client Port: Access to the USB1 Client mode HS USB 2.0 Host Port: USB Type A Socket, 500mA LS/FS/HS Ethernet: 10/100/1000, RJ45 Expansion Connectors

Power 5V, 3.3V, VDD_ADC(1.8V). 3.3V I/O on all signals McASP0, SPI1, I2C, GPIO(65), LCD, GPMC, MMC1, MMC2, 7 AIN(1.8V MAX), 4 Timers, 3 Serial Ports, CAN0, EHRPWM(0,2), XDMA Interrupt, Power button, Battery Charger LED Backlight, Expansion Board ID (Up to 3 can be stacked)


Board Connector and Indicator Locations


Beaglebone - System Block Diagram


Expansion Header P8 Pinout


Expansion Header P9 Pinout


3.37 AM3359 Processor


ARM Cortex-A8 MPU Subsystem



3.38 Software in Beaglebone Program storage

RAM – Loss of contents when power-off microSD (flash memory) – No loss when power off. Preinstalled

software can reside.

Possible software in microSD (Flash) Embedded Linux: Angstrom Linux: Ubuntu, Debian, ArchLinux, Gentoo, Sabayon, Buildroot,

Erlang, Fedora Windows CE Android Other: QNX, FreeBSD

3.39 Hardware Connection


Router

A router contains capability to connect multiple computers to the network with single IP port.

Moreover, it has capability of assigning floating IPs to slave computers using DHCP.

Hence, for the upper connection from the router to KAIST network, we use an IP for KAIST network, such as 143.248.aaa.bbb.

For the lower connections from the router to computer and embedded board, the router can be programmed to assign IPs in a specific range, e.g., from 192.168.100.2 to 192.168.100.254.

The router occupies its own IP address, e.g., 192.168.100.1. Note that the KAIST network should start with 143.248 and the

floating IPs should start with 192.168, according to international agreement on IPv4.


Linux Console Connection Beaglebone with Linux

Console input/output via UART0 Universal Asynchronous Receiver/Transmitter

FT2232H chip Serial-to-USB converter

2 Port USB Hub chip USB connector USB cable

PC USB connector USB-to-serial driver SW Minicom (or screen) in terminal Keyboard & display!!



Reference

[1] BeagleBone Rev A5 System Reference Manual http://beagleboard.org/static/beaglebone/latest/Docs/Hardware/BONE_SRM.pdf

[2] AM3359 Datasheet, AM335x ARM Cortex-A8 Microprocessors (MPUs) (Rev. D), http://www.ti.com/lit/ds/sprs717d/sprs717d.pdf

[3] Technical Reference Manual - AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F), http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf

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