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gital Integrated Circuits 2nd Inverter EE4271 EE4271 VLSI Design VLSI Design The Inverter The Inverter Dr. Shiyan Hu Office: EERC 518 [email protected] Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

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EE4271 VLSI Design. Dr. Shiyan Hu Office: EERC 518 [email protected]. The Inverter. Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Circuit Symbols. V. DD. S. D. V. V. in. out. D. C. L. S. - PowerPoint PPT Presentation

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Page 1: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

EE4271 EE4271 VLSI DesignVLSI Design

The InverterThe Inverter

Dr. Shiyan HuOffice: EERC [email protected]

Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

Page 2: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

Circuit SymbolsCircuit Symbols

Page 3: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance

Vin=Vdd,Vout=0Vin=0,Vout=Vdd

V in Vout

CL

VDD

S

D

D

S

Page 4: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

CMOS Inverter - First-Order DC AnalysisCMOS Inverter - First-Order DC Analysis

VDD VDD

Vin VDD Vin 0

VoutVout

Rn

Rp

Page 5: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response

VoutVout

Rn

Rp

VDDVDD

Vin VDDVin 0(a) Low-to-high (b) High-to-low

CLCL

Delay=0.69RC

Page 6: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

NMOS In InverterNMOS In Inverter For NMOS

1. Vin=0, Vgsn=0<Vtn, Vdsn=Vout=Vdd, NMOS is in cut-off region, X1.

2. PMOS is on. Vout=Vdd.

3. Vin=Vdd, instantaneously, Vgsn=Vdd>Vtn,Vdsn=Vout=Vdd, Vgsn-Vtn=Vdd-Vtn<Vdd, NMOS is in saturation region, X2

4. Instantaneously, Vgsp=0>Vtp. PMOS cut-off

5. NMOS is on so Vdsn->0. The operating point follows the arrow to the origin. Vout=0 at X3.Vin Vout

CL

VDD

S

D

D

S

Page 7: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS InverterThe CMOS Inverter

V in Vout

CL

VDD

S

D

D

S

Assume that Idsp=-Idsn when both transistors are on and Vtn=|Vtp|

Page 8: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter – 2 The CMOS Inverter – 2 (Region A)(Region A)

V in Vout

CL

VDD

S

D

D

S

0<Vin<Vtn

Vgsn=Vin<Vtn, NMOS cut-off

|Vgsp|=|Vin-Vdd|>|Vtp|,|Vdsp|=|Vd-Vdd|~0<|Vgsp-Vtp| PMOS linear region

Vd is close to Vdd

Page 9: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter – 3The CMOS Inverter – 3(Region B)(Region B)

V in Vout

CL

VDD

S

D

D

S

Vtn<Vin<Vdd/2

Vgsn=Vin>Vtn, Vdsn=Vout=Vdd>Vgsn-VtnNMOS saturation region

|Vgsp|=|Vin-Vdd|>Vdd/2>|Vtp|,|Vdsp|~0<|Vgsp-Vtp|PMOS linear region

Page 10: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter - 4The CMOS Inverter - 4

Page 11: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter – 5The CMOS Inverter – 5(Region C)(Region C)

V in Vout

CL

VDD

S

D

D

S

Vin=Vdd/2

Vgsn>Vtn, Vdsn>Vgsn-Vtn, saturation

|Vgsp|=|Vin-Vdd|>|Vtp|,|Vdsp|>|Vgsp-Vtp|, saturation

Page 12: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter - 6The CMOS Inverter - 6

Usually we set for equal rising and falling propagation delay (same R for both devices)

Since , we have

Usually,

Page 13: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter 7The CMOS Inverter 7

Vin=Vout=Vdd/2 The above analysis is actually correct

for Vin=vdd/2 and all Vout such that both devices are in saturation regions For NMOS, Vout>Vin-Vtn For PMOS, Vgsp-Vtp>Vdsp ->Vout<Vin-Vtp

Vin-Vtn<Vout<Vin-Vtp, so for Vin=Vdd/2, Vout can vary around Vdd/2

Page 14: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter – 9The CMOS Inverter – 9(Region D)(Region D)

V in Vout

CL

VDD

S

D

D

S

Vdd/2<Vin<Vdd-|Vtp|

Vgsn=Vin>Vtn, Vdsn=Vout<Vgsn-VtnNMOS linear region

|Vgsp|=|Vin-Vdd|>|Vtp|,|Vdsp|=|Vd-Vdd|>|Vgsp-Vtp|, PMOS saturation region

Page 15: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter - 10The CMOS Inverter - 10

Page 16: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter – 11The CMOS Inverter – 11(Region E)(Region E)

V in Vout

CL

VDD

S

D

D

S

Vin>Vdd-|Vtp|

Vgsn=Vin>Vtn, Vdsn<Vgsn-VtnNMOS linear

|Vgsp|=|Vin-Vdd|<|Vtp|,PMOS cut-off

Page 17: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter -12The CMOS Inverter -12

Page 18: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

The CMOS InverterThe CMOS Inverter

Page 19: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

Circuit Under DesignCircuit Under Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

Page 20: EE4271 VLSI Design

© Digital Integrated Circuits2nd Inverter

Its Layout ViewIts Layout View


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