ee6502 microprocessor & microcontroller regulation 2013

EE6502Microprocessors and

Microcontrollers

Presented byC.GOKUL,AP/EEE

Velalar College of Engg & Tech , Erode

DEPARTMENTS: EEE {semester 05}Regulation : 2013

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syllabus

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Microprocessor

• Microprocessor (µP) is the “brain” of a computer that has been implemented on one semiconductor chip.

• The word comes from the combination micro and processor.

• Processor means a device that processes whatever(binary numbers, 0’s and 1’s)

To process means to manipulate. It describes all manipulation.

Micro - > extremely small

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Definition of a Microprocessor.

The microprocessor is a programmable device that takes in numbers, performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result.

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Microprocessor ?

A microprocessor is multi programmable clock driven

register based semiconductor device that is used to fetch ,

process & execute a data within fraction of seconds.

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Applications

• Calculators• Accounting system• Games machine• Instrumentation• Traffic light Control• Multi user, multi-function environments• Military applications• Communication systems

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MICROPROCESSOR HISTORY

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DIFFERENT PROCESSORS AVAILABLE

Socket

Processor

Pinless Processor

Slot Processor

ProcessorSlot

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Development of Intel Microprocessors

• 8086 - 1979• 286 - 1982• 386 - 1985• 486 - 1989• Pentium - 1993• Pentium Pro - 1995• Pentium MMX -1997• Pentium II - 1997• Pentium II Celeron - 1998• Pentium II Zeon - 1998• Pentium III - 1999• Pentium III Zeon - 1999• Pentium IV - 2000• Pentium IV Zeon - 2001

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GENERATION OF PROCESSORS

Processor Bits Speed

8080 8 2 MHz

8086 16 4.5 – 10 MHz

8088 16 4.5 – 10 MHz

80286 16 10 – 20 MHz

80386 32 20 – 40 MHz

80486 32 40 – 133 MHz

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GENERATION OF PROCESSORS

Processor Bits Speed

Pentium 32 60 – 233 MHz

Pentium Pro

32 150 – 200 MHz

Pentium II, Celeron ,

Xeon

32 233 – 450 MHz

Pentium III, Celeron

, Xeon

32 450 MHz –1.4 GHz

Pentium IV, Celeron ,

Xeon

32 1.3 GHz –3.8 GHz

Itanium 64 800 MHz –3.0 GHz

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Intel 4004 Introduced in 1971.

It was the first microprocessor by Intel.

It was a 4-bit µP.

Its clock speed was 740KHz.

It had 2,300 transistors.

It could execute around 60,000 instructions per second.

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Intel 4040

Introduced in 1971.

It was also 4-bit µP.

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8-bit Microprocessors

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Intel 8008

Introduced in 1972.

It was first 8-bit µP.

Its clock speed was 500 KHz.

Could execute 50,000 instructions per second.

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Intel 8080

Introduced in 1974.


Its clock speed was 2 MHz.


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Intel 8085 Introduced in 1976.



Its data bus is 8-bit and address bus is 16-bit.


Could execute 7,69,230 instructions per second.

It could access 64 KB of memory.

It had 246 instructions.

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16-bit Microprocessors

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INTEL 8086 Introduced in 1978.


Its clock speed is 4.77 MHz, 8 MHz and 10 MHz, depending on the version.



Could execute 2.5 million instructions per second.

It could access 1 MB of memory.

It had 22,000 instructions.

It had Multiply and Divideinstructions.

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It was created as a cheaper version of Intel’s 8086.

It was a 16-bit processor with an 8-bit external bus.

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INTEL 80186 & 80188 Introduced in 1982.

They were 16-bit µPs.

Clock speed was 6 MHz.

80188 was a cheaper version of 80186 with an 8-bit external data bus.

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It was 16-bit µP.



It could address 16 MB of memory.

It had 1,34,000 transistors.

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32-BIT MICROPROCESSORS

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It could address 4 GB of memory.

It had 2,75,000 transistors.

Its clock speed varied from 16 MHz to 33 MHz depending upon the various versions. 24



It had 1.2 million transistors.

Its clock speed varied from 16 MHz to 100 MHz depending upon the various versions.

8 KB of cache memory was introduced.

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INTEL PENTIUM Introduced in 1993.


It was originally named 80586.



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INTEL PENTIUM PRO

Introduced in 1995.


It had 21 million transistors.

Cache memory:

8 KB for instructions.

8 KB for data.

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INTEL PENTIUM II Introduced in 1997.


Its clock speed was 233 MHz to 500 MHz.

Could execute 333 million instructions per second.

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INTEL PENTIUM II XEON

Introduced in 1998.


It was designed for servers.

Its clock speed was 400 MHz to 450 MHz.

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INTEL PENTIUM III Introduced in 1999.


Its clock speed varied from 500 MHz to 1.4 GHz.

It had 9.5 million transistors.

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INTEL PENTIUM IV Introduced in 2000.


Its clock speed was from 1.3 GHz to 3.8 GHz.

It had 42 million transistors.

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INTEL DUAL CORE Introduced in 2006.

It is 32-bit or 64-bit µP.

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64-BIT MICROPROCESSORS

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Intel Core 2 Intel Core i3

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INTEL CORE I5 INTEL CORE I7

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Basic Terms• Bit: A digit of the binary number { 0 or 1 }• Nibble: 4 bit Byte: 8 bit word: 16 bit• Double word: 32 bit • Data: binary number/code operated by an

instruction• Address: Identification number for memory

locations• Clock: square wave used to synchronize various

devices in µP• Memory Capacity = 2^n ,

n->no. of address lines

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BUS CONCEPT• BUS: Group of conducting lines that carries data ,

address & control signals.CLASSIFICATION OF BUSES:1.DATA BUS: group of conducting lines that carries

data.2. ADDRESS BUS: group of conducting lines that

carries address.3.CONTROL BUS: group of conducting lines that

carries control signals {RD, WR etc}CPU BUS: group of conducting lines that directly

connected to µPSYSTEM BUS: group of conducting lines that carries

data , address & control signals in a µP system38

TRISTATE LOGIC3 logic levels are:• High State (logic 1) • Low state (logic 0)• High Impedance state

High Impedance: output is not being driven to any defined logic level by the output circuit.

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Basic Microprocessors System

InputDevices

Processing Data into

InformationOutput Devices

Control Unit

Secondary Storage Devices

Arithmetic-Logic Unit

Primary Storage Unit

Central Processing Unit

Keyboard,Mouseetc

MonitorPrinter

Disks, Tapes, Optical Disks

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8085 PROCESSOR

UNIT

1

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UNIT 1 Syllabus• Hardware Architecture, pinouts • Functional Building Blocks of Processor • Memory organization • I/O ports and data transfer concepts• Timing Diagram • Interrupts.

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8085 PIN DIAGRAM & ARCHITECTURE

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PIN CONFIGURATION

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X1 & X2Pin 1 and Pin 2 (Input)

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These are also called Crystal Input Pins.

8085 can generate clock signals internally.

To generate clock signals internally, 8085 requires external inputs from X1 and X2.

RESET IN and RESET OUTPin 36 (Input) and Pin 3 (Output)

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RESET IN:

◦ It is used to reset the microprocessor.

◦ It is active low signal.

◦ When the signal on this pin is low for at least 3 clocking cycles, it forces the microprocessor to reset itself.

Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode


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Resetting the microprocessor means:

◦ Clearing the PC and IR.◦ Disabling all interrupts

(except TRAP).◦ Disabling the SOD pin.◦ All the buses (data,

address, control) are tri-stated.◦ Gives HIGH output to

RESET OUT pin.


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RESET OUT:

◦ It is used to reset the peripheral devices and other ICs on the circuit.

◦ It is an output signal.

◦ It is an active high signal.

◦ The output on this pin goes high whenever RESET IN is given low signal.

◦ The output remains high as long as RESET IN is kept low.


SID and SODPin 4 (Input) and Pin 5 (Output)

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SID (Serial Input Data):

o It takes 1 bit input from serial port of 8085.

o Stores the bit at the 8th

position (MSB) of the Accumulator.

o RIM (Read Interrupt Mask) instruction is used to transfer the bit.

SID and SODPin 4 (Input) and Pin 5 (Output)

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SOD (Serial Output Data):

o It takes 1 bit from Accumulator to serial port of 8085.

o Takes the bit from the 8th

position (MSB) of the Accumulator.

o SIM (Set Interrupt Mask) instruction is used to transfer the bit.

Interrupt Pins

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Interrupt:

• It means interrupting the normal execution of the microprocessor.

• When microprocessor receives interrupt signal, it discontinues whatever it was executing.

• It starts executing new program indicated by the interrupt signal.

• Interrupt signals are generated by external peripheral devices.

• After execution of the new program, microprocessor goes back to the previous program.

Sequence of Steps Whenever There is an Interrupt

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Microprocessor completes execution of current instruction of the program.

PC contents are stored in stack.

PC is loaded with address of the new program.

After executing the new program, the microprocessor returns back to the previous program.

It goes to the previous program by reading the top value of stack.

Five Hardware Interrupts in 8085

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TRAP

RST 7.5

RST 6.5

RST 5.5

INTR

Classification of Interrupts

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Maskable and Non-Maskable

Vectored and Non-Vectored

Edge Triggered and Level Triggered

Priority Based Interrupts

Maskable Interrupts

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Maskable interrupts are those interrupts which can be enabled or disabled.

Enabling and Disabling is done by software instructions.

Maskable Interrupts

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List of Maskable Interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• INTR

Non-Maskable Interrupts

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The interrupts which are always in enabled mode are called non-maskable interrupts.

These interrupts can never be disabled by any software instruction.

TRAP is a non-maskable interrupt.

Vectored Interrupts

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The interrupts which have fixed memory location for transfer of control from normal execution.

Each vectored interrupt points to the particular location in memory.

Vectored Interrupts

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List of vectored interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• TRAP

Vectored Interrupts

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The addresses to which program control goes:

Absolute address is calculated by multiplying the RST value with 0008 H.

Name Vectored Address

RST 7.5 003C H (7.5 x 0008 H)

RST 6.5 0034 H (6.5 x 0008 H)

RST 5.5 002C H (5.5 x 0008 H)

TRAP 0024 H (4.5 x 0008 H)

Non-Vectored Interrupts

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The interrupts which don't have fixed memory location for transfer of control from normal execution.

The address of the memory location is sent along with the interrupt.

INTR is a non-vectored interrupt.

Edge Triggered Interrupts

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The interrupts which are triggered at leading or trailing edge are called edge triggered interrupts.

RST 7.5 is an edge triggered interrupt.

It is triggered during the leading (positive) edge.

Level Triggered Interrupts

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The interrupts which are triggered at high or low level are called level triggered interrupts.

RST 6.5 RST 5.5 INTR

TRAP is edge and level triggered interrupt.


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Whenever there exists a simultaneous request at two or more pins then the pin with higher priority is selected by the microprocessor.

Priority is considered only when there are simultaneous requests.


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Priority of interrupts:

Interrupt Priority

TRAP 1

RST 7.5 2

RST 6.5 3

RST 5.5 4

INTR 5

TRAPPin 6 (Input)

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It is an non-maskable interrupt.

It has the highest priority.

It cannot be disabled.

It is both edge and level triggered.

It means TRAP signal must go from low to high.

And must remain high for a certain period of time.

TRAP is usually used for power failure and emergency shutoff.

RST 7.5Pin 7 (Input)

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It is a maskable interrupt.

It has the second highest priority.

It is positive edge triggered only.

The internal flip-flop is triggered by the rising edge.

The flip-flop remains high until it is cleared by RESET IN.


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It is a maskable interrupt. It has the third highest

priority. It is level triggered only. The pin has to be held high

for a specific period of time.

RST 6.5 can be enabled by EI instruction.

It can be disabled by DI instruction.


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It is a maskable interrupt.

It has the fourth highest priority.

It is also level triggered. The pin has to be held

high for a specific period of time.

This interrupt is very similar to RST 6.5.

INTRPin 10 (Input)

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It is a maskable interrupt. It has the lowest priority. It is also level triggered. It is a general purpose

interrupt. By general purpose we

mean that it can be used to vector microprocessor to any specific subroutine having any address.

INTAPin 11 (Output)

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It stands for interrupt acknowledge.

It is an out going signal.

It is an active low signal.

Low output on this pin indicates that microprocessor has acknowledged the INTR request.

Address and Data Pins

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Address Bus:

• The address bus is used to send address to memory.

• It selects one of the many locations in memory.

• Its size is 16-bit.

Address and Data Pins

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Data Bus:

• It is used to transfer data between microprocessor and memory.

• Data bus is of 8-bit.

AD0 – AD7Pin 19-12 (Bidirectional)

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These pins serve the dual purpose of transmitting lower order address and data byte.

During 1st clock cycle, these pins act as lower half of address.

In remaining clock cycles, these pins act as data bus.

The separation of lower order address and data is done by address latch.

A8 – A15Pin 21-28 (Unidirectional)

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These pins carry the higher order of address bus.

The address is sent from microprocessor to memory.

These 8 pins are switched to high impedance state during HOLD and RESET mode.

ALEPin 30 (Output)

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It is used to enable Address Latch.

It indicates whether bus functions as address bus or data bus.

If ALE = 1 then◦ Bus functions as address bus.

If ALE = 0 then◦ Bus functions as data bus.

S0 and S1Pin 29 (Output) and Pin 33 (Output)

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S0 and S1 are called Status Pins.

They tell the current operation which is in progress in 8085.

S0 S1 Operation

0 0 Halt

0 1 Write

1 0 Read

1 1 Opcode Fetch

IO/MPin 34 (Output)

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This pin tells whether I/O or memory operation is being performed.

If IO/M = 1 then◦ I/O operation is being

performed.

If IO/M = 0 then◦ Memory operation is being

performed.


IO/MPin 34 (Output)

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The operation being performed is indicated by S0 and S1.

If S0 = 0 and S1 = 1 then◦ It indicates WRITE operation.

If IO/M = 0 then◦ It indicates Memory operation.

Combining these two we get Memory WriteOperation.

Table Showing IO/M, S0, S1 and Corresponding Operations

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Operations IO/M S0 S1

Opcode Fetch 0 1 1

Memory Read 0 1 0

Memory Write 0 0 1

I/O Read 1 1 0

I/O Write 1 0 1

Interrupt Ack. 1 1 1

Halt High Impedance 0 0

RDPin 32 (Output)

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RD stands for Read.

It is an active low signal.

It is a control signal used for Read operation either from memory or from Input device.

A low signal indicates that data on the data bus must be placed either from selected memory location or from input device.

WRPin 31 (Output)

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WR stands for Write.

It is also active low signal.

It is a control signal used for Write operation either into memory or into output device.

A low signal indicates that data on the data bus must be written into selected memory location or into output device.

READYPin 35 (Input)

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This pin is used to synchronize slower peripheral devices with fast microprocessor.

A low value causes the microprocessor to enter into wait state.

The microprocessor remains in wait state until the input at this pin goes high.

HOLDPin 38 (Input)

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HOLD pin is used to request the microprocessor for DMA transfer.

A high signal on this pin is a request to microprocessor to relinquish the hold on buses.

This request is sent by DMA controller.

Intel 8257 and Intel 8237 are two DMA controllers.

HLDAPin 39 (Output)

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HLDA stands for Hold Acknowledge.

The microprocessor uses this pin to acknowledge the receipt of HOLD signal.

When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins are tri-stated.

This means they are cut-off from external environment.

HLDAPin 39 (Output)

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The control of these buses goes to DMA Controller.

Control remains at DMA Controller until HOLD is held high.

When HOLD goes low, HLDA also goes low and the microprocessor takes control of the buses.

VSS and VCCPin 20 (Input) and Pin 40 (Input)

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+5V power supply is connected to VCC.

Ground signal is connected to VSS.

THE 8085 AND ITS BUSSESThe 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory. It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz.

-The pins on the chip can be g rouped into 6 g roups:Address Bus.Data Bus.Control and Status Signals.Power supply and frequency.Externally Initiated Signals.Serial I/O ports. 88

The Address and Data Busses The address bus has 8 signal lines A8 – A15 which are

unidirectional. The other 8 address bits are multiplexed (time shared)

with the 8 data bits. So, the bits AD0 – AD7 are bi-directional and serve

as A0 – A7 and D0 – D7 at the same time.During the execution of the instruction, these

lines carry the address bits during the early part,then during the late parts of the execution, theycarry the 8 data bits.

In order to separate the address from the data, wecan use a latch to save the value before the functionof the bits changes. 89

Flag Register

CY PACZS D0 D1D2D3D4D5D6D7

The flags are affected by the arithmetic and logical instruction

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Accumulator

It is an 8 bit register For any arithmetic and logical instruction one of the data

should be in this register It is used for storing the result of any arithmetic and

logical manipulations. It is also called as A register All the data which are sent to I/O devices are sent via

A register.

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Temporary register

It is used to hold the data during the operation of arithmetic and logical operation

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Sign Flag

If the D7 bit of the accumulator is set then this flag is set i.e 1 meaning that the result is in negative.

Ex. 7-8 = -1

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Carry flag

During the arithmetic operation if a carry occurs then this flag is set.

Ex. F1+1F= 101

Carry

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Zero flag

During the arithmetic/ logical operation if the result is zero then this flag is set.Ex. FF-FF = 00

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Parity flag

After the of the arithmetic and logical operation if the result is even then this flag is set.

Ex. 0A-02 = 08

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Auxiliary carry flag

During BCD arithmetic operation when a carry is generated by D3 bit and passed on to D4 bit then this flag is set.

Ex. 1F+11 = 0001 1111 + 0001 0001

= 0010 0000

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Timing and control

It synchronizes all the operation with the clock and generates the communication between the microprocessor and peripherals

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Instruction Register and decoder

The instruction is loaded in the instruction registerThe decoder decodes them and establishes

the operation that has to be performed

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Register array

The W and Z register are temporary registersUsed to hold the 8 bit data during the

execution and it is used internally .It is not used by the programmer.

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Control and status signals

Machine Cycle IO/M S1 S0

Opcode fetch 0 1 1Memory read 0 1 0Memory write 0 0 1

I/O read 1 1 0I/O write 1 0 1

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Arithmetic and Logical unit

It is an 8 bit registerIt is used for performing addition,

subtraction and logical operation.AND, OR, NOT, XOR, CMP are

some of the logical operation.

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Program Counter

It is a 16 bit registerIt is used to point out the address of

the next instruction which is to be executed

104Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode

Stack pointer

It is a 16 bit register It points the starting address of the stack .

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Register Array

B, C, D, E, H and L are general purpose register

All are 8 bit register If the are combined as BC, DE and HL

they can store 16 bit data

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Memory organization

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8085 Communication with Memory

Involves the following three steps1. Identify the memory location (with address)2. Generate Timing & Control signals3. Data transfer takes place

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Example: Memory Read Operation

1

2

3

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8085 Interfacing with Memory chips

8085Memory

Interface

Memory

Chip

Address

Data

Control

Address

Data

Control

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8085

MemoryInterface

Memory

ChipAD0-AD7

Control

A0 – A7

Data

74LS373

A8-A15 A8-A15

ALE

111


8085

MemoryInterface

Program

MemoryAD0-AD7

IO/M

A0 – A7

Data

74LS373

A8-A15 A8-A15

ALE

RDRD

CS

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I/O ports & Data transfer

concepts113

Interfacing I/O devices with 8085

8085

I/O Interface

I/O Devices

Memory Interface

Memory Devices

System Bus

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Techniques for I/O Interfacing

Memory-mapped I/O Peripheral-mapped I/O

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Memory-mapped I/O

8085 uses its 16-bit address bus to identify a memory location

Memory address space: 0000H to FFFFH 8085 needs to identify I/O devices also I/O devices can be interfaced using

addresses from memory space 8085 treats such an I/O device as a memory

location This is called Memory-mapped I/O

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Peripheral-mapped I/O

8085 has a separate 8-bit addressing scheme for I/O devices

I/O address space: 00H to FFH This is called Peripheral-mapped I/O or

I/O-mapped I/O

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8085 Communication with I/O devices

Involves the following three steps1. Identify the I/O device (with address)2. Generate Timing & Control signals3. Data transfer takes place

8085 communicates with a I/O device only if there is a Program Instruction to do so

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1.Identify the I/O device (with address)

1. Memory-mapped I/O (16-bit address)2. Peripheral-mapped I/O (8-bit address)

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2.Generate Timing & Control Signals

Memory-mapped I/O Reading Input: IO/M = 0, RD = 0 Write to Output: IO/M = 0, WR = 0

Peripheral-mapped I/O Reading Input: IO/M = 1, RD = 0 Write to Output: IO/M = 1, WR = 0

3. Data transfer takes place

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8085 Communication with I/O devices

Involves the following three steps Identify the I/O device (with address) Generate Timing & Control signals Data transfer takes place

8085 communicates with a I/O device only if there is a Program Instruction to do so

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Peripheral I/O Instructions

IN Instruction Inputs data from input device into the

accumulator It is a 2-byte instruction Format: IN 8-bit port address Example: IN 01H

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OUT Instruction Outputs the contents of accumulator to an

output device It is a 2-byte instruction Format: OUT 8-bit port address Example: OUT 02H

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----------Example Program----------

WAP to read a number from input port (port address 01H) and display it on ASCII display connected to output port (port address 02H)

IN 01H ;reads data value 03H (example)into ;accumulator, A = 03H

MVI B, 30H;loads register B with 30HADD B ;A = 33H, ASCII code for 3OUT 02H ;display 3 on ASCII display

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Memory-mapped I/O Instructions

I/O devices are identified by 16-bit addresses 8085 communicates with an I/O device as if it

were one of the memory locations Memory related instructions are used For e.g. LDA, STA LDA 8000H

Loads A with data read from input device with 16-bit address 8000H

STA 8001H Stores (Outputs) contents of A to output

device with 16-bit address 8001H125

----------Example Program----------

WAP to read a number from input port (port address 8000H) and display it on ASCII display connected to output port (port address 8001H)

LDA 8000H;reads data value 03H (example)into ;accumulator, A = 03H

MVI B, 30H;loads register B with 30HADD B ;A = 33H, ASCII code for 3STA 8001H;display 3 on ASCII display

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Timing Diagram of

8085127

Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle:The time required to execute an instruction .

Machine Cycle:The time required to access the memory or

input/output devices .

T-State:•The machine cycle and instruction cycle takes multiple clock periods.•A portion of an operation carried out in one system clock period is called as T-state.

128

Timing diagrams• The 8085 microprocessor has 7 basic machine

cycle. They are1. Op-code Fetch cycle(4T or 6T).2. Memory read cycle (3T)3. Memory write cycle(3T)4. I/O read cycle(3T)5. I/O write cycle(3T)6. Interrupt Acknowledge cycle(6T or 12T)7. Bus idle cycle

130

1.Opcode fetch cycle(4T or 6T)

132

OPCODE FETCH• The Opcode fetch cycle, fetches the instructions from memory

and delivers it to the instruction register of the microprocessor• Opcode fetch machine cycle consists of 4 T-states.

T1 State:During the T1 state, the contents of the program counter are

placed on the 16 bit address bus. The higher order 8 bits are transferred to address bus (A8-A15) and lower order 8 bits are transferred to multiplexed A/D (AD0-AD7) bus.

ALE (address latch enable) signal goes high. As soon as ALE goes high, the memory latches the AD0-AD7 bus. At the middle of the T state the ALE goes low

133

T2 State:During the beginning of this state, the RD’ signal goes low to enable memory. It is during this state, the selected memory location is placed on D0-D7 of the Address/Data multiplexed bus.

T3 State:In the previous state the Opcode is placed in D0-D7 of the A/D

bus. In this state of the cycle, the Opcode of the A/D bus is transferred to the instruction register of the microprocessor. Now the RD’ goes high after this action and thus disables the memory from A/D bus.

T4 State:In this state the Opcode which was fetched from the memory is decoded.

134

2. Memory read cycle (3T)

135

• These machine cycles have 3 T-states.

T1 state:• The higher order address bus (A8-A15) and lower order address

and data multiplexed (AD0-AD7) bus. ALE goes high so that the memory latches the (AD0-AD7) so that complete 16-bit address are available.The mp identifies the memory read machine cycle from the status signals IO/M’=0, S1=1, S0=0. This condition indicates the memory read cycle.T2 state:

• Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. RD’ goes LOWT3 State:

• The data which was loaded on the previous state is transferred to the microprocessor. In the middle of the T3 state RD’ goes high and disables the memory read operation. The data which was obtained from the memory is then decoded. 136

3. Memory write cycle (3T)

137

• These machine cycles have 3 T-states.

T1 state:• The higher order address bus (A8-A15) and lower order address

and data multiplexed (AD0-AD7) bus. ALE goes high so that the memory latches the (AD0-AD7) so that complete 16-bit address are available.The mp identifies the memory read machine cycle from the status signals IO/M’=0, S1=0, S0=1. This condition indicates the memory read cycle.T2 state:

• Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. WR’ goes LOWT3 State:

• In the middle of the T3 state WR’ goes high and disables the memory write operation. The data which was obtained from the memory is then decoded.

138

4.I/O read cycle(3T)

139

5.I/O write cycle(3T)

140

STA instructionex: STA 526A

141

It require 4 m/c cycles13 T states

1.opcode fetch(4T)2.memory read(3T)3.memory read(3T)

4.Memory write(3T)

142

Timing diagram for IN C0H

• Fetching the Opcode DBH from the memory 4125H.

• Read the port address C0H from 4126H.• Read the content of port C0H and send it to

the accumulator.• Let the content of port is 5EH.

144

It require 3 m/c cycles10 T states

opcode fetch(4T)memory read(3T)

I/O read(3T)


OUT instruction

Machines Cycles(10T):1.instruction fetch(4T)2.memory read (3T)

3.IO write (3T)

147

Timing diagram for MVI B, 43h

• Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)

• Read (move) the data 43H from memory 2001H. (memory read)

149

INR M

151

http://www.8085projects.info/images/Timing-Diagram-Pic10-pic45.png�

ADD M

152

8085 Interrupts

153

8085 Interrupts

8085 has five interrupt inputs1. TRAP2. RST7.53. RST 6.54. RST5.55. INTR

154

U7

8085

36

12

56

987

1011

29

33

39

35

1213141516171819

2122232425262728

303132

34

337438

40

20

RST-IN

X1X2

SIDTRAP

RST 5.5RST 6.5RST 7.5

INTRINTA

S0

S1

HOLD

READY

AD0AD1AD2AD3AD4AD5AD6AD7

A8A9

A10A11A12A13A14A15

ALEWRRD

IO/M

RST-OTCLKOSODHLDA

VCC

VSS

Interrupt pins of 8085 155

Types of Interrupts• Interrupts of 8085 can be classified as

– Maskable (RST 7.5, RST 6.5, RST 5.5, INTR)– Non-maskable (TRAP)

• An interrupt is a request for attention/service• 8085 may choose to service/not-service a

maskable interrupt • 8085 cannot ignore a service request from a

non-maskable interrupt

156

Interrupt process

• 8085 is executing its main program• an interrupt is generated by an external

device • 8085 pauses execution of main program• 8085 calls the Interrupt service routine• 8085 executes the Interrupt service routine• 8085 returns to execution of main program

(from where it was paused)157

Example: Blinking LED Display with Interrupt-based Display-Pattern change

8085Input

Switches LEDDisplay

RST 7.5

(Display-Pattern)

Interrupt Switch

Peripheral-mapped I/OInterrupt I/O

158

Interrupt Service Routine (ISR)

• It is a subroutine • 8085 calls an ISR in response to an

interrupt request by an external device• ISRs must be located in memory at pre-

determined addresses known as Interrupt Vectors

159

Interrupt Vector Table of 8085Interrupt Interrupt Vector

TRAP 0024HRST 7.5 003CHRST 6.5 0034HRST 5.5 002CH

Please Note: INTR is a non-vectored interrupt

160

Using Vectored Interrupts of 8085

• By default, all the vectored interrupts (except TRAP) of 8085 are disabled

• 8085 vectored interrupts are enabled with two instructions: EI and SIM

• EI (Enable Interrupt): 1-byte instruction that sets the Interrupt Enable flip-flop – It is internal to the processor & can be set or reset

by using software instructions

161

Using Vectored Interrupts

Step-1• Set Interrupt Enable flip-flop by using EI

instruction to enable the interrupt processStep-2• Use SIM (Set Interrupt Mask) instruction to

set mask for RST 7.5, 6.5 and 5.5 interrupts

162

SIM Instruction• It is a 1-byte instruction• Reads Accumulator contents• Enables/Disables interrupts accordingly• Used for three different functions

– Set mask for RST 7.5, 6.5, 5.5 interrupts– Additional control for RST 7.5– Implement serial I/O

163

Accumulator bit pattern for SIMD7 D6 D5 D4 D3 D2 D1 D0SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5

0 = Available, 1 = Masked

Mask Set Enable, 0 = bits 0-2 ignored

1 = mask is set

IF 1, RESET RST 7.5

If 1, bit 7 is output to serial output data latch

Serial Output Data, ignored if bit 6 = 0 164


8085 Interrupt process for Vectored-Interrupts

1. Enables Interrupt process by writing the EIinstruction in the main program

2. Set interrupt mask using SIM instruction3. 8085 monitors the status of all interrupt

lines during the execution of each instruction

165

4. When 8085 detects an interrupt signal from an external device

• It completes execution of current instruction

• Disables the Interrupt Enable flip-flop5. Executes a CALL to Interrupt Vector

location for that interrupt• Before the CALL is made, 8085 stores

return address in main program on stack

8085 Interrupt process for Vectored-Interrupts (Cont.)

166

6. 8085 executes the ISR written at the specified interrupt vector location

• ISR should include the EI instruction to Enable Interrupt again

• At the end of ISR, RET instruction transfers the program control back to the main program

8085 Interrupt process for Vectored-Interrupts (Cont.)


PROGRAMMING OF 8085 PROCESSOR

UNIT

2

168



UNIT 2 Syllabus• Instruction -format and addressing

modes • Assembly language format – Data

transfer, data manipulation& control instructions

• Programming: Loop structure with counting & Indexing – Look up table -Subroutine instructions - stack.

169

Addressing Modes of

8085170

Addressing Modes of 8085

• Format of a typical Assembly language instruction is given below-

[Label:] Mnemonic [Operands] [;comments]HLTMVI A, 20HMOV M, A ;Copy A to memory location whose

address is stored in register pair HLLOAD: LDA 2050H ;Load A with contents of memory

location with address 2050HREAD: IN 07H ;Read data from Input port with

address 07H171

• The various formats of specifying operands are called addressing modes

• Addressing modes of 80851. Register Addressing2. Immediate Addressing3. Memory Addressing4. Input/Output Addressing

172

1. Register Addressing

• Operands are one of the internal registers of 8085

• Examples-MOV A, BADD C

173

2. Immediate Addressing

• Value of the operand is given in the instruction itself

• Example-MVI A, 20HLXI H, 2050HADI 30HSUI 10H

174

3. Memory Addressing

• One of the operands is a memory location• Depending on how address of memory

location is specified, memory addressing is of two types– Direct addressing– Indirect addressing

175

3(a) Direct Addressing

• 16-bit Address of the memory location is specified in the instruction directly

• Examples-LDA 2050H ;load A with contents of memory

location with address 2050H

STA 3050H ;store A with contents of memory location with address 3050H

176

3(b) Indirect Addressing

• A memory pointer register is used to store the address of the memory location

• Example-MOV M, A ;copy register A to memory location

whose address is stored in register pair HL

30HA 20H

H50H

L30H2050H

177

4. Input/Output Addressing

• 8-bit address of the port is directly specified in the instruction

• Examples-IN 07HOUT 21H

178

Instruction set

179

Instruction set

An instruction is a binary pattern designed inside a microprocessor to perform a specific function.

A group of instruction together called as instruction set.

Group of instruction set is called as a program.

180

Classification of instruction set

According to word size or byte size it is classified into 3 types.

1 - byte instruction 2 - byte instruction and 3 - byte instruction

181

1. One-byte Instructions

• Includes Opcode and Operand in the same byte• Examples-

Opcode Operand Binary Code Hex CodeMOV C, A 0100 1111 4FHADD B 1000 0000 80HHLT 0111 0110 76H

182

2. Two-byte Instructions

• First byte specifies Operation Code• Second byte specifies Operand• Examples-

Opcode Operand Binary Code Hex CodeMVI A, 32H 0011 1110

0011 00103EH32H

MVI B, F2H 0000 01101111 0010

06HF2H

183

3. Three-byte Instructions

• First byte specifies Operation Code• Second & Third byte specifies Operand• Examples-

Opcode Operand Binary Code Hex CodeLXI H, 2050H 0010 0001

0101 00000010 0000

21H50H20H

LDA 3070H 0011 10100111 00000011 0000

3AH70H30H 184

Instruction Set of 8085 An instruction is a binary pattern designed inside a

microprocessor to perform a specific function.

The entire group of instructions that a microprocessor supports is called Instruction Set.

8085 has 246 instructions.

Each instruction is represented by an 8-bit binary value.

These 8-bits of binary value is called Op-Code or Instruction Byte.


Classification of Instruction Set

Data Transfer Instruction

Arithmetic Instructions

Logical Instructions

Branching Instructions

Control Instructions

186

1.Data Transfer Instructions These instructions move data between

registers, or between memory and registers.

These instructions copy data from source to destination(without changing the original data ).

187

Opcode Operand

MOV Rd, RsM, RsRd, M

This instruction copies the contents of the source register into the destination register. (contents of the source register are not altered)

If one of the operands is a memory location, its location is specified by the contents of the HL registers.

Example: MOV B, C or MOV B, M

MOV-Copy from source to destination

188

A 20 B 20

A FB 30 CD EH 20 L 50

A 20 B

BEFORE EXECUTION AFTER EXECUTIONMOV B,A

A FB 30 CD EH 20 L 50

A FB CD EH 20 L 50

A FB C 40D EH 20 L 50

MOV M,B

MOV C,M

40 40

30

189

Opcode Operand

MVI Rd, DataM, Data

The 8-bit data is stored in the destination register or memory.

If the operand is a memory location, its location is specified by the contents of the H-L registers.

Example: MVI B, 60H or MVI M, 40H

MVI-Move immediate 8-bit

190

A FB CD EH L

A FB 60 CD EH L

AFTER EXECUTIONBEFORE EXECUTION

MVI B,60H

40HL=20502051H

204FH 204F

2051H

MVI M,40H

BEFORE EXECUTION AFTER EXECUTION

HL=2050

191

LDA-Load accumulator

Opcode Operand

LDA 16-bit address

The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator.

The contents of the source are not altered.

Example: LDA 2000H

192

A

30

A 30

30


LDA 2000H

2000H 2000H

193

Opcode Operand

LDAX B/D Register Pair

The contents of the designated register pair point to a memory location.

This instruction copies the contents of that memory location into the accumulator.

The contents of either the register pair or the memory location are not altered.

Example: LDAX D

LDAX-Load accumulator indirect

194

A F

B C

D 20 E 30

A 80 F

B C

D 20 E 30

80 80


LDAX D2030H

2030H

195

Opcode Operand

LXI Reg. pair, 16-bit data

This instruction loads 16-bit data in the register pair.

Example: LXI H, 2030 H

LXI-Load register pair immediate


A F

B C

H L

A 80 F

B C

H 90 L 30

30

90

50


LXI H, 2030

2030H 9030H

2031H

M=50

197

Opcode Operand

LHLD 16-bit address

This instruction copies the contents of memory location pointed out by 16-bit address into register L.

It copies the contents of next memory location into register H.

Example: LHLD 2030 H

LHLD-Load H and L registers direct

198

A F

B C

H L

A 80 F

B C

H 85 L 00

00

85

60


LHLD 2030

2030H 8500H

M=60

199

Opcode Operand

STA 16-bit address

The contents of accumulator are copied into the memory location specified by the operand.

Example: STA 2000H

STA-Store accumulator direct

200

A 50 A 50

50


STA 2000H

2000H 2000H

201

Opcode Operand

STAX Reg. pair

The contents of accumulator are copied into the memory location specified by the contents of the register pair.

Example: STAX B

STAX-Store accumulator indirect

202

B 85 C 00

A=1AH


STAX B1A8500H

203

Opcode OperandSHLD 16-bit address

The contents of register L are stored into memory location specified by the 16-bit address.

The contents of register H are stored into the next memory location.

Example: SHLD 2550H

SHLD-Store H and L registers direct

204

D E

H 70 L 80


SHLD 8500

80

70

8500H

8501H

205

Opcode OperandXCHG None

The contents of register H are exchanged with the contents of register D.

The contents of register L are exchanged with the contents of register E.

Example: XCHG

XCHG-Exchange H and L with D and E

206

D 20 E 40

H 70 L 80

D 70 E 80

H 20 L 40


XCHG

207

Opcode Operand

SPHL None

This instruction loads the contents of H-L pair into SP.

Example: SPHL

SPHL-Copy H and L registers to the stack pointer

208

H 25 L 00SP

BEFORE EXECUTION

AFTER EXECUTION

SPHLSP 2500H 25 L 00

209

Opcode OperandXTHL None

The contents of L register are exchanged with the location pointed out by the contents of the SP.

The contents of H register are exchanged with the next location (SP + 1).

Example: XTHL

XTHL-Exchange H and L with top of stack

210

H 30 L 40

SP 2700

BEFORE EXECUTION

50

60H

60L

50

SP 2700 40

30

AFTER EXECUTION

XTHL

2700H

2701H

2702H

2700H

2701H

2702H

L=SPH=(SP+1)

211

Opcode Operand Description

PCHL None Load program counter with H-L contents

The contents of registers H and L are copied into the program counter (PC).

The contents of H are placed as the high-order byte and the contents of L as the low-order byte.

Example: PCHL


Opcode Operand

PUSH Reg. pair

The contents of register pair are copied onto stack.

SP is decremented and the contents of high-order registers (B, D, H, A) are copied into stack.

SP is again decremented and the contents of low-order registers (C, E, L, Flags) are copied into stack.

Example: PUSH B

PUSH-Push register pair onto stack

213

PUSH H

214

Opcode OperandPOP Reg. pair

The contents of top of stack are copied into register pair.

The contents of location pointed out by SP are copied to the low-order register (C, E, L, Flags).

SP is incremented and the contents of location are copied to the high-order register (B, D, H, A).

Example: POP H

POP- Pop stack to register pair

215

POP H

216

Opcode Operand

IN 8-bit port address

The contents of I/O port are copied into accumulator.

Example: IN 8C H

IN- Copy data to accumulator from a port with 8-bit address

217

10 A

10 A 10

BEFORE EXECUTION

AFTER EXECUTION

IN 80H

PORT 80H

PORT 80H 218

Opcode OperandOUT 8-bit port address

The contents of accumulator are copied into the I/O port.

Example: OUT 78H

OUT- Copy data from accumulator to a port with 8-bit address

219

10 A 40

40 A 40

BEFORE EXECUTION

AFTER EXECUTION

OUT 50H

PORT 50H

PORT 50H

220

2.Arithmetic Instructions These instructions perform the

operations like:

◦ Addition

◦ Subtract

◦ Increment

◦ Decrement


Addition Any 8-bit number, or the contents of register, or

the contents of memory location can be added to the contents of accumulator.

The result (sum) is stored in the accumulator.

No two other 8-bit registers can be added directly.

Example: The contents of register B cannot be added directly to the contents of register C.

222


ADD RM

Add register or memory to accumulator

The contents of register or memory are added to the contents of accumulator.

The result is stored in accumulator.

If the operand is memory location, its address is specified by H-L pair.

Example: ADD B or ADD M

ADD

223

B C 05D E

H L

B C 05

D E

H L


B C

D E

H 20 L 50

B C

D E

H 20 L 50


A 09A 04

ADD C A=A+C

ADD MA=A+M

10 10

2050 2050

A 04 A 14

04+05=09

04+10=14 224


ADC RM

Add register or memory to accumulator with carry

The contents of register or memory and Carry Flag (CY) are added to the contents of accumulator.



All flags are modified to reflect the result of the addition.

Example: ADC B or ADC M

ADC

225

B C 05D E

H L

A 50B C 20

D E

H L

A 56


ADC CA=A+C+CY

CY 01

CY 1A 06 A 37

H 20 L 50 H 20 L 50

ADC MA=A+M+CY


30 302050H 2050H

06+1+30=37

50+05+01=56

226


ADI 8-bit data Add immediate to accumulator

The 8-bit data is added to the contents of accumulator.



Example: ADI 45 H

ADI

227

A 03


ADI 05H

A=A+DATA(8)A 08

03+05=08

228


ACI 8-bit data Add immediate to accumulator with carry

The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator.



Example: ACI 45 H

ACI

229

CY 1

A 05


ACI 20H

A=A+DATA(8)+CY

A 26

05+20+1=26 230

Opcode Operand DescriptionDAD Reg. pair Add register pair to H-L pair

The 16-bit contents of the register pair are added to the contents of H-L pair.

The result is stored in H-L pair.

If the result is larger than 16 bits, then CY is set.

No other flags are changed.

Example: DAD B or DAD D

DAD

231

D 12 E 34

H 23 L 45

D 12 E 34

H 35 L 79


DAD D

DAD D HL=HL+DE DAD B HL=HL+BC

12342345 +-------3579

232

Subtraction Any 8-bit number, or the contents of register, or

the contents of memory location can be subtracted from the contents of accumulator.

The result is stored in the accumulator.

Subtraction is performed in 2’s complement form.

If the result is negative, it is stored in 2’s complement form.

No two other 8-bit registers can be subtracted directly.

233

Opcode Operand DescriptionSUB R

MSubtract register or memory from accumulator

The contents of the register or memory location are subtracted from the contents of the accumulator.



All flags are modified to reflect the result of subtraction.

Example: SUB B or SUB M

SUB

234

B C 04D E

H L

B C 04

D E

H L


B C

D E

H 20 L 50

B C

D E

H 20 L 50


A 05A 09

SUB C A=A-C

SUB MA=A-M

10 10

2050 2050

A 14 A 04

09-04=05

14-10=04 235

Opcode Operand DescriptionSBB R

MSubtract register or memory from accumulator with borrow

The contents of the register or memory location and Borrow Flag (i.e. CY)are subtracted from the contents of the accumulator.




Example: SBB B or SBB M

SBB

236

B C 05D E

H L

A 08B C 05

D E

H L

A 02


SBB CA=A-C-CY

CY 01

CY 1A 06 A 03

H 20 L 50 H 20 L 50

SBB MA=A-M-CY


02 022050H 2050H

08-05-01=02

06-02-1=03237


SUI 8-bit data Subtract immediate from accumulator

The 8-bit data is subtracted from the contents of the accumulator.



Example: SUI 05H

SUI

238

A 08


SUI 05H

A=A-DATA(8)A 03

08-05=03239


SBI 8-bit data Subtract immediate from accumulator with borrow

The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the contents of the accumulator.



Example: SBI 45 H

SBI

240

CY 1

A 25


SBI 20H

A=A-DATA(8)-CY

A 04

25-20-01=04241

Increment / Decrement The 8-bit contents of a register or a

memory location can be incremented or decremented by 1.

The 16-bit contents of a register pair can be incremented or decremented by 1.

Increment or decrement can be performed on any register or a memory location.


Opcode Operand DescriptionINR R

MIncrement register or memory by 1

The contents of register or memory location are incremented by 1.

The result is stored in the same place.

If the operand is a memory location, its address is specified by the contents of H-L pair.

Example: INR B or INR M

INR

243

B 10 C

D E

H L

A

B 11 C

D E

H L

A


H20

L50

H20

L5010 112050H 2050H


INR MM=M+1

B 10 C

D E

H L

A

BEFORE EXECUTION

INR BR=R+1

10+1=11

10+1=11 244

Opcode Operand DescriptionINX R Increment register pair by 1

The contents of register pair are incremented by 1.


Example: INX H or INX B or INX D

INX

245

B C

D E

H 10 L 20

B C

D E

H 10 L 21


SPSP

INX HRP=RP+1

1020+1=1021246

Opcode Operand DescriptionDCR R

MDecrement register or memory by 1

The contents of register or memory location are decremented by 1.


If the operand is a memory location, its address is specified by the contents of H-L pa ir.

Example: DCR B or DCR M

DCR

247

B C

D E 19

H L

A

AFTER EXECUTION

B C

D E 20H L

A

BEFORE EXECUTION

DCR ER=R-1

H20

L50

H20

L5021 202050H


DCR MM=M-1

2050H

21-1=20

20-1=19

248


DCX R Decrement register pair by 1

The contents of register pair are decremented by 1.


Example: DCX H or DCX B or DCX D

DCX

249

B C

D E

H 10 L 21

B C

D E

H 10 L 20


SPSP

DCX HRP=RP-1

250

3.Logical Instructions These instructions perform logical operations on

data stored in registers, memory and status flags.

The logical operations are:◦ AND

◦ OR

◦ XOR

◦ Rotate

◦ Compare

◦ Complement

251

AND, OR, XOR Any 8-bit data, or the contents of register,

or memory location can logically have

◦ AND operation

◦ OR operation

◦ XOR operation

with the contents of accumulator.


252


ANA RM

Logical AND register or memory with accumulator

The contents of the accumulator are logically ANDed with the contents of register or memory.

The result is placed in the accumulator.


S, Z, P are modified to reflect the result of the operation.

CY is reset and AC is set.

Example: ANA B or ANA M.

253

B 10 C

D E

H L

A

B 0F C

D E

H L

A 0A

AFTER EXECUTION

ANA BA=A and R

B 0F C

D E

H L

A AA

BEFORE EXECUTION

CY AC CY 0 AC 1


CY AC CY 0 AC 1

A 11A 55

H 20 L 50 H 20 L 50

B3 B32050H

ANA MA=A and M

2050H

1010 1010=AAH

0000 1111=0FH

0000 1010=0AH

0101 0101=55H1011 0011=B3H

0001 0001=11H

254

Opcode Operand DescriptionANI 8-bit data Logical AND immediate with

accumulator

The contents of the accumulator are logically ANDed with the 8-bit data.


S, Z, P are modified to reflect the result.

CY is reset, AC is set.

Example: ANI 86H.

255

CY AC

A B3


CY0

AC 1

A 33

ANI 3FHA=A and DATA(8)

1011 0011=B3H

0011 1111=3FH

0011 0011=33H

256


ORA RM

Logical OR register or memory with accumulator

The contents of the accumulator are logically ORed with the contents of the register or memory.




CY and AC are reset.

Example: ORA B or ORA M.257


CY AC

ORA BA=A or R

1010 1010=AAH0001 0010=12H

1011 1010=BAH

B 12 C

D E

H L

A AA

B 12 C

D E

H L

A BA

CY 0 AC 0

258


CY AC

ORA MA=A or M

0101 0101=55H1011 0011=B3H

1111 0111=F7H

H 20 L 50

A 55 A F7

CY0

AC 0

H 20 L 50

B3 B32050H 2050H

259


ORI 8-bit data Logical OR immediate with accumulator

The contents of the accumulator are logically ORed with the 8-bit data.




Example: ORI 86H.

260

CY AC

A B3


CY0

AC0

A BB

ORI 08H

A=A or DATA(8)

1011 0011=B3H0000 1000=08H

1011 1011=BBH

261


XRA RM

Logical XOR register or memory with accumulator

The contents of the accumulator are XORed with the contents of the register or memory.



S, Z, P are modified to reflect the result of the operation.


Example: XRA B or XRA M.

262

B 10 C

D E

H L

A

B C 2D

D E

H L

A 87

AFTER EXECUTION

XRA CA=A xor R

B C 2D

D E

H L

A AA

BEFORE EXECUTION

CY AC CY 0 AC 0

1010 1010=AAH

0010 1101=2DH

1000 0111=87H


H 20 L 50

A 55

AFTER EXECUTION

XRA MA=A xor M

BEFORE EXECUTION

CY AC CY 0 AC 0

0101 0101=55H1011 0011=B3H

1110 0110=E6H

H 20 L 50

A E6B3 B32050H 2050H

264


XRI 8-bit data XOR immediate with accumulator

The contents of the accumulator are XORed with the 8-bit data.




Example: XRI 86H.

265

CY AC

A B3


CY0

AC0

A 8A

XRI 39H

A=A xor DATA(8)

1011 0011=B3H0011 1001=39H

1000 1010=8AH

266

Compare Any 8-bit data, or the contents of register,

or memory location can be compares for:

◦ Equality

◦ Greater Than

◦ Less Than

with the contents of accumulator.

The result is reflected in status flags.

267

Opcode Operand DescriptionCMP R

MCompare register or memory with accumulator

The contents of the operand (register or memory) are compared with the contents of the accumulator.

Both contents are preserved .

268

B 10 C

D E

H L

A

B C

D 20 E

H L

A 10

AFTER EXECUTION

CMP DA-R

B C

D 20 E

H L

A 10

BEFORE EXECUTION

CY Z CY 01 Z 0


CY Z CY 0 ZF 1

A B8A B8

H 20 L 50 H 20 L 50

B8 B82050H CMP M

A-M

2050H

A>R: CY=0A=R: ZF=1A<R: CY=1

A>M: CY=0A=M: ZF=1A<M: CY=1

10<20:CY=01

B8=B8 :ZF=01269


CPI 8-bit data Compare immediate with accumulator

The 8-bit data is compared with the contents of accumulator.

The values being compared remain unchanged.

270

CY Z

A BA


CY0

AC0

A BA

CPI 30HA-DATA

A>DATA: CY=0A=DATA: ZF=1A<DATA: CY=1

BA>30 : CY=00 271

Rotate Each bit in the accumulator can be shifted

either left or right to the next position.

272


RLC None Rotate accumulator left

Each binary bit of the accumulator is rotated left by one position.

Bit D7 is placed in the position of D0 as well as in the Carry flag.

CY is modified according to bit D7.

S, Z, P, AC are not affected.

Example: RLC.

273

B7 B6 B5 B4 B3 B2 B1 B0CY

B6 B5 B4 B3 B2 B1 B0 B7B7

AFTER EXECUTION

BEFORE EXECUTION

274


RRC None Rotate accumulator right

Each binary bit of the accumulator is rotated right by one position.

Bit D0 is placed in the position of D7 as well as in the Carry flag.



Example: RRC.

275

B7 B6 B5 B4 B3 B2 B1 B0 CY

B0 B7 B6 B5 B4 B3 B2 B1 B0

AFTER EXECUTION

BEFORE EXECUTION

276


RAL None Rotate accumulator left through carry

Each binary bit of the accumulator is rotated left by one position through the Carry flag.

Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0.



Example: RAL.

277

B7 B6 B5 B4 B3 B2 B1 B0CY

B6 B5 B4 B3 B2 B1 B0 CYB7

AFTER EXECUTION

BEFORE EXECUTION

278


RAR None Rotate accumulator right through carry

Each binary bit of the accumulator is rotated right by one position through the Carry flag.

Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7.



Example: RAR.


B7 B6 B5 B4 B3 B2 B1 B0 CY

CY B7 B6 B5 B4 B3 B2 B1 B0

AFTER EXECUTION

BEFORE EXECUTION

280

Complement The contents of accumulator can be

complemented.

Each 0 is replaced by 1 and each 1 is replaced by 0.

281


CMA None Complement accumulator

The contents of the accumulator are complemented.

No flags are affected.

Example: CMA. A=A’

A 00 A FF


282


CMC None Complement carry

The Carry flag is complemented.

No other flags are affected.

Example: CMC => c=c’


C 00 C FF283


STC None Set carry

The Carry flag is set to 1.

No other flags are affected.

Example: STC CF=1

S-set (1) C-clear (0)284

4.Branching Instructions

The branch group instructions allows the microprocessor to change the sequence of program either conditionally or under certain test conditions. The group includes,

(1) Jump instructions, (2) Call and Return instructions, (3) Restart instructions,

285


JMP 16-bit address

Jump unconditionally

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.

Example: JMP 2034 H.

286


Jx 16-bit address

Jump conditionally

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW.

Example: JZ 2034 H.

287

Jump ConditionallyOpcode Description Status Flags

JC Jump if Carry CY = 1

JNC Jump if No Carry CY = 0

JZ Jump if Zero Z = 1

JNZ Jump if No Zero Z = 0

JPE Jump if Parity Even P = 1

JPO Jump if Parity Odd P = 0

A-Above , B-Below , C-Carry , Z-Zero , P-Parity

288


CALL 16-bit address

Call unconditionally

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.

Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack.

Example: CALL 2034 H.

289

Call ConditionallyOpcode Description Status Flags

CC Call if Carry CY = 1

CNC Call if No Carry CY = 0

CP Call if Positive S = 0

CM Call if Minus S = 1

CZ Call if Zero Z = 1

CNZ Call if No Zero Z = 0

CPE Call if Parity Even P = 1

CPO Call if Parity Odd P = 0

290


RET None Return unconditionally

The program sequence is transferred from the subroutine to the calling program.

The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address.

Example: RET.

291

Return ConditionallyOpcode Description Status Flags

RC Return if Carry CY = 1

RNC Return if No Carry CY = 0

RP Return if Positive S = 0

RM Return if Minus S = 1

RZ Return if Zero Z = 1

RNZ Return if No Zero Z = 0

RPE Return if Parity Even P = 1

RPO Return if Parity Odd P = 0

292


RST 0 – 7 Restart (Software Interrupts)

The RST instruction jumps the control to one of eight memory locations depending upon the number.

These are used as software instructions in a program to transfer program execution to one of the eight locations.

Example: RST 1 or RST 2 ….

293

Instruction Code Vector Address

RST 0 0*8=0000H

RST 1 1*8=0008H

RST 2 2*8=0010H

RST 3 3*8=0018H

RST 4 4*8=0020H

RST 5 5*8=0028H

RST 6 6*8=0030H

RST 7 7*8=0038H

294

5. Control Instructions The control instructions control the

operation of microprocessor.

295


NOP None No operation

No operation is performed.

The instruction is fetched and decoded but no operation is executed.

Example: NOP

296


HLT None Halt

The CPU finishes executing the current instruction and halts any further execution.

An interrupt or reset is necessary to exit from the halt state.

Example: HLT

297


DI None Disable interrupt

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled.


Example: DI



EI None Enable interrupt

The interrupt enable flip-flop is set and all interrupts are enabled.


This instruction is necessary to re-enable the interrupts (except TRAP).

Example: EI

299


RIM None Read Interrupt Mask

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit.

The instruction loads eight bits in the accumulator with the following interpretations.

Example: RIM

300

RIM Instruction

301


SIM None Set Interrupt Mask

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output.

The instruction interprets the accumulator contents as follows.

Example: SIM

302

SIM Instruction

303

8085 Assembly Language

Programming

304

Example Data Transfer (Copy) Operations / Instructions

1. Load a 8-bit number 4F in register B

2. Copy from Register B to Register A

3. Load a 16-bit number 2050 in Register pair HL

4. Copy from Register B to Memory Address 2050

5. Copy between Input / Output Port and Accumulator

MVI B, 4FH

MOV A,B

LXI H, 2050H

MOV M,B

OUT 01HIN 07H

305

Example ArithmeticOperations / Instructions

1. Add a 8-bit number 32H to Accumulator

2. Add contents of Register B to Accumulator

3. Subtract a 8-bit number 32H from Accumulator

4. Subtract contents of Register C from Accumulator

5. Increment the contents of Register D by 1

6. Decrement the contents of Register E by 1

ADI 32H

ADD B

SUI 32H

SUB C

INR D

DCR E

306

Example Logical & Bit ManipulationOperations / Instructions

1. Logically AND Register Hwith Accumulator

2. Logically OR Register L with Accumulator

3. Logically XOR Register Bwith Accumulator

4. Compare contents of Register C with Accumulator

5. Complement Accumulator6. Rotate Accumulator Left

ANA H

ORA L

XRA B

CMP C

CMARAL

307

Example BranchingOperations / Instructions

1. Jump to a 16-bit Address 2080H if Carry flag is SET

2. Unconditional Jump3. Call a subroutine with its 16-bit

Address 4. Return back from the Call5. Call a subroutine with its 16-bit

Address if Carry flag is RESET6. Return if Zero flag is SET

JC 2080H

JMP 2050HCALL 3050H

RETCNC 3050H

RZ

308

Writing a Assembly Language Program

• Steps to write a program– Analyze the problem– Develop program Logic– Write an Algorithm– Make a Flowchart– Write program Instructions using

Assembly language of 8085

309

Program 8085 in Assembly language to add two 8-bit numbers and store 8-bit result in register C.

1. Analyze the problem– Addition of two 8-bit numbers to be done

2. Program Logic– Add two numbers– Store result in register C– Example

10011001 (99H) A+00111001 (39H) D11010010 (D2H) C

310

1. Get two numbers

2. Add them

3. Store result

4. Stop

• Load 1st no. in register D• Load 2nd no. in register E

3. Algorithm Translation to 8085 operations

• Copy register D to A• Add register E to A

• Copy A to register C

• Stop processing

311

4. Make a FlowchartStart

Load Registers D, E

Copy D to A

Add A and E

Copy A to C

Stop

• Load 1st no. in register D• Load 2nd no. in register E

• Copy register D to A• Add register E to A


• Stop processing

312

5. Assembly Language Program1. Get two numbers

2. Add them

3. Store result

4. Stop

a) Load 1st no. in register Db) Load 2nd no. in register E

a) Copy register D to Ab) Add register E to A

a) Copy A to register C

a) Stop processing

MVI D, 2HMVI E, 3H

MOV A, DADD E

MOV C, A

HLT313

Program 8085 in Assembly language to add two 8-bit numbers. Result can be more than 8-bits.

1. Analyze the problem– Result of addition of two 8-bit numbers can

be 9-bit– Example

10011001 (99H) A+10011001 (99H) B100110010 (132H)

– The 9th bit in the result is called CARRY bit.

314

0

• How 8085 does it?– Adds register A and B– Stores 8-bit result in A– SETS carry flag (CY) to indicate carry bit

10011001

10011001

A

B+

99H

99H

10011001 A1

CY

00110010 99H32H

315

• Storing result in Register memory

10011001

A32H1

CY

Register CRegister B

Step-1 Copy A to CStep-2

a) Clear register Bb) Increment B by 1

316

2. Program Logic

1. Add two numbers2. Copy 8-bit result in A to C3. If CARRY is generated

– Handle it4. Result is in register pair BC

317

1. Load two numbers in registers D, E

2. Add them

3. Store 8 bit result in C4. Check CARRY flag5. If CARRY flag is SET

• Store CARRY in register B

6. Stop

• Load registers D, E

3. Algorithm Translation to 8085 operations

• Copy register D to A• Add register E to A• Copy A to register C

• Stop processing

• Use Conditional Jump instructions

• Clear register B• Increment B


318

4. Make a FlowchartStart

Load Registers D, E

Copy D to A

Add A and E

Copy A to CStop

If CARRY

NOT SETClear B

Increment B

False

True


5. Assembly Language ProgramMVI D, 2HMVI E, 3HMOV A, DADD EMOV C, A

HLT

• Load registers D, E

• Copy register D to A• Add register E to A• Copy A to register C

• Stop processing

• Use Conditional Jump instructions

• Clear register B• Increment B


JNC END

MVI B, 0HINR B

END:320

8 bit ADDITION

321

8 bit Subtraction

323

8 bit Multiplication

325

8 bit Division

327

Ascending & Descending order

329

Ascending Order

330

Descending order

331

Smallest Number in an Array

332

Largest Number in an Array

334

BasicsMicroprocessor &Microcontroller

336

What is Microcontroller?

Micro Controller

337

Very Small A mechanism that controls the operation of a machine


CPU for Computers No RAM, ROM, I/O on CPU chip itself Example: Intel's x86, Motorola’s 680x0

338


A smaller computer On-chip RAM, ROM, I/O ports... Example: Motorola’s 6811, Intel’s 8051, Zilog’s

Z8 and PIC

339

Microprocessor

CPU is stand-alone, RAM, ROM, I/O, timer are separate

Designer can decide on the amount of ROM, RAM and I/O ports.

Expansive

General-purpose

Microcontroller

CPU, RAM, ROM, I/O and timer are all on a single chip

Fix amount of on-chip ROM, RAM, I/O ports

For applications in which cost, power and space are critical

Not Expansive

Single-purpose

341

Home Appliances, intercom, telephones, security systems, garage door

openers, answering machines, fax machines, home computers,TVs, cable TV tuner, VCR, camcorder, remote controls, videogames, cellular phones, musical instruments, sewing machines,lighting control, paging, camera, pinball machines, toys, exerciseequipment etc.

Office Telephones, computers, security systems, fax machines,

microwave, copier, laser printer, color printer, paging etc.

Auto Trip computer, engine control, air bag, ABS, instrumentation,

security system, transmission control, entertainment, climatecontrol, cellular phone, keyless entry

342

344




UNIT 3 Syllabus

• Architecture of 8051• Special Function Registers(SFRs)• I/O Pins Ports and Circuits {Pin Diagram}• Instruction set• Addressing modes • Assembly language programming

345

The 8051 is a subset of the 8052 The 8031 is a ROM-less 8051

Add external ROM to it You lose two ports, and leave only 2 ports for I/O

operations

346

Intel introduced 8051, developed in the year1981.

The 8051 is an 8-bit controller. D0-D7 DATA LINES A0-A15 ADDRESS LINES

348


InterruptControl

8bitCPU

4KROM

256 BRAM

OSCBus

Control 4 I/O Ports SerialPort

Timer 1

Timer 0

General Block Diagram of 8051

TXD RXDP0 P1 P2 P3

349

External Interrupts

CounterInputs

8 bit CPU On-chip clock oscillator 4K bytes of on-chip Program Memory-ROM 128 bytes of on-chip Data RAM 64KB Program Memory address space 64KB Data Memory address space 32 bidirectional I/0 lines (Port 0,1,2,3)

Port 0 { P0.0-P0.7 } – 8 pinsPort 1 { P1.0-P1.7 } – 8 pinsPort 2 { P2.0-P2.7 } – 8 pinsPort 3 { P3.0-P3.7 } – 8 pins

350

Two 16-bit timer/counters(Timer 1,Timer 0) One serial port

UART(Universal Asynchronous Receiver Transmitter) 6-source interrupt structure

1. External interrupt INT02. Timer interrupt T03. External interrupt INT14. Timer interrupt T15. Serial communication interrupt6. Timer Interrupt T2

4 Register Banks (Bank 0, Bank 1, Bank 2, Bank 3) each bank has R0-R7 registers

351

Pin Description of the 8051

352

EA/VPP

• EA, “external access’’

• EA = 0, 8051 microcontroller access fromexternal program memory (ROM) only.

• EA = 1, then it access internal and externalprogram memories (ROMS).


I/O Port Pins

• The four 8-bit I/O ports

Port 0 { P0.0-P0.7 } – 8 pinsPort 1 { P1.0-P1.7 } – 8 pinsPort 2 { P2.0-P2.7 } – 8 pinsPort 3 { P3.0-P3.7 } – 8 pins

355

Port 3

• Port 3 can be used as input or output.

• Port 3 has the additional function ofproviding some extremely importantsignals

356

Pin Description SummaryPIN TYPE NAME AND FUNCTION

Vss I Ground: 0 V reference.

Vcc I Power Supply + 5V.

P0.0 - P0.7I/O Port 0: Port 0 is also the multiplexed low-order address and

data bus during accesses to external program and datamemory.

P1.0 - P1.7I/O Port 1: Port 1 is an 8-bit bi-directional simple I/O port.

P2.0 - P2.7

I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits thehigh order address byte

P3.0 - P3.7I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also

serves special features as explained.357

Pin Description SummaryPIN TYPE NAME AND FUNCTION

RST I Reset: resets the device.

ALE O Address Latch Enable:When ALE=0, it provides data D0-D7When ALE=1, it has address A0-A7

PSEN* O Program Store Enable:For External Code Memory, PSEN = 0For External Data Memory, PSEN = 1

EA*/VPP I External Access Enable/Programming Supply Voltage:EA = 0, 8051 microcontroller access from externalprogram memory (ROM) only.

EA = 1, then it access internal and external programmemories (ROMS).

358

Architecture of 8051

microcontroller

359

Program Counter(PC) : The program counter always points to the address of the next instruction to be executed.Stack Pointer Register (SP) : It is an 8-bit register which stores the address of the stack top.ALU: perform arithmetic & logical operations

Flags : Carry(C),Auxiliary Carry(AC), Overflow(O) & Parity(P)

362


Timing & Control: Timing and control unit synchronises all microcontroller operations with clock & generates control signals.

DPTR: (Data Pointer) - 16 bit DPH-Data Pointer High – 8 bit DPL-Data Pointer Low – 8 bit

DPTR Register is usually used for storing data and intermediate results.

363


8051 Program Memory,

Data Memory structure

364

8051 Memory Structure

Exte

rnal

EXT INT 128

SFR

Exte

rnal

Program Memory Data Memory

64K 64K

EA = 0 EA = 1

4K

60K

365

Special Function

Registers [SFR]366

• A Register (Accumulator)• B Register• Program Status Word (PSW) Register• Data Pointer Register (DPTR)

– DPH (Data Pointer High) , DPL(Data Pointer Low)• Stack Pointer (SP) Register• P0, P1, P2, P3 - Input/output port Registers• Timer T0 - TH0 & TL0• Timer T1 – TH1 & TL1• Timer Control (TCON) Register• Serial Port Control (SCON) Register• Serial Buffer Control (SBUF) Register• IP Register (Interrupt Priority)• IE Register (Interrupt Enable)

367

8051 Register Bank Structure4 MEMORY BANKS

Bank 0

R0 R1 R2 R3 R4 R5 R6 R7Bank 3



R0 R1 R2 R3 R4 R5 R6 R7

368

Program Status Word [PSW]

C AC F0 RS1 RS0 OV F1 P

Register Bank Select

Carry

Auxiliary Carry

User Flag 0

Parity

User Flag 1

Overflow

369

00-Bank 001-Bank 110-Bank 211-Bank 3

Data Pointer Register (DPTR)It consists of two separate registers: DPH (Data Pointer High) &DPL (Data Pointer Low).

370

Stack Pointer (SP) Register

371

P0, P1, P2, P3 – Input / Output Registers

8 bit

8 bit

8 bit

8 bit

8 bit

8051 Interrupts


INTERRUPTS

• An interrupt is an external or internal event thatinterrupts the microcontroller to inform it that a deviceneeds its service

• A single microcontroller can serve several devices by twoways:

1. Interrupt2. Polling

373

Interrupt

– Upon receiving an interrupt signal, themicrocontroller interrupts whatever it is doingand serves the device.

– The program which is associated with theinterrupt is called the interrupt service routine(ISR) .


Steps in Executing an Interrupt1. It finishes the instruction it is executing and saves the address of

the next instruction (PC) on the stack.

2. It also saves the current status of all the interrupts internally (i.e:not on the stack).

3. It jumps to a fixed location in memory, called the interruptvector table, that holds the address of the ISR.

4. The microcontroller gets the address of the ISR from theinterrupt vector table and jumps to it.

5. It starts to execute the interrupt service subroutine until itreaches the last instruction of the subroutine which is RETI(return from interrupt).

6. Upon executing the RETI instruction, the microcontroller returnsto the place where it was interrupted.

375

Steps in executing an interrupt• Finish current instruction and saves the PC on stack.

• Jumps to a fixed location in memory depend on type of interrupt

• Starts to execute the interrupt service routine until RETI (return from interrupt)

• Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack

Interrupt Sources• Original 8051 has 6 sources of interrupts

– Reset (RST)– Timer 0 overflow (TF0)– Timer 1 overflow (TF1)– External Interrupt 0 (INT0)– External Interrupt 1 (INT1)– Serial Port events (RI+TI)

{Reception/Transmission of Serial Character}

8051 Interrupt Vectors

378

8051 Interrupt related Registers• The various registers associated with the use of

interrupts are:

– TCON - Edge and Type bits for External Interrupts 0/1

– SCON - RI and TI interrupt flags for RS232 {SERIALCOMMUNICATION}

– IE - interrupt Enable

– IP - Interrupts priority

379

Enabling and Disabling an Interrupt

• The register called IE (interrupt enable) that isresponsible for enabling (unmasking) and disabling(masking) the interrupts.

380

Interrupt Enable (IE) Register

• EA : Global enable/disable.

• --- : Reserved for additional interrupt hardware.

• ES : Enable Serial port interrupt.

• ET1 : Enable Timer 1 control bit.

• EX1 : Enable External 1 interrupt.

• ET0 : Enable Timer 0 control bit.

• EX0 : Enable External 0 interrupt.

MOV IE,#08hor

SETB ET1

--

381

Interrupt Priority

382

Interrupt Priority (IP) Register

PS PT1 PX1 PT0 PX0Reserved

Serial Port

Timer 1 Pin

INT 1 Pin Timer 0 Pin

INT 0 Pin

Priority bit=1 assigns high priorityPriority bit=0 assigns low priority

383

Comparison to Programming

concepts with 8085.

385

Assembly language programs : 8085 & 8051

NOTE: Refer Unit 2 & Unit 5

UNIT-4Peripheral interfacing

386




UNIT 4 Syllabus Introduction: Memory Interfacing & I/O interfacing• 8255 PPI {Parallel communication interface}• 8259 {Programmable Interrupt controller }• 8253/8254 Timer – {Timer {or counter}}• 8237/8257 {DMA controller}• 8251 USART {Serial communication interface}• 8279 {Keyboard /display controller}• A/D and D/A Interface {ADC 0800/0809,DAC 0800}

[Interfacing with 8085 & 8051]

Introduction to peripheral interfacing

388

Data Transfers Synchronous ----- Usually occur when

peripherals are located within the same computer as the CPU. Close proximity allows all state bits change at same time on a common clock.

Asynchronous ----- Do not require that the source and destination use the same system clock.

389

MEMORY DEVICES I/O DEVICESPresented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

390

interface memory (RAM, ROM, EPROM'...) or I/O devices to 8086 microprocessor. Several memory chips or I/O devices can connected to a microprocessor. An address decoding circuit is used to select the required I/O device or a memory chip.

391

IO mapped IO V/s Memory Mapped IO

Memory Mapped IO

IO is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 216=64k

locations. Less memory is available.

IO Mapped IO

IO is treated IO. 8- bit addressing. Less Decoder

Hardware. Can address 28=256

locations. Whole memory address

space is available.

392

Memory Mapped IO

• Memory Instructions are used.

• Memory control signals are used.

• Arithmetic and logic operations can be performed on data.

• Data transfer b/w register and IO.

IO Mapped IO

• Special Instructions are used like IN, OUT.

• Special control signals are used.

• Arithmetic and logic operations can not be performed on data.

• Data transfer b/w accumulator and IO.

393

Parallel communication interface

INTEL 8255

Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode

394

8255 PPI• The 8255 chip is also called as Programmable

Peripheral Interface. • The Intel’s 8255 is designed for use with Intel’s

8-bit, 16-bit and higher capability microprocessors

• The 8255 is a 40 pin integrated circuit (IC), designed to perform a variety of interface functions in a computer environment.

• It is flexible and economical.

395

PIN DIAGRAM OF 8255396

Signals of 8085397

8255 PIO/PPI It has 24 input/output lines which may be

individually programmed. 2 groups of I/O pins are named as

Group A (Port-A & Port C Upper)Group B (Port-B & Port C Lower)

3 ports(each port has 8 bit)Port A lines are identified by symbols PA0-PA7

Port B lines are identified by symbols PB0-PB7

Port C lines are identified by PC0-PC7 , PC3-PC0ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)

398

D0 - D7: data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines.

CS (Chip Select). If this line is a logical 0, the microprocessor can read and write to the 8255.

RESET : The 8255 is placed into its reset state if this input line is a logical 1

399

• RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255.

• WR : This is an input line driven by the microprocessor. A low on this line indicates write operation.

• A1-A0 : These are the address input lines and are driven by the microprocessor.

400


Control Logic CS signal is the master Chip Select A0 and A1 specify one of the two I/O Ports

CS A1 A0 Selected0 0 0 Port A0 0 1 Port B0 1 0 Port C0 1 1 Control

Register1 X X 8255 is not

selected

401

Block Diagram of 8255A 402

Block Diagram of 8255 (Architecture)

It has a 40 pins of 4 parts.1. Data bus buffer2. Read/Write control logic3. Group A and Group B controls4. Port A, B and C

403

1. Data bus buffer This is a tristate bidirectional buffer used

to interface the 8255 to system data bus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU.

404

2. Read/Write control logic This unit accepts control signals ( RD, WR ) and

also inputs from address bus and issues commands to individual group of control blocks ( Group A, Group B).

It has the following pins.

CS , RD , WR , RESET , A1 , A0

405

3. Group A and Group B controls• These block receive control from the CPU

and issues commands to their respective ports.Group A - PA and PCU ( PC7 –PC4)Group B – PB and PCL ( PC3 –PC0)

a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes – mode 0, mode 1, mode 2.

406


b) Port B: It can be programmed in mode 0, mode1

c) Port C : It can be programmed in mode 0

407

Modes of Operation of 8255

Bit Set/Reset(BSR) Mode Set/Reset bits in Port C

I/O Mode Mode 0 (Simple input/output) Mode 1 (Handshake mode) Mode 2 (Bidirectional Data Transfer)

409

1. BSR Mode410

B3 B2 B1 Bit/pin of port C selected

0 0 0 PC0

0 0 1 PC1

0 1 0 PC2

0 1 1 PC3

1 0 0 PC4

1 0 1 PC5

1 1 0 PC6

1 1 1 PC7

Concerned only with the 8-bits of Port C.Set or Reset by control wordPorts A and B are not affected

411

a) Mode 0 (Simple Input or Output):

• Ports A and B are used as Simple I/O Ports

• Port C as two 4-bit ports

• Features– Outputs are latched– Inputs are not latched– Ports do not have handshake or

interrupt capability

2. I/O MODE 412

b) Mode 1: (Input or Output with Handshake)

• Handshake signals are exchanged between MPU & Peripherals

• Features– Ports A and B are used as Simple I/O Ports– Each port uses 3 lines from Port C as

handshake signals– Input & Output data are latched– interrupt logic supported

414

c) Mode 2: Bidirectional Data Transfer

• Used primarily in applications such as data transfer between two computers

• Features– Ports A can be configured as the bidirectional

Port– Port B in Mode 0 or Mode 1.– Port A uses 5 Signals from Port C as handshake

signals for data transfer– Remaining 3 Signals from Port C Used as –

Simple I/O or handshake for Port B

415

Find control word(1) Port A: output with handshake (2) Port B: input with handshake (3) Port CL: output (4)Port CU: input

Solution:

1 0 1 0 1 1 1 0 = AEH

416


Port A: Output, Port B: Output, Port CU: Output, Port CL: Output

Solution:

1 0 0 0 0 0 0 0 = 80H

The control word register for the above ports of Intel 8255 is 80H.

417

Port A: Input, Port B: Input, Port CU: Input, Port CL: Input

Solution:

1 0 0 1 1 0 1 1 = 9BH

The control word register for the above ports of intel 8255 is 9BH.

418

INTERRUPT CONTROLLER

419

1. This IC is designed to simplify the implementation of the interrupt interface in the 8088

and 8086 based microcomputer systems.

2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.4. The operation of the PIC is programmable under software control (Programmable)and it

can be configured for a wide variety of applications.

5. 8259A is treated as peripheral in a microcomputer system.

6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.

7. This controller can be expanded without additional hardware to accept up to 64

interrupt request inputs. This expansion required a master 8259A and eight 8259A

slaves.

8. Some of its programmable features are:

· The ability to accept level-triggered or edge-triggered inputs.

· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.

· Its ability to be configured to implement a wide variety of priority schemes.

8259 Programmable Interrupt Controller (PIC)

8259A PIC- PIN DIGRAM

8259

ASSINGMENT OF SIGNALS FOR 8259: 1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave

in a system with multiple 8259As.3. WR - the write input connects to write strobe signal of microprocessor.4. RD - the read input connects to the IORC signal.5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,

and is connected to a master IR pin on a slave.6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.

In a system with a master and slaves, only the master INTA signal is connected.7. A0 - this address input selects different command words within the 8259A.8. CS - chip select enables the 8259A for programming and control.9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.

When the 8259A is in buffered mode, this pin is anoutput that controls the data bus transceivers in alarge microprocessor-based system.

When the 8259A is not in buffered mode, this pinprograms the device as a master (1) or a slave (0).

CAS2-CAS0, the cascade lines are used as outputs fromthe master to the slaves for cascading multiple8259As in a system.

8259A PIC- BLOCK DIAGRAM

The 82C59A accepts two types of command words generated by theCPU:1. Initialization Command Words (ICWs):

Before normal operation can begin, each 82C59A in thesystem must be brought to a starting point - by a sequence of 2 to4 bytes timed by WR pulses.

2. Operational Command Words (OCWs):These are the command words which command the 82C59A

to operate in various interrupt modes. Among these modes are:a. Fully nested mode.b. Rotating priority mode.c. Special mask mode.d. Polled mode.

The OCWs can be written into the 82C59A anytime afterinitialization.

Programming the 8259A: -

To program this ICW for 8086 we place a logic 1 in bit IC4.

Bits D7, D6 , D5and D2 are don’t care for microprocessor operation and only

apply to the 8259A when used with an 8-bit 8085 microprocessor.

This ICW selects single or cascade operation by programming the SNGL bit. If

cascade operation is selected, we must also program ICW3.

The LTIM bit determines whether the interrupt request inputs are positive edge

triggered or level-triggered.

ICW1:

Selects the vector number used with the interrupt request inputs.

For example, if we decide to program the 8259A so that it functions at vector

locations 08H-0FH, we place a 08H into this command word.

Likewise, if we decide to program the 8259A for vectors 70H-77H, we place a

70H in this ICW.

ICW2:

Is used only when ICW1 indicates that the system is operated in cascade mode.

This ICW indicates where the slave is connected to the master.

For example, if we connected a slave to IR2, then to program ICW3 for this

connection, in both master and slave, we place a 04H in ICW3.

Suppose we have two slaves connected to a master using IR0 and IR1. The

master is programmed with an ICW3 of 03H; one slave is programmed with an

ICW3 of 01H and the other with an ICW3 of 02H.

ICW3:

Is programmed for use with the 8088/8086. This ICWis not programmed in a system that functions with the8085 microprocessors.

The rightmost bit must be logic 1 to select operationwith the 8086 microprocessor, and the remaining bitsare programmed as follows:

ICW4:

Is used to set and read the interrupt mask register.

When a mask bit is set, it will turn off (mask) the corresponding

interrupt input. The mask register is read when OCW1 is read.

Because the state of the mask bits is known when the 8259A is

first initialized, OCW1 must be programmed after programming

the ICW upon initialization.

Operation Command Words

OCW1:

Is programmed only when the AEOI mod is not selected for the 8259A.

In this case, this OCW selects how the 8259A responds to an interrupt.

The modes are listed as follows in next slide:

OCW2:

Selects the register to be read, the operation of the special mask register, and

the poll command.

If polling is selected, the P-bit must be set and then output to the 8259A. The

next read operation would read the poll word. The rightmost three bits of the

poll word indicate the active interrupt request with the highest priority.

The leftmost bit indicates whether there is an interrupt, and must be checked

to determine whether the rightmost three bits contain valid information.

OCW3:

TIMER/COUNTER

452

RD: read signal WR: write signal CS: chip select signal A0, A1: address lines Clock :This is the clock input for the counter.

The counter is 16 bits. Out :This single output line is the signal that

is the final programmed output of the device. Gate :This input can act as a gate for the

clock input line, or it can act as a start pulse,

454

8254 Programming

11-457

8254 ModesGate is low the count will be paused

Gate is highWill continuecounting

Mode 0: An events counter enabled with G.

Mode 1: One-shot mode. s

Gate isHigh outputwill be high

Counter will be reloadedAfter gate high.

458

Mode 2: Counter generates a series of pulses 1 clock pulse wide

Mode 3: Generates a continuous square-wave with G set to 1

cycle is repeated untilreprogrammed or G pin set to 0

If count is even, 50% duty cycleotherwise OUT is high 1 cycle longer

459

Mode 4: Software triggered one-shot.

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

In the last countingWill be stop(not repeated)

In the last countOut will be low

460

8237DMA CONTROLLER


Introduction: Direct Memory Access (DMA) is a method of allowing data

to be moved from one location to another in a computerwithout intervention from the central processor (CPU).

It is also a fast way of transferring data within (andsometimes between) computer.

The DMA I/O technique provides direct access to thememory while the microprocessor is temporarily disabled.

The DMA controller temporarily borrows the address bus,data bus and control bus from the microprocessor andtransfers the data directly from the external devices to aseries of memory locations (and vice versa).

462

The 8237 DMA controller• Supplies memory and I/O with control signals and addresses during DMA

transfer• 4-channels (expandable)

– 0: DRAM refresh– 1: Free– 2: Floppy disk controller– 3: Free

• 1.6MByte/sec transfer rate• 64 KByte section of memory address capability with single programming• “fly-by” controller (data does not pass through the DMA-only memory to I/O

transfer capability)• Initialization involves writing into each channel:

• i) The address of the first byte of the block of data that must be transferred (called the base address).

• ii) The number of bytes to be transferred (called the word count).

463

8237 pins• CLK: System clock• CS΄: Chip select (decoder output)• RESET: Clears registers, sets mask register• READY: 0 for inserting wait states• HLDA: Signals that the μp has relinquished buses• DREQ3 – DREQ0: DMA request input for each channel• DB7-DB0: Data bus pins• IOR΄: Bidirectional pin used during programming and during a DMA write cycle• IOW΄: Bidirectional pin used during programming and during a DMA read cycle• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or

as output to signal the end of the DMA transfer• A3-A0: Address pins for selecting internal registers• A7-A4: Outputs that provide part of the DMA transfer address• HRQ: DMA request output• DACK3-DACK0: DMA acknowledge for each channel.• AEN: Address enable signal• ADSTB: Address strobe• MEMR΄: Memory read output used in DMA read cycle• MEMW΄: Memory write output used in DMA write cycle

464

8237 block diagram

465

Block Diagram Description

It containing Five main Blocks.1. Data bus buffer2. Read/Control logic3. Control logic block4. Priority resolver5. DMA channels.

466

DATA BUS BUFFER: It contain tristate ,8 bit bi-directional buffer. Slave mode ,it transfer data between

microprocessor and internal data bus. Master mode ,the outputs A8-A15 bits of

memory address on data lines (Unidirectional).

READ/CONTROL LOGIC: It control all internal Read/Write operation. Slave mode ,it accepts address bits and control

signal from microprocessor. Master mode ,it generate address bits and control

signal.467

Control logic block It contains ,1. Control logic2. Mode set register and 3. Status Register.

CONTROL LOGIC: Master mode ,It control the sequence of DMA

operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement 14 bit

counter registers. It activate a HRQ signal on DMA channel Request. Slave ,mode it is disabled.

468

DMA controller details

469

Basics of serial communication1. Transmitter:- A parallel-in, serial-out shift register

2. Receiver:- A serial-in, parallel-out shift register.

-470

Parallel Transfer


TRANSMITTER

Receiver

471

Serial communicationinterface

INTEL 8251 USART

472

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

TRANSMITTER (USART) Programmable chip designed for

synchronous and asynchronous serial data transmission

28 pin DIP Coverts the parallel data into a serial stream

of bits suitable for serial transmission. Receives a serial stream of bits and convert

it into parallel data bytes to be read by a microprocessor.

473

BLOCK DIAGRAM 475

Five Sections– Read/Write Control Logic

• Interfaces the chip with MPU• Determine the functions according to the control word • Monitors data flow

– Transmitter• Converts parallel word received from MPU into serial bits• Transmits serial bits over TXD line to a peripheral.

– Receiver• Receives serial bits from peripheral• Converts serial bits into parallel word• Transfers the parallel word to the MPU

– Data Bus Buffer- 8 bit Bidirectional bus.– Modem Controller

• Used to establish data communication modems over telephone line

476

Input Signals

CS – Chip Select When this signal goes low, 8251 is selected by

MPU for communication C/D – Control/Data

When this signal is high, the control registeror status register is addressed

When it is low, the data buffer is addressed Control and Status register is differentiated by

WR and RD signals, respectively

477

• WR – Write– writes in the control register or sends outputs to the

data buffer.– This connected to IOW or MEMW

• RD – Read– Either reads a status from status register or accepts

data from the data buffer– This is connected to either IOR or MEMR

• RESET - Reset• CLK - Clock

– Connected to system clock– Necessary for communication with microprocessor.

478

CS C/D RD WR Function0 1 1 0 MPU writes instruction in the

control register0 1 0 1 MPU reads status from the status

register 0 0 1 0 MPU outputs the data to the Data

Buffer0 0 0 1 MPU accepts data from the Data

Buffer1 X X X USART is not Selected

479

• Control Register– 16-bit register– This register can be accessed an output port

when the C/D pin is high

• Status Register– Checks ready status of a peripheral

• Data Buffer

480


Transmitter Section

Accepts parallel data and converts it into serial data

Two registers Buffer Register

To hold eight bits

Output Register Converts eight bits into a stream of serial bits

Transmits data on TxD pin with appropriate framing bits(Start and Stop)

481

Signals Associated with Transmitter Section

• TxD – Transmit Data– Serial bits are transmitted on this line

• TxC – Transmitter Clock– Controls the rate at which bits are transmitted

• TxRDY – Transmitter Ready– Can be used either to interrupt the MPU or

indicate the status• TxE – Transmitter Empty

– Logic 1 on this line indicate that the output register is empty

482

Receiver Section

Accepts serial data from peripheral and converts it into parallel data

The section has two registers Input Register Buffer Register

483

Signals Associated with Receiver Section

RxD – Receive Data Bits are received serially on this line and

converted into parallel byte in the receiver input

RxC – Receiver Clock RxRDY – Receiver Ready

It goes high when the USART has a character in the buffer register and is ready to transfer it to the MPU

484


Signals Associated with Modem Control

• DSR- Data Set Ready– Normally used to check if the Data Set is ready when

communicating with a modem• DTR – Data Terminal Ready

– device is ready to accept data when the 8251 is communicating with a modem.

• RTS – Request to send Data– the receiver is ready to receive a data byte from

modem• CTS – Clear to Send

485

Control words486

Interfacing of 8255(PPI) with 8085 processor: 491

11-493

Programming 8251 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

11-494

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode (1=enable search for SYN character)

11-495

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

Keyboard/Display Controller

INTEL 8279

496

The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086 microprocessor based system

497

Simultaneous keyboard and display operations

Scanned keyboard mode Scanned sensor mode 8-character keyboard FIFO 1 6-character display

498

Keyboard section Display section Scan section CPU interface section

500

The keyboard section consists of 8 return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix.

It has two additional input : shift and control/strobe. The keys are automatically debounced.

The two operating modes of keyboard section are 2-key lockout and N-key rollover.

503

In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.

In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO.

The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.

The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal (IRQ)when there is an entry in FIFO.

504

The display section has eight output lines divided into two groups A0-A3 and B0-B3.

The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display.

The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs.

505

The cathodes are connected to scan lines through driver transistors.

The display can be blanked by BD (low) line.

The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.

506

The scan section has a scan counter and four scan lines, SL0 to SL3.

In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.

In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.

The scan lines are common for keyboard and display.

507

The CPU interface section takes care of data transfer between 8279 and the processor.

This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU.

It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of8279.

508

The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler.

509


All the command words or status words are written orread with A0 = 1 and CS = 0 to or from 8279.

a) Keyboard Display Mode Set : The format of the command word to select different modes of operation of 8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 D D K K K

510

SENSOR MATRIX

SENSOR MATRIX

511

B) Programmable clock :

The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler. PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31, decided by the bits of an internal prescaler, PPPPP.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 P P P P P

512

c) Read FIFO / Sensor RAM : The format of this command is given below.

AI – Auto Increment FlagAAA – Address pointer to 8 bit FIFO RAM

X- Don’t careThis word is written to set up 8279 for reading FIFO/ sensor RAM. In scanned keyboard mode, AI and AAA bits are of no use. The 8279 will automatically drive data bus for each subsequent read, in the same sequence, in which the data was entered.In sensor matrix mode, the bits AAA select one of the 8 rows of RAM. If AI flag is set, each successive read will be from the subsequent RAM location.

D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 AI X A A A

513

d) Read Display RAM : This command enables a programmer to read the display RAM data.

The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA, the 4-bit address points to the 16-byte display RAM that is to be read.If AI=1, the address will be automatically, incremented after each read or write to the Display RAM. The same address counter is used for reading and writing.

D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 AI A A A A

514

d) Write Display RAM : This command enables a programmer to write the display RAM data.

AI – Auto increment Flag.AAAA – 4 bit address for 16-bit display RAM to be

written.e) Display Write Inhibit/Blanking :

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 AI A A A A

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 X IW IW BL BL

IW - inhibit write flag BL - blank display bit flags

515

g) Clear Display RAM :

ENABLES CLEAR DISPLAY WHEN CD2=1

• CD2 must be 1 for enabling the clear display command.• If CD2 = 0, the clear display command is invoked by setting CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly same as above. • If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared and IRQ line is pulled down and the sensor RAM pointer is set to row 0. •If CA=1, this combines the effect of CD and CF bits.

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 CD2 CD1 CD0 CF CA

CD2 CD1 CD0

0X - All zeros ( x don’t care ) AB=0010 - A3-A0 =2 (0010) and B3-B0=00 (0000)11 - All ones (AB =FF), i.e. clear RAM

516

h) End Interrupt / Error mode Set :

E- Error modeX- don’t care

For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM. Otherwise, if a change in sensor value is detected, IRQ goes high that inhibits writing in the sensor RAM. For N-Key roll over mode, if the E bit is programmed to be ‘1’, the 8279 operates in special Error mode

D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 E X X X 1

517

The digital to analog converters convert binary numbers into their analog equivalent voltages or currents. Techniques are employed for digital to analog conversion.

i. Weighted resistor network ii. R-2R ladder network iii. Current output D/A converter

522

The DAC find applications in areas like digitally controlled gains, motor speed control, programmable gain amplifiers, digital voltmeters, panel meters, etc.

In a compact disk audio player for example a 14 or16-bit D/A converter is used to convert the binary data read off the disk by a laser to an analog audio signal.

Characteristics :1. Resolution: It is a change in analog output for one LSB change in digital input.It is given by(1/2^n )*Vref. If n=8 (i.e.8-bit DAC)

1/256*5V=39.06mV2. Settling time: It is the time required for the DAC to settle for a full scale code change.

523

DAC 0800 8-bit Digital to Analog converter

Features: i. DAC0800 is a monolithic 8-bit DAC manufactured by

National semiconductor. ii. It has settling time around 100ms iii. It can operate on a range of power supply voltage i.e.

from 4.5V to +18V. Usually the supply V+ is 5V or +12V. The V- pin can be kept at a minimum of -12V.

iv. Resolution of the DAC is 39.06mV

524

525


A/D Interfacing{using 8051 microcontroller}

527

Interfacing ADC to 8051ADC0804 is an 8 bit successive approximation analogue to digital

converter from National semiconductors. The features of ADC0804 are differential analogue voltage inputs, 0-5V input voltage range, no zero adjustment, built in clock generator, reference voltage can be externally adjusted to convert smaller analogue voltage span to 8 bit resolution etc.

528

ADC Interfacing

529

D/A Interfacing{using 8051 microcontroller}

530

8051 Connection to DAC808

531

program to send data to the DAC to generate a stair-step ramp


533




UNIT 5 Syllabus

• Data Transfer, Manipulation, Control Algorithms& I/O instructions

• Simple programming exercises: 1. Key board & display interface2. Closed loop control of servo motor3. Stepper motor control 4. Washing Machine Control.

534

INSTRUCTION SET OF 8051

535

8051 Instruction Set• The instructions are grouped into 5 groups

– Arithmetic– Logic– Data Transfer– Boolean– Branching

536

1. Arithmetic Instructions• ADD A, source

A ← A + <operand>.

• ADDC A, sourceA ← A + <operand> + CY.

• SUBB A, sourceA ← A - <operand> - CY{borrow}.

537

• INC– Increment the operand by one. Ex: INC DPTR

• DEC– Decrement the operand by one. Ex: DEC B

• MUL AB

• DIV AB

538

Multiplication A*B Result

8 byte * 8 byte A=low byte,B=high byte

Division

A/BQuotient Remainder

8 byte /8 byte A B

Multiplication of NumbersMUL AB ; A × B, place 16-bit result in B and A

A=07 , B=02 MUL AB ;07 * 02 = 000E where B = 00 and A = 0E

539

Division of NumbersDIV AB ; A / B , 8-bit Quotient result in A &

8-bit Remainder result in BA=07 , B=02 DIV AB ;07 / 02 = Quotient 03(A) Remainder 01 (B)

2. Logical instructions

540

541

•ANL D,S-Performs logical AND of destination & source

- Eg: ANL A,#0FH ANL A,R5•ORL D,S

-Performs logical OR of destination & source- Eg: ORL A,#28H ORL A,@R0

•XRL D,S-Performs logical XOR of destination & source- Eg: XRL A,#28H XRL A,@R0

542

• CPL A-Compliment accumulator-gives 1’s compliment of accumulator data

• RL A-Rotate data of accumulator towards left without carry

• RLC A- Rotate data of accumulator towards left with carry

• RR A-Rotate data of accumulator towards right without carry

• RRC A- Rotate data of accumulator towards right with carry

3. Data Transfer Instructions

543

MOV Instruction• MOV destination, source ; copy source to destination.

• MOV A,#55H ;load value 55H into reg. AMOV R0,A ;copy contents of A into R0

;(now A=R0=55H)MOV R1,A ;copy contents of A into R1

;(now A=R0=R1=55H)MOV R2,A ;copy contents of A into R2

;(now A=R0=R1=R2=55H)MOV R3,#95H ;load value 95H into R3

;(now R3=95H)MOV A,R3 ;copy contents of R3 into A

;now A=R3=95H

544

•MOVX– Data transfer between the accumulator and

a byte from external data memory.•MOVX A, @DPTR•MOVX @DPTR, A

545

•PUSH / POP– Push and Pop a data byte onto the stack.

•PUSH DPL•POP 40H

546

• XCH– Exchange accumulator and a byte variable

•XCH A, Rn•XCH A, direct•XCH A, @Ri

547

4.Boolean variable instructions

548

CLR:• The operation clears the specified bit indicated in

the instruction• Ex: CLR C clear the carry

SETB:• The operation sets the specified bit to 1.

CPL:• The operation complements the specified bit

indicated in the instruction

549

550

•ANL C,<Source-bit>

-Performs AND bit addressed with the carry bit.- Eg: ANL C,P2.7 AND carry flag with bit 7 of P2

•ORL C,<Source-bit>

-Performs OR bit addressed with the carry bit.- Eg: ORL C,P2.1 OR carry flag with bit 1 of P2

• XORL C,<Source-bit>

-Performs XOR bit addressed with the carry bit.- Eg: XOL C,P2.1 OR carry flag with bit 1 of P2

•MOV P2.3,C•MOV C,P3.3•MOV P2.0,C

551

5. Branching instructions

552

Jump Instructions• LJMP (long jump):

– Original 8051 has only 4KB on-chip ROM

• SJMP (short jump):– 1-byte relative address: -128 to +127

553

Call Instructions• LCALL (long call):

– Target address within 64K-byte range

• ACALL (absolute call): – Target address within 2K-byte range

554

• 2 forms for the return instruction:– Return from subroutine – RET– Return from ISR – RETI

555

8051 Addressing

ModesPresented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode

8051 Addressing Modes

• The CPU can access data in various ways, which are called addressing modes

1. Immediate2. Register3. Direct4. Indirect5. Relative6. Absolute7. Long8. Indexed

558

1. Immediate Addressing Mode• The immediate data sign, “#”• Data is provided as a part of instruction.

559

2. Register Addressing Mode• In the Register Addressing mode, the instruction involves

transfer of information between registers.

560

3. Direct Addressing Mode

• This mode allows you to specify the operand by giving its actual memory address

561

4. Indirect Addressing Mode

• A register is used as a pointer to the data.• Only register R0 and R1 are used for this purpose.• R2 – R7 cannot be used to hold the address of an

operand located in RAM.• When R0 and R1 hold the addresses of RAM locations,

they must be preceded by the “@” sign.

562

MOVX A,@DPTR

5. Relative Addressing

• This mode of addressing is used with some type of jump instructions, like SJMP (short jump) and conditional jumps like JNZ

Loop : DEC A ;Decrement AJNZ Loop ;If A is not zero, Loop

563

6. Absolute Addressing

• In Absolute Addressing mode, the absoluteaddress, to which the control is transferred, isspecified by a label.

• Two instructions associated with this modeof addressing are ACALL and AJMPinstructions.

• These are 2-byte instructions

564

7. Long Addressing

• This mode of addressing is used with the LCALL and LJMP instructions.

• It is a 3-byte instruction• It allows use of the full 64K code space.

565

8. Indexed Addressing

• The Indexed addressing is useful when there is a need to retrieve data from a look-up table (LUT).

566

8051 Assembly Language

Programming(ALP)

567

ADDITION OF TWO 8 bit Numbers

ADDRESS LABEL MNEMONICS

9100: MOV A,#05

MOV B,#03

ADD A,B

MOV DPTR,#9200

MOVX @DPTR,AHERE SJMP HERE

568After execution: A=08

SUBTRACTION OF TWO 8 bit Numbers

569

ADDRESS LABEL MNEMONICS

9100: CLR C

MOV A,#05

MOV B,#03

SUBB A,B

MOV DPTR,#9200

MOVX @DPTR,AHERE SJMP HERE

After execution: A=02

MULTIPLICATION OF TWO 8 bit Numbers

Address Label Mnemonics

9000 START MOV A,#05

MOV B,#03

MUL AB

MOV DPTR,#9200

MOVX @ DPTR,A

INC DPTR

MOV A,B

MOVX @DPTR,A

HERE SJMP HERE

Address Label Mnemonics

9000 START MOV A,#05

MOV B,#03

DIV AB

MOV DPTR,#9200

MOVX @ DPTR,A

INC DPTR

MOV A,B

MOVX @DPTR,A

HERE SJMP HERE

DIVISION OF TWO 8 bit Numbers

After execution: A=0F , B=00 After execution: A=01 , B=02

MOV 40H, #02H store 1st number in location 40HMOV 41H, #04H

MOV 42H, #06H

MOV 43H, #08H

MOV 44H, #01H

MOV R0, #40H store 1 st number address 40H in R0MOV R5, #05H store the count {N=05} in R5MOV B,R5 store the count {N=05} in BCLR A Clear Acc

LOOP: ADD A,@R0INC R0DJNZ R5,LOOPDIV ABMOV 55H,A Save the quotient in location 55H

HERE SJMP HERE

Average of N (N=5) 8 bit Numbers

Answer: 02+04+06+08+01 = 21(decimal) = 15 (Hexa)

SUM = 15 H Average = 21(decimal) / 5 = 04 (remainder) , 01 (quotient) quotient55

Simple programming exercises: 1. Key board & display interface2. Closed loop control of servo motor3. Stepper motor control 4. Washing Machine Control.

572

1.Keyboard & Display

Interfacing

573

KEYBOARD INTERFACING • Keyboards are organized in a matrix of rows

and columnsThe CPU accesses both rows and columns

through ports .• Therefore, with two 8-bit ports, an 8 x 8

matrix of keys can be connected to a microprocessor

When a key is pressed, a row and a column make a contact

574

•Otherwise, there is no connection between rows and columns

•A 4x4 matrix connected to two portsThe rows are connected to an

output port and the columns are connected to an input port

575

4x4 matrix

576

Connection with keyboard matrix

Final Circuit


2.CLOSED LOOPSERVO MOTOR

CONTROL

3. STEPPERMOTOR

INTERFACING

Stepper Motor Interfacing

586

Stepper Motor Interfacing

• Stepper motor is used in applications such as; dot matrix printer, robotics etc

• It has a permanent magnet rotor called the shaft which is surrounded by a stator. Commonly used stepper motors have 4 stator windings

• Such motors are called as four-phase or unipolar stepper motor.

587

Full step

590

Step angle:

• Step angle is defined as the minimum degree of rotation with a single step.

• No of steps per revolution = 360° / step angle• Steps per second = (rpm x steps per revolution) / 60• Example: step angle = 2°• No of steps per revolution = 180

591

A switch is connected to pin P2.7. Write an ALP to monitor the status of the SW. If SW = 0, motor moves clockwise and If SW = 1, motor moves anticlockwise

SETB P2.7MOV A, #66HMOV P1,A

TURN: JNB P2.7, CWRL AACALL DELAYMOV P1,ASJMP TURN

CW: RR AACALL DELAYMOV P1,ASJMP TURN592

DELAY: MOV R1,#20L2: MOV R2,#50L1:DJNZ R2,L2

DJNZ R2,L1RET

4. Washing machine control

using 8051


What Is a Washing Machine?

A washing machine is an electronic device that is designed to wash laundry like clothes, sheets, towels and other bedding. A washing machine is built with two steel tubs which are the inner tub and the outer tub whose main role is to prevent water from spilling to other parts of the machine.

Control knobs in washing machine:

• Load select knob• Water inlet select knob• Mode select knob• Program select knob


Load select knob:-

load Number of clothes

low

medium

high

Load select

Water inlet select knob:-

hot

cold

both-mixed

Water inlet

Mode select knob:-

Save mode

Normal mode

Mode

Program select knob:-

Heavy Clothes very dirty

Normal Normal dirty clothes

LIGHT For light dirty clothes

Delicate For silk clothes

Operations:-

• Fill:- water will be filled by the pump as per the load knob selected.

• Agitate:- The wash basket will rotate in a clockwise direction for 10 revolutions, After that basket will stop for 2 seconds, then rotate 10 revolutions in anticlockwise direction. The process will be continued for specified minutes in cycle table.

Drain:- After agitation, the water and detergent are drained.

Spin:- During spin, agitator will be stationary, only the basket will rotate at high speed. Then the moisture of clothes are removed through holes in the inner metallic basket.

Indicator:- Machine ON LED ONAfter completion of washing cycle,

buzzer sound will be generated.

Washing cycle for Heavy, Normal, Light and Delicate setting

Operation Heavy Normal Light Delicate

Fill water Set by loadSelect knob

Set by loadSelect knob



Agitate 20 minutes 15 minutes 10 minutes 5 minutes

Drain 5 minutes 5 minutes 5 minutes 5 minutes

Fill water Set by loadSelect knob




Agitate 10 minutes 10 minutes 5 minutes 5 minutes

Drain 5 minutes 5 minutes 5 minutes 5 minutes

Spin 10 minutes 10 minutes 5 minutes 5 minutes


Circuit diagram

08051

Microcontroller

P2.1P2.2

P0.2P0.1P0.0

P2.3

P2.4

P2.6

P2.5

P2.0 P2.7

P1.0P1.1P1.2P1.3

P0.3P0.4

Hot

Cold

Agitator rmotordrive

Agitator rmotordrive

Spin motordrive

High level

Medium level

LowlevelDrain

Washing machine ON

LED0

HeavyNormalLightDelicated

HotNormal

Buzzer sound

Basket

Operation Signal Input/output Port pin no.

Load / water level select

Water level lowWater level medWater level high

InputInputInput

P0.0P0.1P0.2

Water inlet Hot water knobNormal water knob

InputInput

P0.3P0.4

Program select HeavyNormalLightDedicate

InputInputInputInput

P1.0P1.1P1.2P1.3

Machine ON Machine on indic Output P2.0

Fill water Hot water inletNormal water inlet

OutputOutput

P2.1P2.2

Agitation control Motor rotate in clocdirectionMotor rotate in anticlock direc

Output

Output

P2.3

P2.4

Drain Drain valve open Output P2.5

Spin Spin motor ON/OFF Output P2.6

Washing ccomplete Washing comp indic Output P2.7

Put machine ON

Fill machine with water hot or normal

Check program settingAgitate20 min

Drain 5 min

Fill water

Agitate10 min

Spin20 min

Drain5 min

Buzzer for wash

complete

Agitate15 min

Drain 5 min

Fill water

Agitate10 min

Spin10 min

Drain5 min

Buzzer for wash

complete

Agitate10 min

Drain 5 min

Fill water

Agitate5 min

Spin5 min

Drain5 min

Buzzer for wash

complete

Agitate5 min

Drain 5 min

Fill water

Agitate5 min

Spin5 min

Drain5 min

Buzzer for wash

complete

Commands for washing-machine controllerLabels Mnemonics Operands Comments

SETBLCALL

JNB

SJMP

P2.0FILL_1

P1.0,LOOP_1

HEAVY

Machine ON indicationMachine fill with water 1st

timeChk prog setng knob for heavy. if P1.0 is not set,jump to LOOP_1If P1.0 is set,jump to HEAVY

LOOP_1 JNB

SJMP

P1.1,LOOP_2

NORMAL

Check prog setng knob for normal.if P1.1 is not set.jump to LOOP_2If P1.1 is set, jump to NORM

LOOP_2 JNB

SJMP

P1.2,LOOP_3 Chck prog setng knob for normal.if P1.2 is not set,jump to LOOP_3If P1.2 is set,jump to LIGHT

LOOP_3 JNB

SJMP

P1.3,LOOP_4

DELICATE

Check prog set knob for delicate. If P1.3is not set,jump to LOOP_4If P1.2 is set,jump to delicate

DISPLAY SETB P2.7 Indicate the completion of wash cycle.

LOOP_4 NOPLJMP 0000 End of program

ee6502 microprocessor & microcontroller regulation 2013

Engineering

pentium mmx

clock speed

pentium iv zeon

data bus

address bus

external bus

programmable device

semiconductor device