eee2243 digital system design chapter 3: verilog hdl (combinational) by muhazam mustapha, january...
TRANSCRIPT
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EEE2243Digital System Design
Chapter 3: Verilog HDL (Combinational)
by Muhazam Mustapha, January 2011
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Learning Outcome
• By the end of this chapter, students are expected to be able to:– Quartus II– Verilog
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Chapter Content
• Why HDL?
• Verilog
• Boolean Equation Modeling
• Behavior Modeling
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Why HDL?
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Hardware Description Language• A drawing of a circuit, or schematic, contains graphical information about a design– Inverter is above the OR
gate, AND gate is to the right, etc.
• Such graphical information may not be useful for large designs
• Can use textual language instead
DoorOpener
c
h
p
f
Vahid Slide
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Hardware Description Language• Hardware description language (HDL)
– Intended to describe circuits textually, for a computer to read
– Evolved starting in the 1970s and 1980s
• Popular languages today include:– VHDL –Defined in 1980s by U.S. military; Ada-like
language– Verilog –Defined in 1980s by a company; C-like
language– SystemC –Defined in 2000s by several companies;
consists of libraries in C++
Vahid Slide
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Verilog
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General Structure
Mohamed Khalil Hani
module module_name(ports)
{ parameter declaration }
input port_list;
output port_list;
wire list;
reg (or integer) list;
{ assign continuous_statement; }
{ initial block; }
{ always block; }
{ gate instantiations; }
{ module instantiations; }
endmodule
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General Structure
module CircuitA(Cin, x, y, X, Y, Cout, s, Bus, S)
input Cin, x, y;
input [3:0] X, Y;
output Cout, s;
output [3:0] S;
inout [7:0] Bus;
wire d;
reg e;
...
endmodule
Mohamed Khalil Hani
• Example:
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• Format:
Constant Representation
Mohamed Khalil Hani
<size_in_bit>’<base_id><significant_digit>
8 bit binary: 8’b0011101012 bit hex: 12’habc7 bit decimal: 7’d50
Negative 5 bit binary: -5’b01010Negative 8 bit hex: -8’h8c
• Example:
• Negative numbers are internally represented as 2’s complement, but in the code we just use signed magnitude:
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• High-Z output is represented as z• Undefined output is represented as x
Constant Representation
Mohamed Khalil Hani
8 bit binary with 4 bit z: 8’bzzzz10108 bit binary with 4 bit x: 8’b1010xxxx
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Operators
Mohamed Khalil Hani
Operator Type Operator Symbol
Operation
Bitwise ~, &, |, ^, ~^ not, and, or, xor, xnor
Logical !, &&, || not, and, or
Arithmetic +, -, *, / add, sub, mul, div
Relational >, <, >=, <= gt, lt, gt or eq, lt or eq
Equality ==, !=, ===, !==
eq, not eq, case eq, case not eq
Shift >>, <<, >>>, <<<
unsigned rs, unsigned ls, signed rs, signed ls
Concatenation { , }
Conditional ? :
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Modeling Style• There are 3 coding styles in Verilog• Boolean Equation
– Done by writing Verilog version of Boolean equation to define output
• Behavioral– Done by writing the output arithmetical definition
instead of the direct Boolean equation
• Structural– Done writing Verilog in multiple modules
• We will first cover Boolean equation and Behavioral
Mohamed Khalil Hani
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Boolean Equation Modeling
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assign Keyword• The pure Boolean combinational style modeling
is signified by the use of assign keyword
Mohamed Khalil Hani
module functionA(x1, x2, x3, f); input x1, x2, x3; output f;
assign f = (~x1 & ~x2 & x3) | (x1 & ~x2 & ~x3) | (x1 & ~x2 & x3) | (x1 & x2 & ~x3);endmodule
Logic Function
x1
x2
x3
f
321321321321 xxxxxxxxxxxxf
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Example – AND Gate
module ANDGate(x, y, f); input x, y; output f;
assign f = x & y;endmodule
y f
Quartus II version 9 Demo
x
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Example – Boolean Half Adder
Mohamed Khalil Hani
module HalfAdder(a, b, sum, carry); input a, b; output sum, carry;
assign sum = a ^ b; assign carry = a & b;endmodule
x1
x2
sum
carry
Quartus II version 9 Demo
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Behavior Modeling
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always Keyword• The behavioral style
modeling is signified by the use of always keyword
• Many C-like keywords can also be used
• For a complex design, behavioral style is more favorable
Mohamed Khalil Hani
module ORGate(x, y, f); input x, y; output f; reg f;
always@(x or y) begin if (x == 0) && (y == 0) f = 0; else f = 1; endendmodule
Also read Vahid pg 496
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Example – Behavioral Half Adder
module HalfAdder(a, b, sum_carry); input a, b; output [1:0] sum_carry; reg [1:0] sum_carry;
always@(a or b) begin sum_carry = a + b; endendmodule
Quartus II version 9 Demo