eet 1131 unit 11 counter circuits

EET 1131 Unit 11Counter Circuits

Read Kleitz, Chapter 12, skipping Sections 12-10 and 12-11.

Homework #11 and Lab #11 due next week.

Quiz next week.

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text.

LSB changes on every number.

The next bit changes on every other number.

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

The next bit changes on every fourth number.

Counting in Binary


A counter can form the same pattern of 0’s and 1’s with logic levels. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary.

0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

0 0 0 0 1 1 1 1 0

LSB

MSB

Counting in Binary

Synchronous versus Asynchronous

The synchronous/asynchronous distinction has different meanings:

1. As applied to inputs: A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately.

2. As applied to counters: in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs.


In an asynchronous counter, the clock is applied only to the first stage. Each subsequent stage gets its clock from the previous stage.

Three bit Asynchronous Counter

The asynchronous counter shown is a three-bit counter (also called MOD-8 counter or divide-by-8 counter). It uses J-K flip-flops in the toggle mode.

CLK

K0

J0

Q0

Q0

C C C

J1 J2

K1 K2

Q1 Q2

Q1

HIGH

Waveforms are on the following slide…


Three bit Asynchronous Counter

CLK

Q0

Q1

Q2

1 2 3 4 5 6 7 8

10 10 10 10 0

10 10 01010

00 11 01100

Notice that the Q0 output is triggered on the rising edge of the clock signal. The following stage is triggered from Q0. The rising edge of Q0 is equivalent to the falling edge of Q0. The resulting sequence is that of a 3-bit binary up counter.


Propagation Delay

Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage.

Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage.

CLK

Q0

Q1

Q2

1 2 3 4

Q0 is delayed by 1 propagation delay, Q1 by 2 delays and Q2 by 3 delays.


The 74LS93 Asynchronous Counter

(9)(12) (8) (11)

(1)

(14)

(2)

(3)

The 74LS93 has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B.

CLK A

K0

J0

Q0

C C C

J1 J2

K1 K2

Q1 Q2

C

J3

K3

Q3

CLK B

The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count.

RO (1)RO (2)

All J and K inputs are connected internally HIGH

Some Asynchronous Counter ICs

7490 Four bit decade counter (MOD 10)

7492 Four bit divide-by-12 counter (MOD 12)

7493 Four bit binary counter (MOD 16)

http://focus.ti.com/lit/ds/symlink/sn7490a.pdf


Asynchronous Decade Counter

This counter uses a NAND gate to recycle the count sequence to zero after the 1001 state, resulting in a MOD-10 counter (or decade counter). Other truncated sequences can be obtained using a similar technique.

Waveforms are on the following slide…

CLK

K0

J0

Q0

C C C

J1 J2

K1 K2

Q1 Q2

HIGH

C

J3

K3

Q3

CLR


Asynchronous Decade Counter

When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line.

1 2 3 4 5 6 7 8 9 10

Glitch

Glitch

CLK

Q0

Q1

Q2

Q3

CLR

Glitch

Glitch


BCD Decoder/DriverA special-purpose decoder is the 7447. This is a BCD-to-seven segment display with active LOW outputs.

The a-g outputs are designed for much higher current than most devices (hence the word driver in the name).

abcdefg

1248

(16)

(4)

(13)(12)(11)(10)(9)

(15)(14)

(1)(2)(6)

(7)

(3)(5)

(8)

BCD inputs

Outputs to seven segment device

GND

VCC

BCD/7-segBI/RBO BI/RBO

LTRBI

LT

RBI

74LS47


BCD Decoder/Driver

Here the 7447 is an connected to an LED seven segment display. Notice the current-limiting resistors, required to prevent overdriving the LED display.

VCC

GND

+5.0 V

+5.0 V

R's =330 W

abcdefg

abcdefg

MAN7274LS47

LTBI/RBORBI

1.0 kW

1

1 22

3, 9, 143456

7

7

8

8

9

1010

11

1112 1313

1415

16BCD/7-seg

BCDinput

DCBA

7447 BCD-to-7-Segment Decoder/Driver

4 input pins for BCD code. 7 output pins to control the seven

segments of a 7-segement display. Also has a lamp test input. Also a ripple-blanking input and output

to suppress leading or trailing zeroes. Data sheet: 7447

http://focus.ti.com/lit/ds/symlink/sn7447a.pdf


Synchronous Counters

In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes.

K0

J0

Q0

C C C

J1 J2

K1 K2

Q0Q1Q0 Q1 Q2

CLK

HIGHThis 3-bit binary synchronous counter has the same count sequence as the 3-bit asynchronous counter shown previously.


CTR DIV 16(1)(9)

(7)(10)

C(2)

(3) (4) (5) (6)

(14) (13) (12) (11)

TC = 15(15)

A 4-bit Synchronous Binary CounterThe 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two count enables, and a ripple count output that signals when the count has reached the terminal count.

Example waveforms are on the next slide…

Data inputs

Data outputs

CLRLOADENTENPCLK

RCO

Q0 Q1 Q2 Q3

D0 D1 D2 D3


Data inputs

Data outputs

CLR

LOAD

ENTENPCLK

RCO

Q0

Q1

Q2

Q3

D0

D1

D2

D3

Clear Preset

Count Inhibit

12 13 14 15 0 1 2

Some Synchronous Counter ICs

74160 and 74162: Four-bit synchronous decade counters (MOD 10)

74161 and 74163: Four bit synchronous binary counters (MOD 16)

http://focus.ti.com/lit/ds/symlink/sn74160.pdf


Up/Down Synchronous Counters

The 74HC191 has the same inputs and outputs but is a synchronous up/down binary (MOD-16) counter.

(10)(15)

(4)(5)

(11)(14)

(1) (9)

(3) (2) (6) (7)

(12)

(13)

Data inputs

Data outputs

MAX/MIN

CLK

Q0 Q1 Q2 Q3

LOAD

CTEN

RCO

D/U

D0 D1 D2 D3

C

CTR DIV 10

74HC190

(10)(15)

(4)(5)

(11)(14)

(1) (9)

(3) (2) (6) (7)

(12)

(13)

Data inputs

Data outputs

MAX/MIN

CLK

Q0 Q1 Q2 Q3

LOAD

CTEN

RCO

D/U

D0 D1 D2 D3

C

CTR DIV 16

74HC191

The 74HC190 is a high speed CMOS synchronous up/down decade (MOD-10) counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached.

Some Up/Down Synchronous Counter ICs

74190 Four bit up/down decade counter (MOD 10)

74191 Four bit up/down binary counter (MOD 16)

http://focus.ti.com/lit/ds/symlink/sn74190.pdf

Cascading Counters

Most counter chips are 4-bit counters, with a modulus of 16 or less.

To get larger moduli, you cascade two or more counter chips together.

When you cascade counters, their moduli multiply, not add. Example: If you cascade a MOD-10 counter with a

MOD-16 counter, you get a MOD-160 counter. The connections for cascading counters

differ depending on whether you’re using asynchronous counters or synchronous counters.


Cascaded asynchronous counters


16

ƒin

256ƒin

HIGH

CLK Q0 Q1 Q2C

Counter 1 Counter 2

C

CTEN CTENCTR DIV 16 CTR DIV 16

Q3 Q0 Q1 Q2 Q3

TC TC

fin

a) Each counter divides the frequency by 16. Thus the modulus is 162 = 256.

For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached.

Cascaded synchronous counters

a) What is the modulus of the cascaded DIV 16 counters? b) If fin =100 kHz, what is fout?

fout

b) The output frequency is 100 kHz/256 = 391 Hz

eet 1131 unit 11 counter circuits

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