EET2141 Project 2: Binary Adder Using Xilinx 7.1i

Due Friday April 25

Introduction

This Xilinx project introduces the characteristics of the ripple carry adder. From the last project, you learned that logic circuits do not react instantaneously. When the input changes, there is invariably some delay before the output changes. This project demonstrates the consequences of these delays. If necessary, review the steps in Project 1 with regard to creating schematics in the Schematic Editor, setting up inputs in HDL Bencher and running the simulation with ModelSim.

Opening the Project

Retrieve EET2141proj2.zip from the EET2141 web site and store it in the EET2141 sub- directory on your PC (the one you have created in the first project). Create a new sub-directory (folder) and name it EET2141proj2. Unzip EET2141proj2.zip using WinZip and extract the contents to the sub-directory EET2141proj2. Among the files that have been extracted, you will find a file named proj2.ise.

Start up the Xilinx project by double-clicking on the file proj2.ise. To invoke the Schematic Editor, double-click on the source named top (top.sch) in the Project Navigator window. This will load the circuit into the Xilinx ECS (Schematic Editor). You will get a pop-up window Open Schematic File Errors. Under Out-of-Date Symbols, click on adder and Update Instances button. Select the Action – Ignore these errors and click OK. Then click on the Xilinx ECS – [top.sch] window to save the updated schematic file.

You will see a block called adder, which is a one-bit adder. The inputs are X, Y, and Cin (carry input). Cin is connected to gnd or logic 0. The outputs are Sum and Cout. Sum is the sum bit of the adder, and Cout is the carry out of the adder. If you want to see the internal details of the adder block, you can double-click on the schematic file named adder (adder.sch) in your Project Navigator window. The symbol adder has been created for this project and it can be used as any other logic gate that you have used so far. This method of creating symbols of a circuit is useful if you are going to use multiple instances of the same block. In this project, you will use four instances of the adder block called adder and make a four-bit adder by joining them.

Simulating the One-bit Adder

In your Project Navigator window, Click on your schematic file top (top.sch) to make it active. Now select Project → New Source. In the window that opens up select the option Test Bench Waveform. Specify wave as the name for the waveform in the File Name field and click on Next.

Now you will get to another window called Select. This step is different from the

first project, as you will have to select which module you want to simulate. Since adder is by itself a self contained module, you can simulate it separately. In bigger circuits where you have numerous modules, this selection is very useful for debugging. Select adder as the source file in the Select window. Click Next and then in the following window click Finish.

This will open the HDL Bencher. In the Initialize Timing window, select the option

Combinatorial Design. In the input boxes after Check outputs and Assign inputs, enter the value 1, and set the Initial Length of Test Bench to 38 ns, and set the time scale to ns and click OK.

Assigning Input Values From the Project 1 simulation step, when you select Post-Fit VHDL Model, you can

see that there is a red bar in front of the output, and it has about a 5 ns delay. Thus, in this project, we will start our simulation at 14 ns, use a 4 ns time interval, and set the end of simulation to a large value such as 38 ns.

We have two primary inputs to our circuit X and Y (Input Cin is connected to gnd,

so we don’t need to include that). Now to functionally simulate the circuit, we should simulate all the 4 possible combinations (00, 01, 10, 11) of the X and Y inputs. To do this, we are going to assign a square waveform to X and then assign a similar waveform to Y but the time period of the successive waveform will be half that of the former. So the time period of Y is twice that of X.

There are 2 methods that you can use to assign your inputs. From Project 1, you

have learned how to use the pattern wizard. Another way is to click on the blue area of the waveform signal. This will toggle the signal up or down. See the figure below.

Follow the simulation steps as you did in Project 1. Set the Fit process for

Implementation Template property to Optimize Balance. In this project, we will examine the timing analysis of the circuit. All the simulations should be done with the Simulate Post-Fit VHDL Model option. Observe the output waveforms.

The red bar shows the set up delay of about 5 ns. This creates a delay effect on the

outputs after the X and Y inputs change. Question: 1. In the worst case delay, how long does it take the outputs, Cout and Sum, to reflect changes in the inputs?

Building a Four-Bit Adder

After finishing the simulation, open the top.sch file. As before, if you get the Open Schematic File Errors, make sure that you update the adder instance and save the schematic file before exit. In this section, you will use copies of the one-bit adder you were given in the last part to build a four-bit adder. Follow the steps below to modify the circuit. Step 1: Delete the input and output ports and connecting wires from the circuit. Do not delete the one-bit adder. You should only have the one-bit adder on your sheet now with Cin connected to gnd. Step 2: The component called adder is local to your project. You can either copy the one that is already in the circuit or pick it from the symbols library. In the left side of your Schematic Editor window, under the sub-window called Categories, click on the second entry (entry below <All Symbols>). This will be the path where your project is. This entry will display all the symbols that you have created local to your project. Now click on the entry adder under the Symbols sub-window. You can also choose <All Symbols> in Categories and browse down to adder. Place three copies of adder in your schematic and place them along the same horizontal line matching the adder already present in your sheet.

Step 3: Draw the wires between the adders connecting the Cout to the Cin of the adjacent adders. Connect the Cout of the left most adder to an output marker named Cout. Your circuit will now look something like Figure below.

Step 4: Now draw a horizontal wire above the adders. We will change this wire to a bus. A bus is a collection of wires. So instead of setting the Y input of all the four adders separately, we will set the bus to a 4-bit value and it will automatically set the individual values to the Y inputs.

Step 5: Now click on Select Add → Net Name or click the Add Net Name icon in the Tools tool bar.

Type in Y(3:0) in the text area of the Name field in the left side of the window. Keep the other options in the left side as they are. This will attach the bus name to the cursor. You can see this when you move around the cursor, the name will also move along.

Step 6: Click the end of the wire to apply the name. This will change the wire into a bus. To verify this, zoom in. The bus is represented visually by a thicker wire.

Step 7: Click ESC to exit the bus-drawing mode. Next, add nets (wires) to attach the appropriate pins from the adder to the bus. Use bus taps to tap off a single bit of a bus and connect it to one adder block. The Schematic Capture tool names the bus taps incrementally as they are drawn. Note: Enlarging the view of the schematic will enable greater precision when drawing the nets.

Step 8: Select Add → Bus Tap or click the Add Bus Tap icon in the Tools toolbar. The cursor changes indicating that you are now in the draw bus tap mode. In the Options window in the left, choose the Top orientation for the bus so that the bottom of the triangle

is placed on the bus. The other side of the bus should now be pointing to an unconnected pin.

Step 9: Repeat the above step to tap off the other three bits of the bus.

Step 10: To connect each of the bus taps to the corresponding adder input, select Add →

Wire or click the Add Wire icon in the Tools toolbar. Draw a wire from the other end of the bus tap to the corresponding Y input of the adder. Repeat this for the other bus taps. Zoom in for better clarity. Note: You can skip steps 8 and 9 if you select Automatically add a bus tap between the bus and the wire in the Options window of the Add Wire tool. Try this option with X and Sum.

Step 11: Select Add → Net Name or click the Add Net Name icon in the Tools toolbar. Type in Y(0) in the text area of the Name field (as done previously for the bus name). The net name is now at the end of your cursor. You can increment subsequent net names by selecting the option Increment the Name.

With the Increment the Name option selected, start with the right-most wire and continue clicking left until you have named the fourth and final net Y(3). Make sure you click the name right on top of the wire.

Step 12: To make the bus Y(3:0) as an input, click on the button. Select the direction by clicking on Add an input marker in the Options window. Also select the option Right in the drop down menu to select the orientation of the input port as show below.

Now an input marker appears in your Schematic Editor. You will have to place the input marker to directly coincide with the terminated end of your wire. You may need to zoom in on your schematic to do this.

Step 13: Repeat steps 4 – 12 for adding the buses for input X(3:0) and the output Sum(3:0). Make sure that you specify the IOMarker direction as input for X(3:0) and output for Sum(3:0). The orientation of the bus tap for X(3:0) is Top, the same as Y(3:0). However, the orientation of the bus tap for Sum(3:0) is Bottom. Your final schematic should look like that shown below.

Step 14: When done with wiring, type in your name in the Name Lastname field and you can also change the settings for font size. Step 15: Before you save your changes and start the simulator, you need to check the circuit. Click on Tools → Check Schematic. If there are errors, they will be displayed in the Schematic Check Errors window. If there are no errors, then the Error Msg will display No Errors Detected. Save your schematic and take a printout of the circuit.

Simulating a Four-Bit Adder

Close your Schematic Editor and come to your Project Navigator window. Click on your schematic file top (top.sch) to make it active. Now select Project → New Source. In the window that opens up, select the option Test Bench Waveform. Specify wave2 as the name for the waveform in the File Name field and click on Next. Select top as the source file in Select window. Click Next and then in the following window click Finish.

This will open the HDL Bencher window. In the Initialize Timing window, select

the option Combinatorial Design. In the input boxes after Check outputs and Assign inputs, enter the value 1, and set the Initial Length of Test Bench to 38 ns, and set the time scale to ns and click OK.

Assigning Input Values Use the four-bit adder to compute 6+1=7. You have to apply one of the values (6) to

one of the inputs X and the other value (1) to the other input Y. Remember that this is a 4-bit adder and we have to convert the decimal numbers to 4-bit binary numbers. So decimal 6 is equivalent to 0110 in binary and decimal 1 is equivalent to 0001 in binary.

Now in HDL Bencher, right click on your waveforms to set the base for your

signals (X, Y and Sum) as binary (base 2). Make sure that you have the base selected properly.

Right click on the X(3:0) at 14 ns and select Set Value. Or left click at the field to open Set Value window. Type in 0110 and click OK. This sets the value for 6. Now in a similar fashion set the value for Y(3:0) as 0001. As mentioned in the beginning of the project, we will start all of our simulations at 14 ns, and set the end of simulation for 38 ns.

Save the waveform test bench setup. Click on the waveform file in the Sources in Project sub-window. Now in the sub-window Processes for Current Source, double-click on the option Simulate Post-Fit VHDL Model. This will run ModelSim (this may take a while, so be patient!). Print out the waveform and answer the following questions.

Questions: 2. What is the result of 6+1 addition, in binary? 3. How long did it take, from the time that the inputs changed, until the outputs were stable and gave the correct final result?

Further Simulation

Remember to quit ModelSim every time before you start a new simulation. Now quit ModelSim and simulate the 4-bit adder to compute 7+1. From your Project Navigator window, click on your schematic file top (top.sch) to make it active. Now select Project → New Source. In the window that opens up select the option Test Bench Waveform. Specify wave3 as the name for the waveform in the File Name field and click on Next, Next and then in the following window click Finish. Remember that you can save every simulation you do by opening up new waveform sources or you can take the printouts and answer the questions and then start the next addition from the same wave source. Now use the 4-bit adder to compute 7+1. Print out the waveform and answer the following questions.

Questions: 4. What is the result of 7+1 addition, in hex, binary and decimal? 5. How long did it take, from the time the inputs changed, until the outputs were stable and gave the correct final result? Did 7+1 addition take more or less time than that for 6+1? 6. Now, set the value of X to be 1011 at 18 ns and 1101 at 22 ns and simulate it. What incorrect results, if any, are shown on the output display before the correct result appears? Note: On the Sum output, before you get the correct answer, you will get some other values, which you can read if you place your cursor over the value.

Final Simulations

Follow the same waveform format as in the earlier section, start inputs with 0000 and change them at 14 ns. Use the 4-bit adder to compute 14+1=15 (in binary, this is expressed as 1110+0001=1111). Repeat the simulation to compute 15+1 and 1111+1011. Print out each copy of the waveform for 14+1, 15+1 and the 1111+1101 simulations. Compute each addition in a separate waveform.

Questions: 7. What are the results of the additions 14+1 and 15+1, in hex and binary? 8. What incorrect results, if any, are shown on the output display before the correct result appears? 9. How long did it take, from the time the inputs changed, until the outputs were stable and gave the correct final result for 15+1? Did this addition take more or less time than 14+1? 10. What is the result of the addition 1111 + 1101, in decimal and binary? 11. How long did the 1111+1101 addition take? Did this addition take more or less time than 14+1 and 15+1? Why? Report The report should be typed. Be sure to include:

• Answers to the questions (1-11) • A printout of the 4-bit adder circuit • Five waveform outputs showing the results of the 6+1, 7+1, 14+1, 15+1, and

1111+1101 simulations.