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Effect of the sensing capacitance in a‘sawyer-tower’ set-up on hysteresisloopsPeter Zurcher a , R. E. Jones Jr. a , Peir Chu a , Tom Lii a , S. J.Gillespie a , Bo Jiang b & Jack C. Lee ba Materials Research and Strategic Technologies, Motorola Austin,Texas, 78721, USAb Microelectronics Research Center, University of Texas, Austin, TX,78712Published online: 19 Aug 2006.

To cite this article: Peter Zurcher , R. E. Jones Jr. , Peir Chu , Tom Lii , S. J. Gillespie , BoJiang & Jack C. Lee (1995) Effect of the sensing capacitance in a ‘sawyer-tower’ set-up onhysteresis loops, Integrated Ferroelectrics: An International Journal, 10:1-4, 205-214, DOI:10.1080/10584589508012277

To link to this article: http://dx.doi.org/10.1080/10584589508012277

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Intrgruted E'erroelertric.s. 1995. Vol. 10. pp. 205-214 Reprints available directly from the publisher Photocopying permitted by license only

0 1995 OPA (Overseas Publishers Association) Amsterdam B.V. Published in The Netherlands

under license by Gordon and Breach Science Publishers SA

Printed in M:ikiv\i;i

EFFECT OF THE SENSING CAPACITANCE IN A 'SAWYER- TOWER' SET-UP ON HYSTERESIS LOOPS: MODEL CALCULATIONS AND SrBi2Ta209 EXPERIMENTAL RESULTS

PETER ZURCHER, R.E. JONES, JR., PEIR CHU, TOM LII, and SJ. GILLESPIE Materials Research and Strategic Technologies, Motorola Austin, Texas 78721, USA.

BO JIANG, and JACK C. LEE Microelectronics Research Center, University of Texas, Austin, TX 78712

Abstract It is well known that, for a given ferroelectric capacitor, the tilting of the hysteresis loops and the amount of remanent polarization measured in a 'Sawyer Tower' set-up are dependent on the sense capacitance (or load). However, it is less intuitive that a small sense capacitance will cause horizontal loop shifts and that these shifts depend on the state of the ferroelectric capacitor before the measurement. Since typical ferroelectric non-volatile memories operate with small sense-to-bit capacitance ratios, it is important to have models that can predict such effects. Complicated experimentation is necessary to implement the load and initial state effects properly in a load-line model. In contrast, the numerical ferroelectric capacitor model does not require any special experimentation to predict such effects. Experimental results from SrBizTa209 are compared with both models.

(Received Murch 22, 1995; in final forin April 22, 1995)

INTRODUC TION

The design of ferroelectric non-volatile memories requires improved, fast, and practical models to interface with existing circuit design tools. Ferroelectric capacitor models based on materials and device parameters are important to understand the effect of microstructure, composition, mobile and fixed charge distributions, and interaction with capacitive and resistive circuit elements. First successful approaches in this direction were taken by S.L. Miller, et ai.*3 and by P. Zurcher and D. Gealy 3. Both models are based on a simple layered capacitor structure. Miller, et al. have separated the ferro/load problem into a layered ferroelectric capacitor and a combination of circuit elements. In contrast, Zurcher and Gealy have combined ferroelectric and series-load capacitors into one model based on Gauss-Loop equations (hereafter called GL-model) and have taken advantage of the computing power of today's Pc's (486, Pentium) to generate a self-consistent numerical solution through iteration of a system of electromagnetic equations describing the layered capacitor structure.

The current publication will focus on the load/ferroelectric capacitor interaction in a Sawyer-Tower measurement set-up and compare experimental results from SrBi2Ta2Og (SBT) with two models, the GL-model and a load-line model. The following three main effects of linear series loads on the hysteresis

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206 PETER ZURCHER, et al.

response will be investigated using these two models: (1) the tilting of the loops and the reduction of remanent and non-volatile polarization with decreasing load, and (2) the voltage axis shifts of subsequent loops with different initial states. These effects are shown in Figure 1.

Is

T \ lo V I ? 5

B o 3 i -5 g -10

-15

LOAD = 1.2 la

.-.. .:.. r . l , . . . . : ,,., ,: r,.,;... r . . i . .

. . . .I....). ..... ....*.+,I C

. l i . . 1 1 1 . I

-2 0 2 -2 0 2 -2 0 2

FIGURE 1 Effect of a decreasing load capacitance on a Sawyer-Tower hysteresis loop measurement.

APPLIIDBIAS [Vl

EXPERIM ENTAI,

Process Det ails Ferroelectric capacitors were prepared by spin-coat and firing of metal-organic decomposition (MOD) deposited ferroelectric films of SrBizTa209. The anneals were in an oxygen atmosphere at temperatures between about 550 OC and 850 OC for times between thirty minutes to two hours. These anneals are required to crystallize the film into the desired crystal structure and to recover ferroelectric properties after etch processes during the integration of the capacitors into CMOS circuits. SBT has a bismuth oxide layered perovskite structure 4. Platinum was used for the ferroelectric capacitor electrodes because of its resistance to oxidation during the required oxygen anneals. The SBT capacitors shown here have been processed through aluminum metallization.

Electrical Characterization Since ferroelectric capacitor cells in memory applications are exercised by single pulses, it is important to use pulse measurement techniques to characterize discrete ferroelectric capacitors. The polarization measurements are made using a Sawyer- Tower configuration where an electric signal is imposed on a ferroelectric capacitor in series with a variable load capacitor as shown in Figure 2a. By applying the pulse train shown in Figure 2b, we collect a single pulse switching hysteresis loop (1) originating from a negative initial state and a corresponding loop (2) originating from a positive initial state. Between pulses, the potential is held at zero for times long enough (approx. 10 sec) for the linear load capacitor to completely leak to zero potential, and for the ferroelectric capacitor to undergo a short-time relaxation. Figure 2c shows this relaxation, the frequently reported remanent polarization, 2Pr, and the non-volatile polarization, Pnv, which is directly related to the electrical signal available for logic state sensing.

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SENSING CAPACITANCE IN A SAWYER-TOWER SET-UP 207

The experimental data shown here are obtained from 102x102 pm2 capacitors, measured with a loowHz triangular wave beginning and ending at OV, hence all hysteresis loops presented here start at the potenriacharge origin. The load capacitors are varied from 0.33nF to 10nF. For ease of visual loop comparison, all loops are displayed centered about the charge origin.

(a)

Teet Relaxation

Relaxation

4 - 2 - 1 0 1 2 s Voltage 0

FIGURE 2 (a) Sawyer-Tower set-up used for the hysteresis loop measurements. (b) Pulse sequence applied to generate the hysteresis response. (c) Experimental hysteresis loops, plotted from pulses 1 and 2, showing remanent polarization, Pr, non-volatile polarization, Pnv, and relaxation.

Numerical Self-Consistent Ferroelectric Capacitor Model Our numerical GL-model uses a system of series-layers within the ferroelectric capacitor to describe the materials parameter distributions found in a polycrystalline ferroelectric thin film capacitor (see Figure 3). The adjustable parameter distributions are the coercive field, &, the spontaneous polarization, Ps and the permittivity, E. The weight of each layer (&i, Pg, and Ei combination) is determined by the thickness of the layer, where the sum of all layer thicknesses is kept constant equaling the actual thickness of the capacitor under investigation. A thin linear gap layer is added at each electrode interface 5, that will accommodate the compensating electric field necessary to maintain ferroelectricity after the external potential is returned to zero.

This layered structure is merely a convenient mathematical representation of the materials parameter distributions mentioned above and does not allow a proper treatment of charge distributions inside the ferroelectric capacitors. A proper treatment of charged interface layers, charge gradients, and mobile charges requires a modification of this series-layer structure into a combination of interacting parallel and series layers. ItJs important to point out that all GL-model results shown in this paper are caused by ferroelechicity and not by fixed internal charge distributions.

The stack of series layers is extended by a metal layer and a linear load capacitor layer. The load capacitor is dimensioned such that its capacitance equals

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208 PETER ZURCHER, et al.

the load capacitance in the Sawyer-Tower measurement set-up. The metal layer is generated by a layer with a permittivity Em >> Ei of the capacitor stack layers.

System of Gauss Surfaces m.... .... . - - -

..... .. . .

Ferroelectric Capacitor LoadBitline Capacitor

FIGURE 3 Layered capacitor structure consisting of a linear layer, El, several ferroelectric layers, &2 to Q, metal electrodes El to E3, and a load capacitor ferroelectric layers represent the materials parameter distributions, E, Ec, and Ps, commonly found in poly-crystalline thin films. The total thickness and area are taken to be identical to the capacitor being measured and modeled. A system of Gauss surfaces is used to solve this series-capacitor problem.

It is well accepted that the operation of ferroelectric memory cells can be modeled as a simple capacitor divider with the ferroelectric capacitor in series with a capacitive load (see Figure 3). However, integrated memories do not operate in the large load limit, hence there are significant voltage drops across the capacitive load as well as polarization reversals after the 'read' potential returns to zero. Our GL-model makes no assumption as to how much of the applied potential is dropped across the ferroelectric capacitor, nor how much load-induced polarization reversal occurs since these properties are explicitly calculated. Also, the effect of the degree of polarization of the capacitor on the subsequent pulse response, as readily observed in pulsed experiments, is taken into account by the model 3.

Each layer (Figure 3) is described by a Gauss-Loop equation (Es. 1). All these Gauss-Loops close through one metal electrode and the corresponding equations are coupled through the common charge (Q A1) on the metal electrode as well as the integration of the electric field between the electrodes where the external potential is applied (Eq. 2). The metal electrode between the ferroelectric

used for the numerical ferroelectric capacitor model. The

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SENSING CAPACITANCE IN A SAWYER-TOWER SET-UP 2 0

and the load capacitor is modeled as a linear layer with infinite permittivity, leading to zero electric field within this layer. This leads to a system of linear equations that is solved simultaneously for the electric field inside each layer, Ei, and the total charge density, 6, on the electrodes. The corresponding matrix equation (see Figure 4) is solved by LU-decomposition and Crout's algorithm 6.

X

FIGURE 4 Matrix equation to be solved for each Vbia and polarization state, Ps2 to Psi, of the ferroelectric capacitor. This equation assumes identical areas for the ferroelectric and load capacitors, A1 = A2.

The hysteresis behavior of the ferroelectric capacitor is implemented through an interactive self-consistent process. For each incremental bias step this involves : (1) comparing the electric field in each layer with the coercive field of the corresponding layer, and (2) adjusting the spontaneous polarization in the appropriate layers in incremental steps such that the resulting electric field becomes equal to or smaller than the corresponding coercive field. This last process is rather complex and varies in its detailed execution whether one follows an increasing (positively or negatively) or decreasing bias branch, and whether the capacitor electric fields are below the coercive field distribution, within the range of coercive fields, i.e. during switching of domains, or whether the capacitor layers are saturated or not. Since this adjusting of the capacitor layer polarizations for a given bias change is a multi-variable problem, a simplified analytical solution is used to generate a best-guess first solution for the new individual layer polarizations. This ensures that one finds a physically meaningful solution and greatly reduces the time to reach convergence.

Generating the correct initial state for a pulse calculation in a Sawyer- Tower type circuit occurs through the following processes: While the applied potential across the series pair is returned to zero during the previous pulse, the potential across the ferroelectric capacitor reverses causing some polarization reversal. The smaller the load, the larger the polarization reversal. This is the main source for the reduction in the observed rernanent and non-volatile polarization when measured with smaller load capacitance. During the wait time between two pulses, the potential across the load capacitor leaks to zero. The corresponding change of the potential distribution across the ferroelectric / gap- layer stack causes a readjustment of the ferroelectric capacitor layer polarizations leading to the correct initial state for the next pulse. The GL-model incorporates these processes into the multi-pulse calculations 3-

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210 PETER ZURCHER, et al.

Currently, fitting of experimental hysteresis loops is done by developing empirical materials (Ec, Ps , E) parameter distributions. However, more 'scientifically correct' distributions will be investigated and reported elsewhere. Generally, three hysteresis loops measured to biases at below the coercive field, at approximately mid-switching, and at saturation are used to determine the distributions of coercive fields, spontaneous polarizations, and permittivities. Good fits to hysteresis loops with maximum excursions of 1.0, 1.5, and 3.0V generally assure good fits to loops from 0.5V and up. The data shown in Figure 5 have been fitted using 24 ferroelectric layers and 1 linear gap layer. The materials parameter distribution used covers the following ranges: Ec from 5 to 108 kV/cm, Ps from 4 to 13.5 pC/cm2, and E from 202 to 450.

18, I

FIGURE 5 Comparison between experimental high-load SBT hysteresis loops and the corresponding GL-model fits to l.OV, lSV, and 3.0V loops. The empirical materials parameter distributions used are & from 5 to 108 kV/cm, Ps from 4 to 13.5 pC/cm*, and E from 202 to 450. The large relaxations in the experimental data are not consistent with load induced relaxation and might be due to processing damage to the SBT thin films.

After this initial fit to the experimental data is completed, no additional parameter adjustments are done for any future modeling of experimental results obtained from capacitors from the same lot and processing step, but measured with different loads. Figure 6 shows the load induced slanting of the hysteresis loops, the initial state dependent horizontal loop shifts and the asymmetric relaxation due to the pulse history applied to the ferroelectric capacitor. Separation of processing induced intrinsic materials relaxation from initial state, pulse history, and load effects is complex and has not been attempted for the data presented here. Note how well the load induced slanting and loop shifts are reproduced by the calculated hysteresis loops. However, the relatively large discrepancy in charge on one side of the hysteresis loop is unexpected. It occurs on the leading, switching 'one-half period' of the displayed loop. This could be due to a discrepancy between the calculated pulse sequence and the measured pulse sequence.

The Load-Line Ferroelectric Model Load-line models are commonly used in engineering applications to calculate the potential drop and charge in a series combination of non-linear capacitors of known charge-voltage characteristics. In order to apply this model to ferroelectric capacitors, the high-load-limit hysteresis behavior of the ferroelectric capacitor has

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SENSING CAPACITANCE IN A SAWYER-TOWER SET-UP 21 1

10 , I I

-3 -2 -1 0 1 2 3

Applied Bias (V) Applied Bias 0 FIGURE 6 Comparison of experimental low-load hysteresis loops 1 and 2 with the corresponding GL-model loops. 'Ihe discrepancy in the leading switching 'half-period' is unexpected and indicates a possible difference between the measured pulse sequence and calculated pulse sequence.

to be known for a range of applied bias potentials. The mapping principle of the load-line model is demonstrated in Figure 7. For every load and maximum applied bias combination, the correct high-load-limit loop has to be determined experimentally. Once this is done, this family of intrinsic hysteresis loops serves as the parameter base for calculations of switching and non-switching charges, as well as load induced loop shifts.

1

FIGURE 7 Graphical representation of the load-line model. On the right, using the high-load test loop, the construction of a loop (dots) measured with a load capacitance C1 is shown. The dashed line shows the asymmetric correction to the high-load loop required when the capacitor is modeled from a negative initial state. The left side shows the voltage drop across the ferroelectric and the load capacitor for an applied bias voltage of Vo. Two different load lines, C1 and C2, demonstrate the increased loop shift in positive direction with decreasing load capacitance for a negative initial state capacitor.

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212 PETER ZURCHER, et al.

A first complication arises due to the initial polarization state of a capacitor to be modeled. Polarized capacitors generate hysteresis loops that are not centered with respect to the charge zero, hence an asymmetric high-load loop is required for the complete calculation of a low-load hysteresis loop. This is also required if one only wants to compare a switching with a non-switching signal for the modeling of a memory cell. The non-switching high-load loop has to be measured to a larger bias than the corresponding switching loop. Figure 7 also demonstrates why initially polarized capacitors are shifted when measured in a Sawyer-Tower set-up and why lower loads cause larger shifts. In the absence of imprint, independent of the load capacitance, unpolarized capacitors are actually not shifted at all. In the example shown in Figure 6, the capacitor left in a positive state shows a large relaxation almost to the point where it appears unpolarized, hence the corresponding hysteresis loops show almost no shift.

A second complication comes from the fact that an initial state generated with a high load differs from an initial state generated with a low load since the higher load results in a higher voltage across the ferroelectric capacitor. Thus if the load line model is used to predict a hysteresis loop with a low load from a high load hysteresis loop, then the high load hysteresis loop measurement should be made with the initial state set using the low load. Figure 8 shows the five-pulse test sequence used in our experiments. Data from the second and fourth pulses, labeled 1 and 2 are displayed as hysteresis loops. Normally, this five-pulse

10 nF Initial State

HGURE 8 Top: Regular pulse sequence used to measure a ferroelectric capacitor in a Sawyer-Tower set-up with, e.g. a 10 nF load. Bottom: Pulse sequence used to generate the correct capacitor initial state for the high-load hysteresis loops 1 * and 2* used for predicting the 1.2 nF load hysteresis loops.

sequence is measured with the same load capacitor. However, using the asymmetric high-load loops 1 and 2, the load-line model over-estimates the loop shifts, as shown in Figure 9a. If the initial state for the high-load test loops 1* and 2* is set with the correct low load, as illustrated in the lower part of Figure 8, the load-line model generates a very good fit of the measured low-load hysteresis loops (see Figure 9b). The discrepancy in the polarization charge at the maximum applied bias is most likely due to some undetermined parasitics in the measurement set-up. Figure 9c gives a direct comparison between the experimental hysteresis loops for a 10 nF and a 1.2 nF load capacitance.

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SENSING CAPACITANCE IN A SAWYER-TOWER SET-UP 213

FIGURE 9 (a) Comparison between experiment and load-line model when a high-load initial state is used for the measurement of the high-load test loop. (b) Improvement of the load-line model fit when a low-load initial state is used. (c) Comparison between high load and low load experimental hysteresis loops.

CONCLUSIONS

It is quite clear that some form of load-line model is certainly adequate for specific circuit simulations where the pulse sequence for a cell access operation is simple, The necessary experimentally determined switching and non-switching curves can be modeled by an analytical equation or represented by look-up tables when included in the load-line model. This model can then be easily implemented into circuit simulation tools such as SPICE. However, the load-line model is limited to the set of experimentally determined hysteresis loops and can not predict the response of the capacitor to any arbitrary pulse sequence.

In contrast, the numerical ferroelectric model overcomes such shortcomings and can predict the outcome of any arbitrary pulse sequence. The GL-model can also be used to predict the effects of changes in the coercive field, spontaneous polarization, and permittivity distributions of the ferroelectric material, or changes in non-ferroelectric internal linear gap layers, all effects that could occur during extensive electrical stress of the capacitor.

ACKNOWLEDGMENTS

We would like to thank V. Lopez, S. Revels, D. Cadena, M. Welsh, G. Etherington, L. Lilly, and K. Winters for their technical assistance.

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Dressendorfer, JJDD~. Phvs,, 68,6463 (1990).

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Peter Zurcher and F.D. Gealy, hoc . of Conference on Software for Electrical E n e i n d n e Analysis and Des ien, Southhampton, UK, July 1993, p. 412. B. Aurivillius, b k i v Kemi, 1,463 (1950); 1,499 (1950); 2,519 (1951). B.V. Selyuk, Soviet Physics Solid State, 8,2803 (1967). W.H. Press, B.P. Flannery, S.A. Teukolsky, and W.T. Vetterling, m e r i c a l Reciues in C, (Cambridge University Press, Cambridge, 1989), p. 28.

2849 (1991).

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