egr240 d5.1 basiclogicgates info

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Basic Logic Gates

Discussion D5.1

Section 8.6.2Sections 13-3, 13-4



Basic Logic Gates

and Basic Digital Design

• NOT, AND, and OR Gates

• NAND and N! Gates

• De"o#gan$s %&eo#e'

• ()clusi*e-! +! Gate

• "ultile-inut Gates



N% Gate -- /n*e#te# X Y

01

10



• Y = ~X (Verilog)

• Y = !X (ABEL)

• Y = not X (VHDL)

• Y = X’

• Y = X• Y = X (textook)

• not(Y,X) (Verilog)

N%



N%

X ~X ~~X = X

X ~X ~~X

0 1 0

1 0 1



AND GateAND

X

Y

Z

Z = X & Y

X Y Z

0 0 0

0 1 01 0 0

1 1 1



• X & Y (Verilog " ABEL)

• X and Y (VHDL)

• X Y

• X Y

•X # Y

• XY (text$ook)

• and (Z%X%Y) (Verilog)

AND

U

V



! Gate

'

X

Y Z

Z = X Y

X Y Z

0 0 0

0 1 11 0 1

1 1 1



!

• X Y (Verilog)

• X Y (ABEL)

• X or Y (VHDL)

• X * Y (text$ook)

•X

V Y

• X U Y

• or(Z%X%Y) (Verilog)



Basic Logic Gates


• N%, AND, and ! Gates

• NAND and NOR Gates






NAND GateNAND

X

Y

Z

X Y Z

0 0 1

0 1 11 0 1

1 1 0

Z = ~(X & Y)

nand (Z%X%Y)



NAND Gate

N+,AND

X

Y

Z

- = X & Y

Z = ~- = ~(X & Y)

X Y - Z

0 0 0 1

0 1 0 11 0 0 1

1 1 1 0

-



N! Gate

N'

X

YZ

X Y Z

0 0 1

0 1 01 0 0

1 1 0Z = ~(X Y)

nor(Z%X%Y)



N! Gate

N+,'

X

Y

- = X Y

Z = ~- = ~(X Y)

X Y - Z

0 0 0 1

0 1 1 01 0 1 0

1 1 1 0

Z-



Basic Logic Gates




• DeMorgan’s Theorem





NAND Gate

X

Y

X

Y

Z Z

Z = ~(X & Y) Z = ~X ~Y

=

X Y - Z

0 0 0 10 1 0 1

1 0 0 1

1 1 1 0

X Y ~X ~Y Z

0 0 1 1 10 1 1 0 1

1 0 0 1 1

1 1 0 0 0



De "o#gan$s %&eo#e'-1

~(X & Y) = ~X ~Y

• N% all *a#iales• &ange to and to • N% t&e #esult



N! Gate

X

YZ

Z = ~(X Y)

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

X

Y

Z

Z = ~X & ~Y

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 0

1 0 0 1 0

1 1 0 0 0



De "o#gan$s %&eo#e'-2

~(X Y) = ~X & ~Y

• N% all *a#iales• &ange to and to • N% t&e #esult



De "o#gan$s %&eo#e'

• N% all *a#iales

• &ange to and to

• N% t&e #esult

• --------------------------------------------

• 7 + 7 +

• + 7 + 7 • 7 + 7 +

• + 7 + 7



Basic Logic Gates





• Exclusive-OR (OR! Gate




()clusi*e-! Gate

X Y ZXOR

XY

Z 0 0 0

0 1 1

1 0 1

1 1 0

Z = X . Y

xor(Z%X%Y)



!

• X . Y (Verilog)

• X / Y (ABEL)

• X Y

• xor(Z%X%Y) (Verilog)

, 6 +te)t1oo9-⊕g



()clusi*e-N! Gate

X Y ZXNOR

XY

Z 0 0 1

0 1 0

1 0 0

1 1 1

Z = ~(X . Y)

Z = X ~. Y

xnor(Z%X%Y)



N!

• X ~. Y (Verilog)

• !(X / Y) (ABEL)

• X Y

• xnor(Z%X%Y) (Verilog)

, 6g e



Basic Logic Gates






• Multi"le-in"ut Gates



"ultile-inut Gates

Z1 2

3 4Z Z

Z



"ultile-inut AND Gate

Z1

utut is :/G: onl; i< all inuts a#e :/G:Z1

An oen inut =ill <loat :/G:



"ultile-inut ! Gate

utut is L> onl; i< all inuts a#e L>Z2

2Z



"ultile-inut NAND Gate

utut is L> onl; i< all inuts a#e :/G:Z3

3Z



"ultile-inut N! Gate

utut is :/G: onl; i< all inuts a#e L>Z4

4Z

egr240 d5.1 basiclogicgates info

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