Abstract — The effects of on-chip decoupling capacitors in the powersupply network of a CMOS test-chip on radiated noise are investigat-ed by surface scan measurements. The hardware set-up and the mea-surement procedure are briefly described. Applying the calibrationmethod, measurements of separate field components are given in absoluteform. This permits one to compare and interpret surface scan images ofthe electromagnetic field in terms of electric charge and current distrib-ution. The analysis of scanning results allows one to evaluate core opti-misation efficiency and discovery of parasitic effects within the chip.Finally, a short overview about the status of near-field scanning tech-niques and their challenges is presented.

I. INTRODUCTIONThe development of modern integrated circuits is determinedby a growing complexity, continuously rising clock-rates –internal clock rates are already in the GHz range – and a highlevel of integration. Due to the fast transition times requiredby the high clock frequencies, the transistors’ switching cur-rents produce a broadband noise spectrum which may spreadover the whole system, e. g. via the power supply system. Theseemissions can easily disturb other circuits in highly miniatur-ized systems, and accordingly, there is a great demand inresearch for control and minimisation of such unwanted noisesources and their emission [1]. Because of the tremendous com-plexity, pinpoint measurement of voltage or current on-chip isbecoming rather difficult, and moreover, a derivation of theoverall electromagnetic performance of a chip may not readilybe achieved from this kind of measured data.

In parallel to this situation, electromagnetic near-field scan-ning techniques for EMC applications are developed intensive-ly at many locations in the world because of their capability toprovide information on the distributed nature of the underlyingphysical phenomena. The goal of the investigations is toimprove the practical usability and extend the limitations ofnear-field scanning. In particular, the speed of data acquisitionand the accuracy required by measuring a vector field emittedby an arbitrary DUT, e.g. a PCB or chips, is a great challenge.By optimisation of the probing sensor and application of probecompensation algorithms, a spatial field distribution may bemeasured with high accuracy and resolution. This informationallows for a correct interpretation of the electrical behaviour ofthe DUT as well as determination of emission models as will beshown in section IV.

II. MEASUREMENT SYSTEMA near-field scanner with a resolution high enough to reproducethe fields above the integrated circuit’s package was adapted tothe problem of chip analysis by K. Slattery [2]. Presently, manyresearch labs involved in the study of chip-level EMC are nowusing near-field scanners based on this design. The basic scannersystem consists of measurement probes, mechanical positioningunit, pre-amplifier and a spectrum analyser [3]. In order to obtainthe results presented here, a 3D near-field scanner was used formeasuring the magnitude of the components of the electromag-netic field within a plane at a given height above the DUT (Fig-ure 1), the used probes, monopole and loop antennas, allow oneto measure the components of the electromagnetic field separate-ly in a Cartesian coordinate system, i.e. Ez, Hx, and Hy.

In order to calibrate the probe’s transfer function, a 3D fullwave simulation of special calibration structure was used as refer-ence. The computed field strength was compared to detected sig-nal level in order to obtain a frequency dependent antenna factor

AFM( f ) = 20 · logM( f )

UM( f )[dB/m]M ∈ [E, H] (1)

with f the frequency, UM the measured voltage, and M themagnitude of either the simulated electric or magnetic fieldstrength at the location of the probe.

The AF is a unique function for every probe and measure-ment set-up and accounts for the insertion loss of the cables, thepre-amplifier gain, and for the frequency response of the spec-trum analyser. This calibration allows one to measure the mag-nitude of the field strength with a spatial resolution roughlylimited by the dimensions of the probe.

III. MICROELECTRONIC TEST CHIPThe CESAME test chip [4] made in 0.18mm CMOS technolo-gy has specifically been designed for investigations of different

68 ©2006 IEEE

Electromagnetic Near-Field Scanning for Microelectronic Test Chip InvestigationAdam Tankielun1, Uwe Keller2, Etienne Sicard3, Peter Kralicek4, Bertrand Vrignon5

1 University of Paderborn / Fraunhofer IZM, Germany, tankielun@pb.izm.fhg.de

2 Zuken EMC Technology Center, Germany, uwe.keller@ieee.org3 INSA Toulouse, France, etienne.sicard@insa-toulouse.fr4 pkralicek@web.de5 STMicroelectronics, France, bertrand.vrignon@st.com

Fig. 1. Close-up of measurement station

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techniques improving the electromagnetic interference (EMI)performance. The chip consists of six blocks of core logic asindicated in Figure 2, which possess the same functionality butare equipped with different noise reduction strategies. Themain goal of the chip is to evaluate the noise reduction effi-ciency for each technique implemented by simulations and atthe same time to allow a validation of the predicted results bymeasurements. The test chip is mounted on a standardized testboard, which permits the measurement of radiated (TEM celland surface scan methods) as well as conducted (1 Ω method)emissions [5].

The core of the CESAME test chip has a hierarchical struc-ture with a clock tree (Figure 3). The smallest element of thisstructure, the so-called BASECELL, consists of inverters,NAND gates and flip-flops taken from standard STMicroelec-tronics libraries. This structure is repeated 20 times in order togenerate BASEX20, which is again repeated 12 times to buildCORELOGIC. This description is valid for all six-core logicsblocks.

The focus of this paper is to study the difference in fieldemission characteristics of the IC between the NORM (non-optimised) and the RC (optimised) core. The RC core containsadditional on-chip polysilicon capacitors (C≈950pF) placednear each BASEX20 cell, connecting power (Vdd) and ground(Vss) lines. Accordingly, the area of the RC core is about 25%larger than one of the NORM. The capacitors supply a high fre-quency current required during the internal switching activitiesof the transistors. Hence, the current loops are very small result-ing in a lower emission level anticipation.

The difference between the two core blocks may be explainedwith the help of the schematics shown in Figure 4, which cor-respond to the ICEM draft standard [6] for modelling conduct-ed and radiated emissions. From left to right (Figure 4), themodel consists of a core DC supply VDC and the equivalentinductances Lvdd, Lgnd, accounting for supply network, pack-age and bonding. Also, the on-chip decoupling capacitance Cd,the on-chip LC network (Lvdd_die, Lvss_die, Rvdd_die,

Rvss_die) providing the access to the core, and the current gen-erator itself (ISource) with its local decoupling, Cb, are part ofthe model. All other parasitic parameters for the package as wellas the printed circuit board are ignored.

As can be seen on the right side of the schematic diagram, thecurrent sources ISource are identical for NORM and RC core. Themain difference concerns the serial resistance (Rdd_die, Rvss_die)and the local decoupling capacitance Cb. The access inductance ofthe package is almost the same for RC and NORM cores, as thecores were implemented in a very similar way. In the case of theNORM core, the capacitance Cb is mainly the parasitic couplingcapacitance between the Vdd and Vss rails that are routed insidethe core, added to numerous Vdd/Vss junction capacitances thatexist in all basic CMOS logic cells. The value of Cb at a supplybias of 0V is determined by layout extraction tools. It has beenobserved that Cb is usually underestimated, as compared to itsequivalent value with nominal supply voltage. Good correlationsbetween current simulated spectrum and on-chip measurementon Rvdd_die have been obtained [4]. Although very simple, themodel is within 10dB of the measurement up to 1GHz.

©2006 IEEE

Fig. 2. Core logic of CESAME chip

Fig. 4. Schematic diagram of the NORM Core (upper Fig-ure) and RC core (lower Figure) first-order models

Fig. 3. Hierarchical structure of CESAME core logicFig. 5. X-ray photograph of CESAME package with desig-nation of important pins

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IV. ELECTROMAGNETIC NEAR-FIELDRESULTSIn order to simplify the interpretation of the obtained elec-tromagnetic field scans, a correlation to current and chargedistributions may be established. Based on the MagneticField Integral Equation, the tangential magnetic field withina plane may be mapped onto an equivalent surface currentdistribution [7]. Similarly, it is intuitively clear that underthe assumption of near-field conditions the electric field isdue to an equivalent charge distribution. Hence, in the fol-lowing, the focus will be on the normal electric as well as onthe tangential magnetic field. The magnitude Ht of the lat-ter may be determined from near-field scans of the Hx and Hycomponents

(2)

Indices m and n refer to the measurement point locationwithin an equidistant grid covering the scanned area. For theinvestigations the distribution of the electromagnetic field wasrecorded at a height of 2 mm above the board within a squareplane of 40 mm edge length every 1 mm.

Below, the images of the electromagnetic fields measuredat the first and third clock harmonic frequency are presented.Only one core (NORM or RC) was active during a single fieldscan. The clock frequency was set to 40 MHz and the coresoperated at their highest gate switching activity. To simplifyevaluation, the measured quantities were interpolated and theresulting images are presented in pairs and in the same mag-nitude scale.

According to Figure 5, both cores use separate power supplyfeeds. The NORM core supply is at the lower edge close to theleft corner, while the RC core is supplied via pins at the rightedge near the upper corner. This may also be noticed in thedistribution of the tangential magnetic field for both, NORMand RC core, shown at the fundamental of the clock frequency

in Figure 6. The dimensions of the CESAME test chip aremarked by the black frame, the dot reveals the orientation ofthe chip.

The maximum of the tangential magnetic field may clearlybe attributed to the supply in both cases. However, the highmagnetic field distributed in other areas of the package evidencesthat not the whole supplied current finds its way back throughthe corresponding GND pins of CESAME. This provides theexplanation to an unbalance in magnitude in the Vdd and Vsscurrents observed by on-chip sensors and reported in [4].

The high conductivity of the chip substrate enables parasiticcoupling between active and non-active power supply networkswhich can be identified as a substrate current coupling (SSC)effect. The effect may lead to high radiation field levels due tounwanted current loops of large area. Moreover, in particular themeasurements obtained for the RC core disclose a much bettercurrent isolation from the other ground systems in the chip,while for the NORM core, high current is flowing in all GNDpins except for pin 6 in Figure 5, which is a GND isolated withN buried layers in the substrate from the rest of the chip, lim-iting SSC effect.

The distribution of the normal of the electric field at the fun-damental of the clock frequency looks very similar for both cores(Figure 7). The high electric field is seen to be focused in thearea of the clock line, which is the same for both chip cores. Theload impedance for the clock signal must be considerablebecause of the large electric and low magnetic field in this area(Figure 6). On the other hand, the load impedance for the powersupply is quite small due to the very low electric field to benoticed in the bottom left corner for the NORM core and in theupper right corner for the RC core.

The effect of the optimisation introduced into the RC coreis best seen in Figure 8 showing the magnetic field distribu-tion at 120 MHz, the third harmonic of the clock. For theNORM core the high frequency current is spread to off-chipcircuitry. The magnetic field distribution is basically the same

70 ©2006 IEEE

Fig. 6. Tangential magnetic field distribution; fclock = 40MHz; fmeas = 40 MHz; left NORM core, right RC core

Fig. 7. Normal electric field distribution; fclock = 40 MHz;fmeas = 40 MHz; left NORM core, right RC core

Fig. 8. Tangential magnetic field distribution; fclock = 40MHz; fmeas = 120 MHz; left NORM core, right RC core

Fig. 9. Normal electric field distribution; fclock = 40 MHz;fmeas = 120 MHz; left NORM core, right RC core

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as the one for the fundamental of the clock signal. According-ly, the current attributed to the third harmonic is spreadthroughout the same off-chip loop, resulting in a large currentloop that is closed outside the IC and thereby causing higheremission. For the RC core, there obviously is only a low levelhigh frequency current drawn almost solely via the power sup-ply lines. Therefore, it is concluded that the applied on-chipcapacitors in the case of the RC core eliminate the content ofthis harmonic in the off-chip loop, resulting in an emissionabout 20 dB lower than the NORM core. Similar emissionimprovement was reported according to 1 Ω measurementmethod where the relations in the current magnitude spectraand the tangential magnetic field agreed very well both forNORM and RC cores [3].

The normal component of the measured electric field atthe third harmonic, 120 MHz, for both the operation of theNORM and RC core, is shown in Figure 9. A big chargedensity gathered on almost all transmission lines may benoticed for the NORM core. This may be explained by thesimultaneous switching noise (SSN) phenomena as indicat-ed in Figure 10.

Due to the large current driven by the component solely viaits single supply path, a voltage drop occurs along the induc-tance of the supply path. This is lifting the on-chip ground ontoa different potential than the PCB ground. In turn, the majori-ty of the other interconnects are terminated by high impedancesand accordingly there is virtually no current flowing. This con-serves the potential lift also for the interconnects and explainsthe lively red distribution of charge fanning out from the dietowards the pads of the PCB. It may be noticed that the chargelevel is approximately the same throughout the correspondinginterconnects which evidences the low output impedance of thepassive buffers.

As can be noticed from Figure 9 for the RC core, charges areseen only above clock signal lines, indicating that the potentiallift does not occur in a similar extend as for the NORM core.However, the potential lift effect can be also noticed – deter-mined by yellow-green colour – for the RC core where the elec-tric potential is spread throughout the package on a level simi-lar to the one of the RC GND pin. However, since the overallcurrent is much smaller for the RC core, this effect is on a muchlower level altogether.

V. CONCLUSIONIn this paper, the benefits of using near-field scanning for char-

acterizing the electromagnetic field in the ambient of an inte-grated circuit were investigated in detail. The near-field distri-bution plots demonstrated that the integration of on-chipcapacitors into the RC core may well provide the chargerequired during the transistors’ switching process, and accord-ingly, reduces the relevant loop areas of high-frequent currentsresulting in a considerable decrease in parasitic emission of theCESAME test chip.

Moreover, the interpretation and the discussion of the mea-surement results provided greater insight into the major par-asitic effects and their distribution within the chip. In partic-ular, the cause of parasitic simultaneous switching noise andsubstrate current coupling could be discovered and localizedfor the chip.

Accordingly, on the basis of the near-field scans it is possi-ble to localize dominant current paths and areas of concentra-tion of electric charge. This may lead to an improved redesignof some of the DUT’s circuitry and mitigate emission sources(hot-spots), which may degrade its EMI performance. Conse-quently, any arbitrary test structure emitting time-harmonicfields can be characterized by this contact less measurementmethod.

The extensiveness and complexity of the questions stillrelated to near-field scanning encourages people toexchange their ideas and experiences. There is an initiativeto gather involved engineers into a Partnership for Testand Instrumentation in Near Field (PASTEUR) Society[8]. All interested readers are heartily welcomed to jointhis community.

REFERENCES[1] S. Hayashi, M. Yamada, 2000, “EMI-noise analysis under

ASIC design environment,” IEEE Transactions on Com-puter-Aided Design of Integrated Circuits and Systems,Vol. 19, No. 1, November 2000, pp: 1337–1346.

[2] K. P. Slattery, J.W. Neal, W. Cui, “Near-field Measure-ments of VLSI Devices,” IEEE Transactions on EMC, Vol.41, No. 4, November 1999, pp 374-384.

[3] A. Tankielun, P. Kralicek, U. Keller, E. Sicard, B.Vrignon, “Influence of Core Optimisation and Activityfor Electromagnetic Near-Field and Conducted Emissionsof CESAME Test Chip,” 4th International Workshop onElectromagnetic Compatibility of Integrated Circuits,Angers, France, April 2004, pp. 95-100.

[4] B. Vrignon, S.D. Bendhia, E. Lamoureux, E. Sicard,“Characterization and Modeling of Parasitic Emission inDeep Submicron CMOS,” IEEE Transactions on EMCvol. 47, No. 2, May 2005, pp. 382–387.

[5] International Electro-technical Commission “IEC 61967:Integrated Circuits, Measurements of Conducted andRadiated Electromagnetic Emission,” IEC Standard,www.iec.ch, 2005

[6] International Electro-technical Commission “IEC 62014-3: Models of integrated circuits for EMI behavioural sim-ulation,” IEC Standard, www.iec.ch, 2002

[7] C.A. Balanis, “Advanced Engineering Electromagnetics”John Wiley & Sons, 1989

[8] Partnership for Test and Instrumentation in Near Field(PASTEUR) Society, ww.eseo.fr/~mramdani/pasteur.html

©2006 IEEE

Fig. 10. Simultaneous switching noise phenomena inCESAME chip

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BIOGRAPHIESAdam Tankielun was born in Poland in1977. He received the master engineer degreein Microwave Engineering and OpticalTelecommunication from Technical Universi-ty of Gdansk, Poland in 2002. In years 2001-2003 he worked as an RF specialist at theMicrowave Systems Poland on construction of

military radio relay prototype. Since 2003, he is working at thecompetence network between the Fraunhofer Institute Relia-bility and Microintegration and the University of Paderborn,Germany. His research interests include development of near-field scanning techniques for EMC measurements.

Uwe Keller was born in Halle, Germany, onOctober 21. 1958. In 1993 he entered CAD-LAB, a joint venture between the Universityof Paderborn and the Siemens Nixdorf Infor-mationssystems AG, to work on the model-ling of radiated emissions of printed circuitboards. Since then he was involved in various

SI and EMC subjects. With the foundation of the branch lab ofthe Advanced System Engineering department of the Fraun-hofer Institute Reliability and Microelectronic in Paderborn,he was responsible for its EMC and SI research group. Sincebeginning 2005 he is working as principle engineer at theZuken EMC Technology Center. His main interests includeEMC, electromagnetic interference modelling, and numerics.

Etienne Sicard received the B.S degree in1984 and the PhD in Electrical Engineeringfrom the University of Toulouse, in 1987.He stayed 18 months at Osaka University,Japan, and one year as an invited professor atthe University of Balearic Islands, Spain.

Etienne Sicard is currently a professor at INSA of Toulouse,Department of Electrical and Computer Engineering. He wasa visiting professor at the electronic department of CarletonUniversity, Ottawa, in 2004. His research interests includeseveral aspects of CAD tools for the design and electromag-netic compatibility of integrated circuits. He is the author of10 books, software, and more than 100 technical papers inthese areas.

Peter Kralicek was born in Lippstadt, Ger-many in 1972. He received the degree in elec-trical engineering in 1997 from the Universi-ty of Paderborn. In 1998, he joined the com-petence network between the FraunhoferInstitute Reliability and Microintegration(IZM) and the University of Paderborn. Since

2004, he has worked at Robert Bosch GmbH in Schwieberdin-gen, Germany. His research interests include electromagneticcompatibility, numerical field computation, and modellingtechniques.

Bertrand Vrignon was born in Tours,France, on September 1979. He received anengineering diploma from ESEO, Angers,France in 2002, and a PhD in ElectronicDesign from the National Institute ofApplied Sciences, Toulouse, France, in 2005.His doctoral research was in cooperation

with STMicroelectronics, Crolles, France, where he character-ized low electromagnetic emission guidelines for integratedcircuits. In 2005, he joined Freescale Semiconductor,Toulouse, France, where he continued to work on EMC prob-lems. His research interests include several aspects of designmethodology to reduce emission and noise susceptibility ofdeep-submicron ICs.

©2006 IEEE

8th Annual Chicago EMCMiniSymposium

Tuesday, May 16, 2006Holiday Inn - Itasca, IL

860 West Irving Park Rd.

The Chicago IEEE EMC Society Chapteris presenting

our 8th MiniSymposium!

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exhibits.... contact Frank Krozel at 630-924-1600

EMCFest 2006A Colloquium and Exhibition on the

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Tuesday, May 2, 2006Canton Summit on the Park

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7:30 am - 8:30 am Registration8:30 am - 5:00 pm Technical Sessions

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Registration fees include one copy of the colloquium record,continental breakfast, a “networking” lunch and a “HappyHour” reception immediately following the Technical Ses-sions. Seating is limited; registrations will be confirmed inthe order received until space is full.

For further information: Kimball WilliamsPhone: 248-372-8074e-mail: k.williams@ieee.org

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