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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-1 A representation of the basic structure of the two types of JFET.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-2 A biased n-channel JFET.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-3 Effects of VGS on channel width, resistance, and drain current (VGG = VGS).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-4 JFET schematic symbols.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-5 The drain characteristic curve of a JFET for VGS = 0 showing pinch-off voltage.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-6 JFET action that produces the characteristic curve for VGS = 0 V.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-7 Pinch-off occurs at a lower VDS as VGS is increased to more negative values.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-8 VGS controlsID.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-9 JFET at cutoff.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-10 A biasedp-channel JFET.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-11

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-12 JFET universal transfer characteristic curve (n-channel).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-13 Example of the development of an n-channel JFET transfer characteristic curve (blue) from the JFET drain characteristic

    curves (green).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-14 JFET partial datasheet. 2003 Fairchild Semiconductor Corporation. Used by permission.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-15 gm varies depending on the bias point (VGS).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-16 Self-biased JFETs (IS ID in all FETs).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-17

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-18

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-19

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-20 A self-biased JFET and its transfer characteristic curve.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-21 The intersection of the self-bias dc load line and the transfer characteristic curve is the Q-point.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-22

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-23 An n-channel JFET with voltage divider bias (IS ID).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-24

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-25 Generalized dc load line (red) for a JFET with voltage-divider bias.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-26

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-27 Variation in the transfer characteristic of 2N5459 JFETs and the effect on the Q-point.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-28 The change inIDbetween the minimum and the maximum Q-points is much less for a JFET with voltage divider bias than

    for a self-biased JFET.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-29 Current-source bias.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-30 The ohmic region is the shaded area. The characteristic curves are straight lines with a slope of ID/VDS for small values ofID.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-31 The load line intersects the curves inside the ohmic region.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-32

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-33

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-34 Representation of the basic E-MOSFET construction and operation (n-channel).

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-35 E-MOSFET schematic symbols.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-36 Representation of the basic structure of D-MOSFETs.

    Fi 8 37 O i f h l D MOSFET

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-37 Operation of n-channel D-MOSFET.

    Fi 8 38 D MOSFET h ti b l

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-38 D-MOSFET schematic symbols.

    Figure 8 39 Cross section of conventional E MOSFET structure Channel is shown as white area

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-39 Cross section of conventional E-MOSFET structure. Channel is shown as white area.

    Figure 5-34 drain characteristic of n channel enhancement type MOSFET

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 5-34 drain characteristic of n-channel enhancement type MOSFET.

    Figure 5-35 Sketching the transfer characteristics for an n-channel enhancement type MOSFET from the drain characteristics

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 5 35 Sketching the transfer characteristics for an n channel enhancement type MOSFET from the drain characteristics

    .

    Figure 5-37 p-Channel enhancement-type MOSFET

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 5 37 p Channel enhancement type MOSFET

    .

    Figure 8-44 E-MOSFET general transfer characteristic curves.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    g g

    Figure 8-45 D-MOSFET general transfer characteristic curves.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

    Figure 8-46 Common E-MOSFET biasing arrangements.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.

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    Thomas L. Floyd

    Electronic Devices, 8e

    Copyright 2008 by Pearson Education, Inc.

    Upper Saddle River, New Jersey 07458

    All rights reserved.