embedded design flow xilinx university program. objectives after completing this workshop, you will...
TRANSCRIPT
Embedded Design Flow
Xilinx University Program
Objectives
After completing this workshop, you will be able to:
• Describe the various tools that encompass Xilinx Embedded Development Kit (EDK)
• Rapidly architect an embedded system containing an IBM PowerPC processor and Xilinx-supplied IP cores
• Create and Integrate your own custom peripheral• Develop and debug software applications with the
Eclipse-based Software Development Kit (SDK)
Introduction 2
Outline
The course consists of the following modules:• EDK Overview • PowerPC Hardware Design
– Basic Hardware System• Hardware Design Using EDK
– Adding IP to a Hardware Design• Adding Your Own IP to the System • Debugging with SDK
Introduction 3
PowerPC-Based Labs 1 through 6
Introduction 4
PPC
PLBBus
PLB2OPB
PLB BRAM Cntlr
OPBBus
PLB BRAM
PLB BRAM Cntlr PLB BRAM
INTC
GPIO
Timer
UART
MY IP
DIP SW
Push Buttons
LEDs
ICON
IBA
Embedded DevelopmentTool Flow Overview
EDK Intro 5
Data2MEM
Download Combined Image to FPGA
Compiled ELF Compiled BIT
RTOS, Board Support Package
EmbeddedDevelopment Kit
Instantiate the ‘System Netlist’ and Implement
the FPGA
?
HDL Entry
Simulation/Synthesis
Implementation
Download BitstreamInto FPGA
Chipscope
Standard FPGAHW Development Flow
VHDL or Verilog
System NetlistInclude the BSPand Compile theSoftware Image
?
Code Entry
C/C++ Cross Compiler
Linker
Load SoftwareInto FLASH
Debugger
Standard EmbeddedSW Development Flow
C Code
Board SupportPackage
12 3 Compiled BITCompiled ELF
EDK Intro 6
EDK Tool Flow
Simulation Generator
Hardware Platform Generation
Library Generation
Embedded SoftwareDevelopment
ISETools
IP Library or User Repository
MSS
LibGen
.a
Compiler (GCC)
.o
Linker (GCC)
ELF
MHS
PlatGenDrivers,
MDDMPD, PAO
PCoreHDL
System andWrapper VHD
system.BMM
Synthesis (XST)
NGC
NGDBuildUCF
NGD
MAP
NCD, PCF
PAR
NCD
BitGensystem.BIT
BitInit
download.BIT
iMPACT
system_BD.BMM
SimGen
BehavioralVHD Model
SimGen
StructuralVHD Model
SimGen
TimingVHD Model
Simulation
IP Models ISE ModelsTestbenchStimulus
CompEDKLib CompXLib
ApplicationSource.c, .h, .s
download.CMD
EDK SWLibraries
Xilinx Platform Studio (XPS)
EDK Intro 7
Merging Hardware and Software Flows
EDK Intro 8
data2MEM
download.bit
MicroBlaze™/PPC
UART
Arbiter
GPIO
Hardware Flow
SoftwareFlow
Merging Hardware and Software Flows
• Data2MEM – Update the bitstream– Input files → system_bd.bmm, system.bit,
executable.elf– Output file → download.bit– This invokes the BitInit tool, which initializes the
instruction memory of the processor– The instruction memory may be initialized with a
bootloop, bootloader, or an actual application – Now the hardware and the software flows come
together. This stage also calls the hardware and software flow tools if required
EDK Intro 9
Configuring the FPGA
• Download the bitstream– Input file → download.bit– This downloads the download.bit file onto the
target board using the Xilinx iMPACT tool in batch mode
– XPS uses the etc/download.cmd file for downloading the bitstream
• The download.cmd file contains information such as the type of cable is used and the position of the FPGA in a JTAG chain
EDK Intro 10
Glossary of Tools and Files
• A few of the files the EDK tools generate:– MDD = Microprocessor Driver Description– MHS = Microprocessor Hardware Specification– MPD = Microprocessor Peripheral Description– MSS = Microprocessor Software Specification– PAO = Peripheral Analyze Order– BBD = Black Box Definition– BMM = Block RAM Memory Map
EDK Intro 11
Glossary of Tools and Files
• Some of the EDK tools:– LibGen = Library Generator. Uses MSS file,
copies device drivers source files and generates software libraries for the defined system
– PlatGen = Platform Generator. Uses the MHS and MPD files to create an implementation netlist of a bus-based sub-system
– SimGen = Simulation Generator. Uses MHS file to configure and generate a simulation netlist pointing to various simulation model types, such as SWIFT, BFM, netlist, RTL, etc.
EDK Intro 12
MPD File
## MPD file created automatically for design OPB_SEMAPHORE BEGIN opb_pwm, IPTYPE=PERIPHERAL
## Parameter list for the generics
PARAMETER C_OPB_AWIDTH = 32, DT = integerPARAMETER C_OPB_DWIDTH = 32, DT = integerPARAMETER C_BASEADDR = 0xFFFF8000, DT = std_logic_vectorPARAMETER C_HIGHADDR = 0xFFFF80FF, DT = std_logic_vectorPARAMETER C_NO_CHANNELS = 4, DT = integerPARAMETER C_MAX_RESOLUTION = 16, DT = integer
OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL
BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE
entity OPB_PWM is generic ( C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFA000"; C_HIGHADDR : std_logic_vector := X"FFFFA0FF"; C_NO_CHANNELS : integer range 0 to 15 := 4; C_MAX_RESOLUTION : integer range 4 to 32 := 16 );
Parameters override generics in VHDL
Microprocessor Peripheral Definition file provides default parameter settings in XPS
## Port list for the signals ## Global signalsPORT OPB_Clk = "", DIR = in, SIGIS=CLK, BUS=SOPBPORT OPB_Rst = OPB_Rst, DIR = in, BUS=SOPB## OPB signalsPORT OPB_ABus = OPB_ABus, DIR = in, VEC = [0:31],
BUS=SOPBPORT OPB_BE = OPB_BE, DIR = in, VEC = [0:3], BUS=SOPBPORT OPB_RNW = OPB_RNW, DIR = in, BUS=SOPBPORT OPB_select = OPB_select, DIR = in, BUS=SOPBPORT OPB_seqAddr = OPB_seqAddr, DIR = in, BUS=SOPBPORT OPB_DBus = OPB_DBus, DIR = in, VEC = [0:31],
BUS=SOPBPORT PWM_DBus = Sl_DBus, DIR = out, VEC = [0:31],
BUS=SOPBPORT PWM_errAck = Sl_errAck, DIR = out, BUS=SOPBPORT PWM_retry = Sl_retry, DIR = out, BUS=SOPBPORT PWM_toutSup = Sl_toutSup, DIR = out, BUS=SOPBPORT PWM_xferAck = Sl_xferAck, DIR = out, BUS=SOPB
PORT PWM = "", DIR = out, VEC = [0:C_NO_CHANNELS-1]END
MPD File
port ( -- Global signals OPB_Clk : in std_logic; OPB_Rst : in std_logic;
-- OPB signals OPB_ABus : in std_logic_vector(0 to 31); OPB_BE : in std_logic_vector(0 to 3); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic; OPB_DBus : in std_logic_vector(0 to 31);
OPB Bus Signals
PWM_DBus : out std_logic_vector(0 to 31); PWM_errAck : out std_logic; PWM_retry : out std_logic; PWM_toutSup : out std_logic; PWM_xferAck : out std_logic;
PWM : out std_logic_vector(0 to C_NO_CHANNELS-1) );
Slave Signals
Microprocessor Peripheral Definition file provides default connections in XPS
Review
• What is the MHS file? – The MHS file is the Microprocessor Hardware Specification; it
specifies processors, hardware peripherals, bus connections, and address spaces for the hardware
• What does the PlatGen tool do?– PlatGen takes the MHS file and creates the system and
peripheral netlists, HDL wrapper files, BMM file, etc.
• What tool is used to place executable code in an FPGA block RAM?– The Data2Mem tool will take the BMM file and create the
proper initialization for the block RAM that is assigned to the executable memory space
EDK Intro 15
Review
• What does the LibGen tool do?– Read MSS file and generate libraries
• What is the difference between system.bit and download.bit files?– The system.bit file contains only hardware description
whereas download.bit file contains both hardware description as well as executable software
EDK Intro 16
Where Can I Learn More?
• Tool documentation– Getting Started with the Embedded Development Kit– Processor IP Reference Guide– Embedded Systems Tools Guide– Xilinx Drivers
• Processor documentation– PowerPC Processor Reference Guide– PowerPC 405 Processor Block Reference Guide– MicroBlaze Processor Reference Guide
• Support Website– Tech Tips: www.xilinx.com/xlnx/xil_tt_home.jsp– EDK Website: www.xilinx.com/edk
Adding Your Own IP to the System
Overview
1. Peripherals are connected to the microprocessor by using the data and address buses
2. Xilinx has implemented IBM's CoreConnect bus architecture
3. On-chip Peripheral Bus (OPB) version 2.1 of the CoreConnect architecture is designed for easy connection of on-chip peripheral devices
4. Any custom peripheral that connects to the OPB bus must meet the principles of the OPB protocol and the requirements of the Platform Generator
BBD File
• The netlists are copied into the project/implementation directory• Example of a single file without options
– FILES– Blackbox.ngc
• Example of multiple file selections without options
– FILES– blackbox1.ngc, blackbox2.ngc, blackbox3.edn
The Black Box Definition (BBD) file identifies netlist files used for a user peripheral
File Usage
• There are two ways to integrate your own IP into XPS– As a blackbox
• Synthesized with XST or a third-party synthesis tool • Requires MPD and BBD
– As HDL• Synthesized with the rest of the processor system• Uses XST• Requires MPD and PAO
Example of a BBD Filewith multiple file selections
C_FAMILY C_RPM C_FPU_TYPE
FILES
virtex2 true full opb_fpu_full.edf
virtex2 true lite opb_fpu_lite.edf
virtex2p true full opb_fpu_full.edf
virtex2p true lite opb_fpu_lite.edf
virtex false full opb_fpu_full_noram32x1d.edf, ram32x1ds.edf
virtex false lite opb_fpu_lite_noram32x1d.edf, ram32x1ds.edf
Free Cores Included as VHDL Source with EDK (even more are now free)
Bus fsl, lmb opb dcr, ocm, plb, fcb
Bus Bridge opb2opb, opb2dcr, opb2plb fcb2fsl, plb2opb
Communication opb_spi hard_temac, plb_temac
Debug icon, iba, ila, vio, mdm Iba, jtagppc_cntlr
GPIO opb_gpio plb_gpio
Interrupt Controller opb_intc dcr_intc
Memory Controller mch_opb_ddr, mch_opb_sdram, opb_bram, opb_ddr, opb_emc, opb_sdram, opb_sysace
dsbram, isbram, pb_ddr, plb_emc, plb_sdram
Timer fit_timer, opb_timer, opb_timebase_wdt
Utility bus_split, flipflop, reduced_logic, vector_logic
Processor System Size
• The Processor IP Calculator is an online tool that helps you easily estimate the processor IP core size usage
• www.support.xilinx.com/ipcenter/processor_central/ppcip/calc.htm
• Try it out!!
CoreConnect Features
• IBM PowerPC embedded system
Features
• Platform Generator supports the following features for OPB peripherals, and it is a subset of the OPB v2.1 features– Fully synchronous single-clock edge
– 32-bit address bus, 32-bit data bus
– Single-cycle transfer of data between the OPB master and the OPB slave
– Supports master byte enables
– Supports slave timeout suppress, retry
– No three-state drivers required
• Note that the dynamic bus sizing feature is not supported in OPB v2.1
Physical Implementation
• The OPB bus architecture (v2.1) allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or the other existing peripherals
Physical Implementation
• The OPB bus architecture (v2.1) allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or the other existing peripherals
No don’t cares
Interface Signals
• Global OPB slave signals– Slave signals
• <Sln>_xferAck• <Sln>_errAck• <Sln>_toutSup• <Sln>_retry• <Sln>_DBus
– OPB bus signals• OPB_select• OPB_RNW• OPB_BE• OPB_seqAddr• OPB_Abus• OPB_DBus
OPBSlave
OPBBus
Logic
<Sln>_xferAck
<Sln>_errAck
<Sln>_toutSup
<Sln>_retry
<Sln>_DBus
OPB_select
OPB_RNW
OPB_BE
OPB_seqAddr
OPB_ABus
OPB_DBus
Create/Import Peripheral Wizard• The wizard helps you create your own
peripheral and then import it into your design • The wizard will generate the necessary core
description files• The user peripheral can be imported directly
through the wizard by skipping the creation option– Ensure that the peripheral complies with Xilinx
implementation of the IBM CoreConnect Bus Standard
Adding IP 30
Starting the IP Wizard
Adding IP 31
The Create and Import Peripheral Wizard can be started after creating a project and using Hardware Create or Import Peripheral … or opening an existing project or using Start Programs Xilinx Platform Studio 8.2i Accessories Create and Import Peripheral Wizard
Software Development
GNU Tools
• Calls four different executables– Preprocessor (cpp0)
– Language specific c-compiler• cc1 C-programming language• cc1plus C++ language
– Assembler• mb-as (MicroBlaze processor)• powerpc-eabi-as (PowerPC
processor)
– Linker and loader• mb-ld (MicroBlaze processor)• powerpc-eabi-ld (PowerPC
processor)
Software Design 33
Exceptions and Interrupts
Software Design 34
Entry Point
Save State
Call Handler
Restore State
Return to Program
Exception Code
HANDLER
Registered Handler
Timer Facilities
• Features:– Time base– Fixed Interval Timer (FIT)– Programmable Interval Timer (PIT)– Watchdog timer– These timers share the same time-base clock frequency
• Uses:– Time-of-day– Data logging– Peripherals requiring periodic service– Recover from faulty hardware or firmware
Software Design 35
What is a BSP?
• Board Support Package (BSP):– A set of software modules combined into the
“libxil.a” library
– Allows you to use the low-level PowerPC processor core functions
• Enable, disable, and flush caches
• Read/write time-base registers
– Allows you to use IP peripheral-device drivers• GPIO, PCI controller, UART,…
– Offers glue functionality to link code against standard libraries: Time, sleep, Files, Memory
Software Design 36
PowerPC Processor Boot Files
• Files: boot.S, boot0.S, crt0.S, eabi.S– Application entry point at label _boot in
boot.S– _boot is single jump instruction to _boot0 – _boot0 is a few instructions that do a jump
to _start in crt0.S– _start
• Clears .bss and .sbss sections• Sets up stack on an eight byte alignment• Initializes time-base registers to zero• Optionally, enable FPU bit in MSR• Calls main()
– Calls _eabi to set R13 and R2 registers to point to .sdata and .sdata2 sections respectively
– Performs user tasks
Software Design 37
PowerPC Processor
• Memory and peripherals– PPC405 uses 32-bit addresses
• Special addresses– Every PowerPC™ system should have
the boot section starting at0xFFFFFFFC
• Default linker options– Program space occupies a contiguous
address space from 0xFFFF0000 to0xFFFFFFFF
– Stack size: 4 KB – Heap size: 4 KB
0x0000_0000
0xFFFF_0000
0xFFFF_FFFC
Peripherals
PLB/OPB Memory
PLB/OPB Memory
Reset Address
Object File Sections
Address Management 39
.text
.rodata
.sdata2
.data
.sdata
.sbss
.bss
Text section
Read-only data section
Small read-only data section (less than eight bytes)
Read-write data section
Small read-write data section
Small uninitialized data section
Uninitialized data section
Sections Example
Address Management 40
int ram_data[10] = {0,1,2,3,4,5,6,7,8,9}; /* DATA */
const int rom_data[10] = {9,8,7,6,5,4,3,2,1}; /* RODATA */
int I; /* BSS */
main(){
...
I = I + 10; /* TEXT */
...
}
Linker and Locator Flows
Address Management 41
.text1
.data1
.bss1
.bss2
.data2
.text2
foo1.o
foo2.o
Link
.text
.data
.bss
0xFFFF
0xF000
0xEFFF
0xEF00
0x0000
0x1FFF
0x2000
0xEEFF
Locate
Merged Output
Sections
Unused
Executable Image
Code
uninitialized data
Initialized data
Linker Script Generator GUI
• XPS contains a graphical Linker Script Generator
• Table-based GUI allows you to define the memory space for any section
• Launch from Software → Generate Linker Script, or from the Applications Tab, right-click on <project> → Generate Linker Script
Address Management 43
Debugging
SDK Application Development Flow
Debugging 45
Create softwareApp Project
Add sources + Edit
Compile + Link
Generate HardwarePlatform
Done?Import ELF file,
Download to board
Debug / Profile
Platform Studio SDK
Yes
Generate SoftwarePlatform
libraries, drivers
Platform Studio
SDK Workbench
C/C++ project outline displays the elements of a project with file decorators (icons) for easy identification
C/C++ editor for integrated software creation
Code outline displays elements of the software file under development with file decorators (icons) for easy identification
Problems, Console, Properties view lists output information associated with the software development flow
Debugging 46
1
2
3
4
1 2 3
4
Debugging Using SDK
Debugging 47
Eclipse CDT
XMD
powerpc-eabi-gdb (or)
mb-gdb
JTAG / XMD protocolXilinx custom graphical debug interface, started off as a skin on XMD
auto-launched
auto-launched
gdb remote protocol
SDK Debug PerspectiveThe stack frame for target threads that you are debugging. Each thread in your program is represented as a node in the tree
Variables, Breakpoints, and Registers views allow for viewing and real-time interaction with the view contents for more powerful debugging potential
C/C++ editor highlights the location of the execution pointer, along with allowing the setting of breakpoints
Debugging 48
1
2
3
4
5
5
43
2
1
Code outline and disassembly view provide compiler level insight into the running code
Console view lists output information
Debugging in XPS vs SDK
Debugging 49
Debugging in XPS
- Download bitstream from XPS
- Launch XMD- Provide Target Connection
Options- Launch GDB (Insight GUI)- Set GDB Server connection
port in GDB- Download program - Begin Debugging
Debugging in SDK
- Download bitstream from XPS
- Launch XMD- Provide Target Connection
Options- Launch GDB (Insight GUI)- Set GDB Server connection
port in GDB- Download program - Begin Debugging
Questions?