Embedded  Passives..con0nued  

Why Embedded Passives? •  Improves the packaging efficiency •  System-on-Package (SOP); SLIM integration •  Reducing size •  Eliminating substrate assembly •  Minimizing solder joint failure and enhancing

reliability •  Faster and cleaner electrical signals •  Add functionality •  More design flexibility? •  Better reliability? •  Pb-free •  Cost savings; near-zero incremental cost?

Challenges •  Resistor tolerance and sheet resistivity:

–  Both resistivity and thickness tolerances are goals which have not been met by resistor materials suitable for resistively required for widespread applications.

•  Yields: –  Yield loss per device must be extremely small

(~0.00001) because embedded resistors cannot be repaired.

•  Cost: –  Make new materials and processes cheap enough

to reduce the overall cost.

Embedded capacitor

•  Types of Embedded capacitor –  Singulated. –  Distributed.

•  Types of materials –  Inorganic –  Organic

Source: ITRI documents

Dielectric constant (k) is an intrinsic material property that represents how well a capacitor stores charge when a voltage is applied. Although it is called the dielectric constant, the value changes based on many parameters such as temperature, frequency, voltage and time. As seen in the equation, high dielectric constant results in higher capacitance at a given space. For this reason, higher dielectric constant materials are desired in certain applications where space is limited.

Design Library CEDT

Embedded capacitor •  Inorganic methods.

–  Sputtering: •  chemical vapor deposition (thin film deposition ,

practiced in micro-electronics industry). –  Sol-gel:

•  deposition of thin film of materials with higher dielectric constants. (PLZT-Lead Lanthanum Zirconium Titanate ferroelectric*).

–  Anodization: •  vacuum deposition of aluminum and tantalum to form

thin dielectric oxide layer. • Ferro electric materials exhibit spontaneous electric dipole moment, high crystal lattice order

• Para electric materials have crystal phases in which electric poles are unaligned

Embedded capacitor

•  Organic methods

–  Polymers: •  Simple ways of mixing and dispersion. But has low

permittivity, otherwise ideal choice. (polyvinylidene fluoride, polyvinylchloride, polypyrrole).

•  Improved safety factor due to suppression of combustion, low ESR

•  Mixed methods –  Polymer-ceramic:

•  To increase the dielectric constant.

• A wide range of capacitance from 1pF to many uF is needed for various applications. • For filtering and termination relatively low capacitance of 1pF to 200pF is required.

• For decoupling and energy storage the range is a few nF to a few uF.

Steps for fabrication of Embedded Capacitors

Figure Source: KJ Lee, Georgia Tech

Steps for microvia and Cu addition

Figure Source: KJ Lee, Georgia Tech

CAPACITORS

CEDT

Complete Test vehicle (multi-layer organic substrate) with embedded R and C

Figure Courtesy: GTech

Characterization Design Reference

for R Line

Width mm

R Foil Ω

1 2593

0.75 2545

0.50 2480

0.25 2470

0.25 423

0.5 441

0.75 470

1 474

Design Ref For Cap

Product A Product B

24µ 12µ

10 mm2 913 208 667

8 mm2 593 137 445

6 mm2 364 81 261

4 mm2 147 37 116

2 mm2 43 14 36

1 mm2 14 7 13

Values of Capacitors obtained in test Board based on area and geometry (pF)

Tests and Characterization •  Adhesion Test: Copper on Dielectric to be checked •  Dielectric Shrinkage- should be minimal •  Thermal cycling: 125°C for 100hrs: less than 10% change in R and C values •  Temp/Humidity cycling: 85°C/85%RH: less than 5% failures •  Peel Strength: Ni-Cr foil and Ni-P electroless deposits

Thermal Reliability and Electrical Test

600

650

700

750

800

0 20 40 60 80 100 120

Duration(Hrs.)

Resistance(Ohm

s)

Thermal stability of R by foil

360

370

380

390

400

410

420

0 50 100 150 200 250 300 350 400

Duration (Hrs)

Res

ista

nce

(Ohm

s)

85°C/85%RH cycling of R foil: 400 hours

600

700

800

900

0 20 40 60 80 100

Duration (Hours)

Res

ista

nce

(Ohm

s)Thermal Stability of R by electroless method

1.37nF

Source: CEDT & Georgia Tech

Samples

R patterning after inner layer

Fully etched Capacitor patterns

Test board of C foil - first etch Inductor pattern on PWB

Cross-section of a microvia Test board with R and C

Resistors on Flex Epoxy Base

Resistors by PTF-R material

Prototype board with microvia

CEDT

Ni-P Characterization Assembled Prototypes

Bath Ni % P %

Acetate 94.91 5.09

Alkaline 93.34 6.66

Citrate 94.95 25.05

~90 resistors embedded

Ni-P

0

5

10

15

20

25

10.000,

11.880,

13.760,

15.640,

17.520,

19.400,

21.280,

23.160,

25.040,

26.920,

28.800,

30.680,

32.560,

34.440,

36.320,

38.200,

40.080,

41.960,

43.840,

45.720,

47.600,

49.480,

51.360,

53.240,

55.120,

57.000,

58.880,

60.760,

62.640,

64.520,

66.400,

68.280,

70.160,

72.040,

73.920,

75.800,

77.680,

79.560,

EDAX of Ni-P from acetate and citrate baths: P content varies from 7-25%

SEM photographs of NiCrAlSi from foil, Ni-P from acetate and citrate baths; particle size ~2-3um

XRD analysis shows Ni microcrystalline peak; increase in P content shows lattice disorder of Ni phase

Source: CEDT

Functional board with embedded R

CEDT

Functional board with embedded C

CEDT

Prototype board with embedded C and R

CEDT

Case Study on PWB Miniaturization Implementation

Board Type No of layers

Component mounting

Type

Line widths used

Via type used

Approximate area of board

Board area

savings

Standard Double Sided

2 Through-hole 16, 20, 40 mils

TH via 55 mils

75.0 sq. inch

Standard Double Sided

2 Mixed type-THT and SMD

12, 16, 20 mils

TH via 55 mils

26.8 sq. inch ~60%

Multilayer 4 Mixed type-THT and SMD

06, 12, 16 mils

Microvia (100um) Buried and TH

16.8 sq. inch ~75%

Multilayer (build on

both sides)

6 Signal-4 Emb R-2

Mixed type-THT and SMD Emb R ~100 on two sides

06, 12 mils

Microvia (100um) Stacked

via

12.0 sq. inch ~82%

Multilayer (build on only

one side)

4 Signal-3 Emb R-1

Mixed type-THT and SMD Emb R~100 on one side

06, 08 mils

Microvia (100um) Stacked

via

12.0 sq. inch ~82%

CEDT work

Conclusions •  Microvia interconnects and Sequential build enables high density

packaging at board level. •  Embedded Passives have been successfully designed by industry

and fabricated on multilayered organic substrate. •  Enables System-on-Package architecture. •  Resistors can be fabricated by 3 methods: PTF, Foil and Electroless

plating •  Capacitors can be fabricated by foil and polymer-nanocomposite

routes. •  Merges well with conventional PWB fabrication processes and

materials. •  Eliminates through-hole and surface mount components, although

SMT is still highly popular. •  Lead-free assembly enabled with embedded R and C. •  No standard design library available for embedded components. •  Laser trim of Resistors will yield better tolerance values. •  Basic concerns like adhesion, peel strength taken care of. •  Cost-effective epoxy substrates and interlayer dielectrics used. •  Less than 10% variation in R, C values after thermal cycling and

humidity tests.

Figure: Lord Corporation

Role  of  Materials  and  Processes  in    Electronics  Packaging  

•  Diverse  and  crucial  role  of  materials  in  packaging  

•  Important  proper0es  of  materials  relevant  to  packaging  

•  Summary  of  Processes  in  packaging  

Role of materials in Microsystems packaging

Figure: ‘Fundamentals of Microsystems Packaging’ -Rao Tummala

Figure: ‘Fundamentals of Microsystems Packaging’ -Rao Tummala

•  Protection •  Interconnection •  Heat Dissipation

•  Electrical connection

•  High I/O density •  Cu on Polyimide

•  Copper •  Aluminium •  Gold

• Plastics • Epoxy + filters • Ceramics

•  Compress Molding •  Tape casting •  Dry Pressing

•  Reliability

•  Environmentally friendly

•  Permittivity •  TCE •  Thermal conductivity •  Moisture Absorption

•  Thermocomp. Bonding •  Ultrasonic bonding

Figure: ‘Fundamentals of Microsystems Packaging’ -Rao Tummala

Role of Materials in electronics packaging

•  Integrated Circuit Packaging –  IC Packages

•  IC Assembly •  System-level packaging

– Boards – Board Assembly

Packaging Materials and Processes

•  Electrical Properties – Conductivity – Permittivity and loss tangent

•  Thermal Properties – Thermal conductivity – Coefficient of thermal expansion – Glass transition temperature

Packaging Materials and Processes

•  Mechanical Properties – Young’s Modulus

•  Chemical Properties – Surface tension and wetting – Adhesion

Materials Processing •  Thick-film processes

–  Ceramic –  Screen printing –  Organic

•  PWB processes •  Thin-film processes

–  PVD •  Vacuum evaporation, sputtering

–  CVD –  Solution based: Physical

•  Spin-coating, meniscus coating, dip coating –  Solution based: Chemical

•  Sol-gel deposition, Hydrothermal deposition, electroless and electroplating

•  Photolithography

Current and future trends in materials and processes

•  Interconnections –  Organic-based interconnects –  Non-conductive adhesives –  Anisotropic conductive adhesives (ACA) –  Isotropic conductive adhesives (ICA)

•  Low-dielectric constant dielectrics •  Board materials •  Underfill materials