emerging tech 29.03
DESCRIPTION
Evolution of PC – a look backTRANSCRIPT
EMERGING TECHNOLOGIES
S V RAOSENIOR MANAGER
ASIC DESIGN
WHO WE ARE
AT AMD WE LIVE OUR CORE VALUES THROUGH OUR ACTIONS
OUR STATS
} Established in 1969 and headquartered in Sunnyvale, California and Austin, Texas
} Approximately 10,0004
employees worldwide
} Operations in 31 countries, with more than 50 locations, including more than a dozen R&D facilities,
OUR OFFERINGS
} Accelerated Processing Units (APUs) for consumer and commercial notebook, desktop and embedded markets
} x86 microprocessors for commercial and consumer markets
} Embedded microprocessors for commercial, commercial client and consumer markets
} Chipsets for desktop and notebook PCs, embedded systems, professional workstations and servers
} Graphics, video and multimedia products and technologies for desktop and notebook PCs, embedded systems, professional workstations, servers and game consoles
Agenda
• Introduction • Evolution of PC – a look back• PC Interface Technology • Trends in Computer Architecture• Challenges with Computing Today• Heterogeneous System Architecture• What’s after CMOS-based Transistor?• Q & A
SimpleInstant
Complete
What Customer Needs?Think !!!
http://www.youtube.com/watch?v=Nqvd06mrIrM
Ø IBM PC Commodore PET Ø PC -AT Ø SUN work station
Ø Gaming and MM PC
Ø Laptop
Ø Netbook
Ø Tablet PC
Focus on Technologies that Brings Size of the System Small & Portable
Ø iPAD
Evolution of PC – A Look Back
Ø Letters & words
Ø Touch
Focus on Technologies that Brings New and Exciting User Experience
Ø 2D GUI Speech, Gesture , Facial Recognition
PC Interface Technology
TRENDS IN COMPUTER ARCHITECTURE
o Pasto CPU : Central Processor Unit
o GPU : Graphics Processor Unit
o North Bridge: Hub that enables CPU &GPU to access system memory
o South Bridge: Hub that connects different peripheral devices
(GPU: Graphics Processing Unit = Graphics + Multi-Media + Frame-Buffer)
o Presento APU: Accelerated Processing Unit
(CPU + GPU + North Bridge + South Bridge)
o Futureo APU with HSA (Heterogeneous System Architecture)
http://www.youtube.com/watch?v=qA_XIrY_ISw
o The Challenges with Computing Today (4Ps)
o Power – Reducing power consumption is increasingly critical across all segments of computing
o Performance -- We demand constantly improving performance to enable compelling new user experiences
o Programmability -- To deliver new user experiences, programmer productivity is another essential element that must be delivered
o Portability -- It is increasingly important that software be supported across a broad spectrum of devices
To navigate complex set of requirements, the computer industry needs a different approach – a more efficient approach to computer architecture
CHALLENGES WITH COMPUTING TODAY
CHALLENGES WITH COMPUTING TODAY
o CPUs designed to run general programming tasks very well
o GPU designed to perform specialized graphics computations in parallel
o Current CPUs and GPUs have been designed as separate processing elements and do not work together efficiently
o Moore’s Law has enabled the semiconductor industry to a point where an entire system can be placed on a chip, including memory, I/O, high-speed networks, networking interfaces, and various dedicated and programmable logic components
o Programming heterogeneous solutions is a challenge because each type of compute unit (CPUs, GPUs, DSPs, etc.) has a different execution model due to differing instruction set architectures (ISAs) and separate memory spaces
CHALLENGES WITH COMPUTING TODAY
o The current programming model calls for an Application Programming Interface (API) approach to programming and execution that is designed around the CPU and operating system.
o Most SoCs have separate physical and/or virtual memory spaces for each type of compute --require complex memory mapping and data transfers
o Programmers must account for and maintain the status of memory contents when switching between different compute units such as CPUs and GPUs
o Some heterogeneous programing toolsets like CUDA and OpenCL have been developed, they require detailed knowledge of the hardware architecture, learning new programming languages and tools, and continuous management of memory contents
o HSA creates an improved processor design that exposes the benefits and capabilities of mainstream programmable compute elements, working together seamlessly
o The HSA shares data between CPU and GPU, without memory copies or cache flushes because it assigns each part of the workload to the most appropriate processor with minimal dispatch overhead
What is Heterogeneous System Architecture (HSA)?
o Relative performance gain at Reduced power level
o This level of performance is not possible using only multicore CPU, only GPU, or even combined CPU and GPU with today’s driver model
o An important key to the success of HSA is its ability to simplify the process of getting applications to run on the architecture
o http://www.youtube.com/watch?v=Me0g_FsgU0U
What is Heterogeneous System Architecture (HSA)?
HSA
HAS Foundation
The Goal of the HSA Foundation is four-fold: o To enable power-efficient performance o To improve programmability of heterogeneous processors o To increase the portability of code across processors and platforms o To increase the pervasiveness of heterogeneous solutions throughout the
industry
What’s After CMOS-Based Transistor?
What’s After CMOS-Based Transistor?
o Process Technologyo Historically, the process technology referred to “the length of the silicon
channel between the source and drain terminals in FET”
o One human hair = Two thousand 45 nm objects laid side-by-side
o On-going process technology in Industry is 16/14 nm
o CMOS transistor scaling is the major challenge
(approximate for all vendors)Nanometers Micrometers
Year (nm) (µm)
1957 120,000 120.01963 30,000 30.01971 10,000 10.01974 6,000 6.01976 3,000 3.01982 1,500 1.51985 1,300 1.31989 1,000 1.01993 600 0.61996 350 0.351998 250 0.251999 180 0.18
Nanometers MicrometersYear (nm) (µm)
2001 130 0.132003 90 0.092005 65 0.0652008 45 0.0452010 32 0.0322012 22 0.0222014 16/14 0.016**2016 11 0.011**2018 6 0.006**2020 4 0.004**
** estimated
Semiconductor Feature Sizes
What’s After CMOS?
• Chipmakers continue to scale the CMOS transistor to finer geometries
• Current thinking : CMOS transistor could scale at least to the 3nm node in the 2021 timeframe
• Chipmakers are now migrating to finFETs (3D devices) from planar transistors
• Silicon-based finFETs will scale to 10nm. At 7nm, finFETs may require new and costly materials
• It may take more time to migrate from 14nm to 10nm and then to 7nm
• Once finFET costs come down, the 10nm node will be the sweet spot for a long, long time
o There are more than 20 possible successors; carbon nanotubes, graphene, tunnel FETs, nano-magnetic devices etc are way down on the list
o Industry is exploring technologies in four basic categorieso Charged (CMOS, TFET) o Electric dipole (FeFET) o Magnetic (spin devices) o Orbital state (BisFET)
o It is not clear on the development of a viable next-generation switch by 2020
o The challenges and costs could push out the development of a next-generation switch at least for several decades
o Regarding things that go beyond CMOS, we are really talking about 2030 or 2040 or so
What’s After CMOS?
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