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EML 4561Introduction to Electronic PackagingW. Kinzy Jones, Professor MMEMWF 11:00-11:50Jones@fiu.edu305-393-0506(mobile)305-348-4663 (office)Notes on the fieldI am Past President and Fellow, IMAPS, The Microelectronics and Packaging SocietyResearch in advanced packaging, 1st Level Assembly, Thermal Management, Components and Electronic Materials- Funded over $7MM in past 15 yearsElectronic packaging is a application field that crosses over many disciplines. There are 80,000 ME working in the field. Conferences/journals by ASME, IEEE, ASM, IMAPS, etc.All former graduate student hired prior to graduation!OutlineTechnological DriversDesign ProcessElectrical ConsiderationMechanical ConstraintsThermal ManagementMaterial Science FundamentalsInterconnect Technology Laminate technology Ceramic Processes ( thick film, cofire ceramic)Thin Film DepositedOutline (Cont.)ComponentsActive components technologiesPassive Components technologiesIC Packaging ( from DIP to System-on-package (SOP))AssemblyFirst Level Assembly ( wire bonding, flip chip)SolderingManufacturing ProcessesReliabilityMIL StandardsReliability ProjectionsIntroduction to Microsystems Packaging Definition of Packaging

BoardICPackaging is a Bridge from ICto SystemIt Controls:>90% sizePerformanceCostReliabilityPackaging Hierarchy

Microsystems Technologies

System Packaging Involves Electrical, Mechanical and Materials Technologies

Analogy Between Human and Electronics

Trend to Convergent MicrosystemsDiscrete SystemsPastFuturePackagingMEMSMicroelectronicsPhotonicsRFBioelectronicsConvergentMicrosystems

Building Block of Microsystems Packaging197519952015Year110100100010000WW S/C Revenue ($B)Trend to Convergent Systems

BusinessesHost-based computingMainframeDumb terminalFew vendors / architectureMainframesTransistors / chip1B1M10M100M10B100K10K1K100BPCs

PCs / ServersBusinesses & some peopleClient-server computingLocal area connectionText/graphical interfaceMany vendors / few architecturesTodayAll businesses, people, objectsNetwork computingWide area / bandwidthGraphical, voice, multimedia, etc.Many vendors / platformsInternetSource: Russ Lange, IBM MicroelectronicsWirelessWiredConvergent SystemsWhat are Convergent Microminiaturized Microsystems (CMM)?Convergent: Two or more functionsMicrominiaturized: >1000x volume reductionsMicrosystems: systems with micro-scale technologiesTrend to Convergent Microminiaturized Systems (CMM)Functional Data and VoiceTechnology Digital, RF, Analog and OpticalProduct Computer, consumer and telecom

Video Cell Phone

CONSUMERELECTRONICS

Medical Implant/ Diagnostic Monitor/ CommunicatorMEDICALThe Invention of the First IC

Moore s Law: Doubles Every 18 Months

SOC AdvancesSOISiGeCu - low KMoores Law

SOC ChallengesMajor Delay ProblemsSummaryFundamental Digital LimitsIntegration RF LimitsFundamentalDesign & Verification ComplexityTest ComplexityProcess ComplexityMixed Function CostsWafer Fab CostsLegal ProblemsTime-to-marketSOC: Integration of Two or More Mixed Functions in a Single IC

(a)(b)

Bulky Size

What is Wrong with Current Packaging for Tomorrows Needs?Higher CostPoorer ReliabilityActive ICs 10%Passives: 90%IC: PPBSystems Pkg: PPMCellular PhoneWeight Trend

Barrier to all future systemsLower PerformanceWhat is SOP, SIP, or Board?A.) Todays Board: Interconnect ComponentsRF ICDigital ICSubstrateOptical ICICB.) SIP: Stacked Chip/Package for Reduced Form FactorsFlashRAMmPICPackageSuper IC Stack (ASET)Package (Fujitsu)Stacked IC (Amkor)C.) SOP: Optimizes Functions Between ICs and PackageRF ICOpto ICDigital ICPackage with Opto, RF, Digital FunctionsRFOptoElectrical3-D ICsWhat are SOC, SIP, and SOP?SOC: System on ChipHighly integrated and mixed signal IC with partial system functions in one component

SIP: System in Package3-D IC or Package AssemblyRequires Systems Board

SOP: System on PackageMicrominiaturized system-level board with two or more embedded RF, digital, analog and optical functionsBest of on-chip and package integration for cost, performance, size and reliabilitySimilar to SOC but total system function in a microminiaturized boardSOP: SIP + SOC+Systems Board3 -D Stacking of ICS or Package Structures, Similar to PWBMacro dimensionsVertical stack upTestable3 -D Build up, similar to IC FabricationMicro to Nano dimensionsSequential build up and test similar to MCM-D and ICWafer to IC concept for high yieldSIPSOP

MEMSGa-AsSIPSOC

SOCMEMSSIPGa-AsWhy SOP?SOC is complex to design and test, expensive to Fabricate, long time-to-market and presents fundamental limits.IC companys dream for decades. No complete system has been shipped to date.SOP optimizes the best of IC and package integration for cost, performance, size and reliability.Faster turn-around and faster time-to-market.Provides full system solution today that SOC provides tomorrow.SIP is a 3-D IC or package, not a complete system

Industrial & Medical11%$105BMilitary9%$ 8.7BAutomotive5%$ 48BBusiness Equip38%$ 383BCommunications26%$ 259BConsumer26%$112BInformation Technology is a Trillion $ Industry Microsystems & Packaging is 25% of ITSource: Prismark

MSP Market ($320 B)

Microelectronics ($165B)Systems Packaging ($125B)Opto & MEMS ($30B)Information Technology and Microsystem Markets

Billion $/YearHardware and Software Markets

Functions of Packaging

Package Interconnections

Core TechnologiesSubstrates, circuit boardsInterconnectPassive componentsActive componentsPackaging

Traditionally these were treated as discrete elements Advanced applications require integrated approach of System Level Packaging

Substrates and Circuit BoardsPrinted Circuit Board (PCB), Printed Wiring Board (PWB)Epoxy-glass composite, copperFR-4, FR = fire retardantAdvanced Resins Polyimide BT = bismaleimide traizineCE = cyanate esterCeramic substratesAluminum oxide, aluminum nitride, beryllium oxide, glass-ceramicInterconnect metals - W, Mo, Au, Cu, AgMultichip ModulesMCM-D,C,LPlatform Support interconnect and componentsThermal path away from ICsWithstand mechanical stresses and vibrationsPackaging Evolution

?Microelectronic Density Trends

logicmicroprocessorsRents Rule

Packaging Evolution

I/O Density Trends

ChipPackage Evolution

Packaging Trends (Cont.)

Assembly ProcessesBoard FabricationSingle layerMultilayerPCBFlexCeramicPopulating the boardPick and placeInsertionDie attachSolderingSolder paste reflowWave solderSolder bump reflowEncapsulation

SIA Roadmap for Chip Interconnections, 1995

CMOS Device Trends

Buda et al, 42 CPMT, pp36-41, 1992NEMI Roadmap, 1996

Packaging trends in Automotive ElectronicsPackaging trends in Consumer ElectronicsiNEMI Roadmap, 2009

NEMI Roadmap for Packaging Trends in High-Performance Systems

High Performance Systems, iNEMI 2009

Interconnect Density, Std. PWB

.1mm = 4 milsThermal Cooling Requirements

Types of First Level Packages

Chip-Scale Packages

Types of Ball Grid Arrays

Flip Chip Assembly

ChipSubstrateExample- Controlled Collapse Chip Connection-C4 (IBM) assembly on ceramic substrateSolderPrimary functionsElectrical connection between component and interconnectMechanical attachment of component to boardThermal path from component to boardAlloys of various compositions and melting pointsLead-Tin solder most commonEutectic composition: 63% Tin, 47% Lead60/40 or 2% silver addedSolder paste for screen printing, pressure dispensingAlloy particlesFlux and activator chemicalsVehicle to control viscosityWave solderingFoam or spray fluxPreheat boardTurbulent wave to spread solderLaminar wave to smoothEffect of Underfill on Temp Cycling Performance

With filler, 27ppmFunctions of a Multichip Package

Illustrations of MCM Types

Low Temperature Cofired Ceramics with Buried Components

Packaging Efficiency

Packaging Considerations that Effect the Electrical PerformanceInterconnects Worsen:Signal IntegrityPerformance: switching, speedReliabilityForm, fit, and function- weight, volume, powerInterconnects Can Have Very Important Electrical PropertiesPropertySelf-inductanceCapacitance to groundtransmission line

Mutual Inductance, capacitanceResistance, lossPossible ImpactGround bounceDelay, power sagPropagation delay, reflectionCross-talk, noise

Damping, ringing, power sagDrivers for Reduction of Interconnect LengthDirectly reduces inductance, capacitance, resistance and delayIndirectly reduces switching time, power, size, ringing, ground bounce, and power sagElectrical FundamentalsResistance ( ohms). Relates Ohms law relationship between current and voltage, V=IR. Resistivity, , is a materials property, in ohm-meters. Resistance, R = Length x / cross-sectional area of conductorCapacitance (farads) relates to the ability to store charge. Capacitance for a parallel plate capacitor is proportional to the dielectric constant,K, times the area of the plate/ thickness of dielectric.Inductance ( henry)- relates to the voltage generated to oppose a change in currentBasic Resistance EquationResistance R = L / A = L /wt = L/w Rs where Rs is defined as the sheet resistivity, is resistivity, L is the length and A is the cross sectional area of the conductor/resistor A square ( L=W ) for a fixed thickness of material has a fixed resistance per square, independent of size. A square anything Capacitance isIn the insulation between more than one conductorOrders of Magnitude higher outside the chip than insideThe dominate determinant of digital speed

Dielectric Constants of Some Insulators

Capacitance of Electrically Short InterconnectionsCapacitance is the sum of all output capacitance of all drivers to that interconnect, the input capacitance of all receivers, and the distributed capacitance to ground of the interconnection

Switching Time, PowerIf a step voltage is applied to an RC network, the time delay is proportional to RC. If the capacitor is charged from zero to full charge, the energy dissipated, W, is independent of R and equals CV2/2. But energy is also power X time delay. If we operate twice as fast, the circuit will dissipate twice the power.

InductanceOpposes a change in current by generating a back voltage. If the current change is positive, the back voltage subtracts from the voltage applied, causing a power sag.The voltage is equal to the inductance times the rate of change of the current , VL= L di/dtSelf inductance exists in every wire, trace, wire bond, solder joint, etc..It is minimized by large, short conductors, or a sheet conductor as a ground or power plane. Example: If we switch 1 amp in 5 nsec on a 1 trace with 7.8 nH, we generate a back voltage of 1.6 volts.CrosstalkThere is a mutual capacitance between two adjacent insulated conductors that couples a fraction of one voltage to the otherThere is also mutual inductance, functioning as a transformer by generating a voltage in each when the current changes in the other.This is crosstalk. Can be minimized by design (keep talkers and listeners apart) and use of ground/power traces between talkers/listenersGround Bounce, Power SagCause: Common-mode impedance, usually inductiveDigital devices require most of their power supply current during switching. Clocked signals switch together, so there could be a large total surgeThe inductance in the power and ground leads causes ground bounce and power sag.

Bypass ( decoupling) CapacitorsTo reduce power sag and ground bounce, add decoupling capacitors. Value should be 20-100 nF/sq.cm of silicon. Decoupling capacitors should have low parasitic inductance.Capacitors serve as local energy reserves and need to be close to the power/ground leads

RLC Circuit SwitchingThe voltage step sent down an interconnect can be distorted badly by the R, C, and L on the interconnectThis distortion can be removed by the right balance of the values of R,L and C. When R = 2* sqrt(L/C), critical damping occursIf R is above critical damping, switching slows down; if below, ringing of the signal occurs

Critical Damping

Transmission LinesAny interconnect whose length is over a small fraction of the wavelength of the signal it carries acts like both a transmission line and an antenna radiating or receiving noiseAs speed increase, the lumped analysis of L,R,and C components must be replaced by the distributed network of L,R, and C.Property shielded interconnects minimize the effect of antenna properties, but the transmission properties remainTransmission Line PropertiesA transmission line appears as a string of small inductors and capacitors, with seven principal properties:length L, inductance per unit length, capacitance per unit length, impedance (Z), attenuation, propagation velocity, and time delay

Transmission Line Equations

Transmission line tracesMatched impedance systems require containment of the electrical fields. This has lead to designs including the stripline, the microstrip, the buried microstrip. Additionally, for multilayer routing, vias must be considered

Stripline microstrip

Microstrip Design for 50 Impedance

Traveling Waves on an Infinite LineSwitching on a DC source voltage, V, :draws the same current as a resistor of value Zo connected to V.current flows down the line at the propagation velocity, while the current progressively charges up the line capacitance to voltage V. Hence a voltage step V also travels down the line.Draws current indefinitely due to an infinitely long lineThe source only sees a resistive load Zo continuously drawing currentTraveling Waves on an Unterminated LineWhen the line is unterminated ( R is infinite):Kirchoffs current law still applies at the far end: the sum of current entering the end must equal the current leaving the end. But there is no load to draw current from the end node.Therefore, an equal reflected current wave is generated that travels back toward the source.This reflected current wave requires an extra voltage source, V, to propel it, so the voltage at the far end steps up to 2V.This increased voltage travels back towards the source along with the reflected current.What happens at the source depends on the sources internal impedanceThe waves can on occasion reflected back and forth several times

Lines Traveling Waves Capacitively TerminatedThe problem of reflection is compounded by capacitance at the ends.When a transmission line drives a capacitor, the extra capacitance causes:reflections, since the line is now mismatchedringing for some drivers, since there is no longer critical dampingCMOS inputs are essentially capacitive.AC TerminationTo minimize power dissipation, a series capacitor,C, can be added to the terminating resistorThis terminated the line only when a voltage transition occurs and allows no DC power dissipation in RThe value of C must be selected carefully, either by simulation or experimentation to minimize the effect of capacitively terminated lines.When Interconnections are Electrically SignificantWhen interconnects degrade switching timeWhen the signals are not correctly dampedWhen large amounts of current switchIn the time domain, when the line propagation delay approaches the driver switching time. Propagation delay is proportional to lengthIn the frequency domain, when the wavelength of the signal ( including harmonics) are not long compared to the length of the interconnect ( for 100 Mhz- over a few centimeters)PackagingWhat packaging provides:InterconnectionPower DistributionThermal ManagementEnvironmental ProtectionWhat the package is made from--materials, partsWhat is used to design and fabricate packages:Facilities and EquipmentManufacturing and Design ToolsProcess by which the package is produced over time86Technology DrivesIncreases in semiconductor complexity from decreased feature sizeCorresponding increases in systems speedIncrease in input/output (I/O) densityIncrease in power density (W/cm2)Levels of Packaging1st Level ConnectionIC to Common Circuit BaseWirebonds or solder bumps to package base2nd Level ConnectionCommon Circuit Base to Circuit BoardPackage leads soldered to PCB3rd Level ConnectionAssembly of multiple boards into larger assemblyVideo card, modem, game port on a PC motherboard4th and 5th Level ConnectionsSystem level assembly with several 3rd Level subassembliesMotion control, visual alignment, user interface, etc. in manufacturing equipmentChart18648383259112105

Sheet1Military86Automotive48Business Equip383Communications259Consumer112Industrial & Medical105

Sheet1000000

Sheet2

Sheet3

Chart116512530

Sheet1Semiconductors165Systems Packaging125Opto & MEMS30

Sheet1000

Sheet2

Sheet3

Dielectric Material Type Dielectric Constant, K

FR-4epoxy4.8

PTFEfloropolymer2.8

Aluminaceramic9.0

PVF2Polymer 12.0

air

1.0