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Enabling Coherent FPGA Acceleration Allan Cantle, President & Founder Nallatech Join the conversation at #OpenPOWERSummit 1 #OpenPOWERSummit

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Page 1: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Enabling Coherent FPGA Acceleration

Allan Cantle, President & Founder

Nallatech

Join the conversation at #OpenPOWERSummit 1

#OpenPOWERSummit

Page 2: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Overview

Nallatech at a Glance

Coherent Attached Accelerators…So what’s new?

How CAPI Works compared to PCIe Accelerators

IBM/Nallatech’s CAPI Developer Kit Overview

CAPI to PMC NVMe Demo

Join the conversation at #OpenPOWERSummit 2

Page 3: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Nallatech at a glance Server qualified accelerator cards featuring FPGAs, network I/O and an open architecture software/firmware framework

Design Services/Application Optimization

Join the conversation at #OpenPOWERSummit 3

Leading supplier of FPGA solutions

Energy-efficient High Performance Heterogeneous Computing

Real-time, low latency network and I/O processing

Altera OpenCL partner

OpenPower Foundation Member

Page 4: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

4

Coherent Accelerators…So what’s new?

Decade of Coherent “In Socket” Accelerators • Hyper-Transport, FSB & QPI

Not commercially successful, Why? • Proprietary “In Socket” attached

• Server mechanical fit challenges

• Need to give up processor socket

• Proprietary Specification

• Licensing Issues

• Always lagging 6-12 Month cadence

“In Socket” Coherent Accelerators

Page 5: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Decade of Coherent “In Socket” Accelerators • Hyper-Transport, FSB & QPI

Never commercialized….Why? • Proprietary “In Socket” attached

• Server mechanical fit challenges

• Need to give up processor socket

• Proprietary and poorly documented

• Expensive & complicated licensing

• Always lagging 6-12 Month cadence

5

Coherent Accelerators…So what’s new?

POWER8 Modules CAPI PCIe Cards

Industry Standard Server Configuration

“In Socket” Coherent Accelerators

IBM’s Coherent Accelerator Processor Interface, CAPI, Resolves ALL these Issues

Already Commercialized • Industry Standard PCIe Attached

• PCIe – No Mechanical Challenges

• Processors use all available sockets

• OpenPower & well documented

• Free & simple OpenPower Licensing

• In sync with POWER & PCIe Cadence

Page 6: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

How CAPI Works

Join the conversation at #OpenPOWERSummit 6

PCIe Algorithm Algo m rith

POWER8 Processor

Acceleration Portion:

Data or Compute Intensive,

Storage or External I/O

Application Portion:

Data Set-up, Control

Sharing the same memory space

Accelerator is a peer to POWER8 Core

CAPI FPGA Accelerator – (NOTE: Based on a Standard PCIe Accelerator)

Page 7: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

CAPI technology connections

Join the conversation at #OpenPOWERSummit 7

FPGA

POWER8

Core

CA

PP

P

CIe

Proprietary hardware to enable coherent acceleration

Operating system enablement

– Ubuntu LE

– Libcxl function calls

Customer application and accelerator

Application sets up data and calls the accelerator functional unit (AFU)

AFU reads and writes coherent data across the PCIe and communicates with the application

– PSL cache holds coherent data for quick AFU access

POWER8 Processor

OS

App

Memory (Coherent)

AFU

IBM Supplied PSL

Page 8: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Issues with PCIe Accelerators

Prior to CAPI, an application called a device driver to utilize an FPGA Accelerator.

The device driver performed a memory mapping operation.

Join the conversation at #OpenPOWERSummit 8

Memory Subsystem

Virt Addr

POWER8 Core

POWER8 Core

POWER8 Core

POWER8 Core

POWER8 Core

POWER8 Core

App

FPGA PCIE

Variables Input Data

DD

Device Driver Storage Area

Variables

Input Data

Variables

Input Data

Output Data

Output Data

3 versions of the data (not coherent). 1000s of instructions in the device driver.

Page 9: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Benefit of Coherent accelerators

With CAPI, the FPGA shares memory with the cores

Greatly simplifies programming model

Join the conversation at #OpenPOWERSummit 9

Memory Subsystem

Virt Addr

POWER8 Core

POWER8 Core

POWER8 Core

POWER8 Core

POWER8 Core

POWER8 Core

App

FPGA PCIE

PSL

Variables Input Data

Output Data

1 coherent version of the data. No device driver call/instructions.

Page 10: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

CAPI vs. PCIe Device Driver: Data Prep

Join the conversation at #OpenPOWERSummit 10

Typical PCIe Model Flow:

Flow with a Coherent Model:

Shared Mem.

Notify Accelerator Acceleration

Shared Memory

Completion

DD Call Copy or Pin

Source Data

MMIO Notify

Accelerator Acceleration

Poll / Interrupt

Completion

Copy or Unpin

Result Data

Ret. From DD

Completion

Application

Dependent, but

Equal to below

Application

Dependent, but

Equal to above

300 Instructions 10,000 Instructions 3,000 Instructions 1,000 Instructions

1,000 Instructions

7.9µs 4.9µs

Total ~13µs for data prep

400 Instructions 100 Instructions

0.3µs 0.06µs

Total 0.36µs

Page 11: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Nallatech CAPI Attached FPGA Accelerator

Nallatech’s 385 Card is the CAPI FPGA accelerator card

Collaborated with IBM & Altera through OpenPower

Offering CAPI Developer Kit for Power8

OpenPOWER Summit Confidential 11

Hardware

Components

Software / IP

ComponentsTools Documentation

Nallatech 385 FPGA

Accelerator

IBM CAPI Power

Service Layer (PSL) (Encrypted FPGA IP)

Altera Quartus

FPGA Tools

White Paper and

Decision Guide

Nallatech JTAG

Debug Kit

CAPI Host Support

Library (libcxl)

PSL Simulation

EngineCAPI User's Guide

'Memcopy' Example385 FPGA Card

User Guide

Also RequiredPower 8 System

(IBM Model 8247-21L

or 8247-22L )

CAPI Enabled O/S(initially Ubuntu 14.10 LE

from Canonical)

HDL Simulator (i.e. Cadence,

Mentor, Synopsis)

Included in CAPI

Developer Kit

CAPI Developer Kit

Page 12: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

Nallatech 385 FPGA Accelerator

Half height, half length PCIe form factor (NIC-size)

Altera Stratix V FPGA: A7

PCIe Gen3x8 or CAPI host interface

2 SFP+ network IO ports

2 banks of DDR3 SDRAM: up to 32GB total

Join the conversation at #OpenPOWERSummit 12

Nallatech 385 FPGA Accelerator

Low cost, low power, high performance

Page 13: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

CAPI Developer Kit, Power8 Server Options

IBM Power8 System S812L/(S822L) • 2U server with 1/(2) 10 or 12 Core 3.42 or 3.02GHz Processor(s)

• 80/96 MB L3 Cache per socket + 512KB L2 Cache/Core

• Up to 512GB/(1TB) Memory @ 192/(384) GBytes/s Memory Bandwidth

• Up to 12/(14) Disk/SSD Drives – RAID optional

• 2/(4) PCIex16 + 4/(5) PCIex8 Low Profile Slots – 2/(4) CAPI Enabled

Page 14: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

CAPI - Getting Started Resources

More details at nallatech.com/capi

Discuss your application at nallatech.com/support

Join the conversation at #OpenPOWERSummit 14

http://www.nallatech.com/capi
http://www.nallatech.com/capi
http://www.nallatech.com/support
Page 15: Enabling Coherent FPGA Acceleration - OpenPOWER · Enabling Coherent FPGA Acceleration Allan Cantle, ... Decision Guide Nallatech JTAG ... HDL Simulator (i.e. Cadence,

CAPI to PMC NVMe Demo

Join the conversation at #OpenPOWERSummit 15

NVMe SSD to 385 CAPI FPGA Accelerator

Accelerating Data Analytic operations

Minimal CPU Core Loading

See Demo at Booth 1010

PMC FLASHTEC NVRAM NVMe Drive

Nallatech 385 CAPI FPGA Accelerator

IBM S822L POWER8 Server


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