Enhancing Beneficial Jitter Using Phase Shifted Clock DistributionPhase-Shifted Clock Distribution

Dong Jiao, Jie Gu, Pulkit Jain, and Chris H. Kim

University of MinnesotaDepartment of Electrical and Computer Engineeringp p g g

jainx104@umn.eduwww.umn.edu/~chriskim/

1

Presentation Agendag

• Resonant Noise and TimingResonant Noise and Timing

• Overview of Beneficial Jitter Effect

• Timing Models and 65nm Simulations

• Phase-Shifted Clock Distribution

• Conclusions

2

Power Supply Noise• IR and Ldi/dt noise:

Typically around 10~15% nominal Vdd

• Lower Vdd, larger IVdd, higher fclk:Worsening supply noise with scaling

• Problems due to supply noise: Timing, noise margin, reliability, etc IBM

IVdd

3

Resonant Supply NoiseN. Na, IBM, ECTC 2004

• Typical resonant frequency is 50-300MHz

• Excited by processor loop operation or current spike

• Large magnitude and long g g gduration affects the whole chip

4

Passive Resonance SuppressionIncrease on-chip decap Increase on-chip resistance

ohm

)pe

danc

e (o

L1Q •=

Imp

• Q factor signifies impedance peak G. Ji, et al., T. Adv. Packaging, 2005

CRQ

wire•

Frequency (MHz)

• Penalty for bringing down Q factor:– ↑R: Extra IR drop and power– ↑C: Area and leakage overhead– ↑C: Area and leakage overhead

• Can resonant noise be utilized to improve circuit timing?5

Presentation Agendag

• Resonant Noise and TimingResonant Noise and Timing

• Overview of Beneficial Jitter Effect

• Timing Models and 65nm Simulations

• Phase-Shifted Clock Distribution

• Conclusions

6

Timing Slack in Datapathg• Timing margin between clock period and

datapath delayy

• Positive slack means correct operation7

Beneficial Jitter Effect: Natural Timing C CCompensation Between Clock and Data

• Traditional analysis considers datapath delay only• In reality both datapath delay and clock period varies

8

• In reality, both datapath delay and clock period varies with supply noise

Beneficial Jitter Effect Simulation

50

100

50

100k

(ps)

fres=200MHz, fcp=1GHz, fclk=2GHz, s clk : sdata = 0.7:1

No Supply

65nm, 25°C,1.2V Vdd, 12% Vdd noise

00

50

nalS

lac Noise

‐ 100

‐50

-100

-50

mal

l-sig

n

Clean Clock Noisy Clock

‐ 150

0 5 10 15 200 1.25 2.5 3.75 5-120

Sm Supply Supply25ps

Clock Launching Time (ns)Clock Launching Time (ns)

• Inherent timing compensation between clock and data• 25ps (or 5% T ) slack improvement when considering

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• 25ps (or 5% Tclk) slack improvement when considering beneficial jitter effect

Factors Affecting Beneficial Jitter Effect

cpf/1• : Supply noise phase at clock launch• or : Clock path delaycpt

resθ

dataclk s,s• : Delay sensitivity to supply− Change in speed with respect to supply variation− E.g. If 10% Vdd change causes 15% speed change, s is 1.5g % g % p g ,

• : Resonant frequencyresf

10

Impact of Clock Path Delay65nm, 25°C,1.2V Vdd12% Vdd noise- 20

00

-20

fres=200MHz, fclk=2GHz, sclk: sdata = 0.7:1

No Supply N i

- 60

- 40

Noisy Clock Supply

-60

-40Noise

- 100

- 80

-100

-80Clean Clock

Supply

58ps

- 1200 0.4 0.8 1.2 1.60 0.4 0.8 1.2 1.6

cp cp,

-120

• Optimal clock path delay exists– Small : Approaches clean clock case

Large : Average supply voltages seen by clock edges closercpff

cp cp,

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– Large : Average supply voltages seen by clock edges closer• Up to 58ps (11.6% Tclk) slack improvement with proper cpf

cpf

Impact of Delay Sensitivity65nm, 25°C,1.2V Vdd12% Vdd noise

• Typical clock path delay sensitivity is around 0.6 due to interconnect RC delay

• Much larger (or much smaller) sensitivity worsens

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• Much larger (or much smaller) sensitivity worsens timing slack

Impact of Resonant Frequency65nm, 25°C,1.2V Vdd12% Vdd noise

• Beneficial jitter effect prominent in typical resonant frequency range

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frequency range• Up to 87ps (11.6% Tclk) slack improvement

Presentation Agendag

• Resonant Noise and TimingResonant Noise and Timing

• Overview of Beneficial Jitter Effect

• Timing Models and 65nm Simulations

• Phase-Shifted Clock Distribution

• Conclusions

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Beneficial Jitter Effect Modelingg: Nominal/actual delay

N i l di tYetD ,0: Nominal distance

: DC/AC supply voltage

0Y

aA ,0

[WRM06] K L Wong et al

: Delay sensitivitysS ,

• Adopted methodology from [WRM06]

[WRM06] K. L. Wong, et al., JSSC 2006

• Adopted methodology from [WRM06]• Propagating signal represented as traveling wave with

speed supply voltage

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• Propagation delay equivalent to traveling distance

Beneficial Jitter Effect Modelingg• Mathematical derivations:

0 tSAdtSAYt

== ∫∫ −+= et

m dttsaSAY0 00 )]cos([ θω

000 00 tSAdtSAY == ∫

• Previous model [WRM06](i)

• Previous model [WRM06]

R i d i l d l

θππθπππ

θ cos)sin()sin()sin(2)(0000 Aa

Ss

ff

ff

ff

ff

ff

Aa

Ssslack

data

data

clk

mmm

clk

m

m

clk

clk

clk +−−×=

• Revised simple model)cos()sin()sin()sin(2)(

0000 clk

m

data

data

clk

mmm

clk

m

m

clk

clk

clk

ff

Aa

Ss

ff

ff

ff

ff

ff

Aa

Ssslack πθππθππ

πθ −+−−×=

• Revised accurate model– No closed-form expression exists

Sol e non linear eq ation (i) itho t making appro imations

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– Solve non-linear equation (i) without making approximations– Follow derivation steps of simple model

Timing Model versus HSPICE100

g65nm, 25°C,1.2V Vdd12% Vdd noise

0

50

‐50

‐150

‐100

0 5 10 15 200 5 10 15 20

• Confirms intrinsic compensation effect

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Confirms intrinsic compensation effect• Reduces modeling error from 25ps to 8ps (5% to 1.6% Tclk)

Timing Model versus HSPICEg65nm, 25°C,1.2V Vdd12% Vdd noise

• Revised simple model good for first order approximation

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Revised simple model good for first order approximation• Reduces modeling error from 30ps to 4ps (6% to 0.8% Tclk)

Presentation Agendag

• Resonant Noise and TimingResonant Noise and Timing

• Overview of Beneficial Jitter Effect

• Timing Models and 65nm Simulations

• Phase-Shifted Clock Distribution

• Conclusions

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Intrinsic Beneficial Jitter Effect

• Beneficial jitter effect can be harnessed furtherBeneficial jitter effect can be harnessed further– Datapath delay depends on instantaneous Vdd value.– Clock period depends on Vdd value difference seen by two

consecutive clock edges

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consecutive clock edges.– Worst delay point does not coincide with max clock period point

Enhancing Beneficial Jitter Effect U i Ph Shift d Cl k Di t ib tiUsing Phase-Shifted Clock Distribution

• Phase-shift the clockpath supply noise• Clock period can be stretched out the most when the

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• Clock period can be stretched out the most when the worst case datapath delay occurs

Phase-Shifted Clock Buffer Designg

• New clock buffer with built-in RCfilterO ti l RC l l t d i• Optimal RC value selected using the revised timing models to enhance beneficial jitter effect

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j• IR drop < 50mV

Calculation of Optimal Phase Shift

0.3

0.4

f0.1

0.2

2πφπ

=+ shiftcp

res

ff

I t iti l ti

-0.1

0

0 1 2 3

• Intuitive explanation– : Phase difference caused by clock path delay

Ph diff b t l t l i t dcp

res

ff π

π– : Phase difference between largest slope point and lowest supply point

• Revised simple model used assuming ideal

2π

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Revised simple model used assuming ideal phase shift

Timing Slack Improvement65nm, 25°C,1.2V Vdd12% Vdd noise

• 75ps (or 15% Tclk) slack improvement• Phase-shifted clock distribution keeps timing slack• Phase-shifted clock distribution keeps timing slack

positive ensuring correct operation24

Effectiveness for Wide Band Noise65nm, 25°C,1.2V Vdd12% Vdd noise

• Phase-shifted design most effective for typical resonant frequency rangefrequency range

• Does not affect performance for other noise frequencies25

Partial Phase-Shifted Clock Distribution65nm, 25°C, 1.2V Vdd12% Vdd noise

• Using phase-shifted clock buffers only in the global clock network still improves timing slack

• Effectiveness of phase shifting technique can be traded• Effectiveness of phase-shifting technique can be traded off for die area

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Results SummaryyResonant Noise 200MHz

Clock Frequency 2GHz

65nm, 25°C, 1.2V Vdd, 12% Vdd noise

q y

Intrinsic Decap C* 6nF

Package Inductance L* 0.1nHInductance LLoad Current* 1A

R in RC Filter 300 Ω

C in RC Filter 2pF

Phase Shift 0.2πSlack 75 (15% T )Slack Improvement 75ps (15% Tclk)

Equivalent Decap 24nF

D S i 80%

*The L, C and load current values are scaled down proportionally to account for the smaller clock tree used in our

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Decap Saving 80% test setup.

Conclusions• Resonant noise is an important concern for

power supply network designspower supply network designs• Inherent timing compensation between clock

and data improves timing slackand data improves timing slack• Timing models proposed to accurately describe

this beneficial jitter effectthis beneficial jitter effect• Phase-shifted clock distribution proposed

E h b fi i l jitt ff t– Enhances beneficial jitter effect– Slack improvement by 15% Tclk

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– Performance equivalent to 5X larger decap