erd and memory architectures paul franzon department of electrical and computer engineering...
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ERD and Memory ArchitecturesERD and Memory Architectures
Paul Franzon
Department of Electrical and Computer Engineering
919.515.7351
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High Level OverviewHigh Level OverviewChallenges for Memories
Power consumption Bandwidth Resiliency Scaling (density, speed, power)
Opportunities Increased use of memory in logic and routing Using ERD devices to help ERD memories scale Intersection with 3DIC
Impact on Memory Architectures Scope for new and more specialized memory
architectures Mobile; (Cloud) Computing; SSD; Structured ASIC;
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Challenge: BandwidthChallenge: Bandwidth
Soon to exceed 1 TBps Key challenge: Power: DDR3 would consume
600 W at this bandwidth
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Challenge: Power ConsumptionChallenge: Power Consumption Memory hierarchy is becoming the largest single
consumer of the power in a computer Consumes 30%+ of power in today’s servers E.g. DARPA Exascale computing study
Note: This assumed DRAM power was reduced from 600 pJ/bit to 3 pJ/bit
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Challenge: ResiliencyChallenge: Resiliency
Issues: SEU of SRAM Checkpointing and resiliency of entire processor Future scaled systems could spend 80% of their time
checkpointing
Note: DRAM Failures almost all due to packaging
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Opportunity: PowerOpportunity: Power
Reduced capacitance associated with scalable 4F2 ERD memory technologies
Change RAM architecture Smaller sub-arrays Less
energy/access Low-swing interconnect Reduced overhead
Revisit memory hierarchy to optimize energy, not latency
Exploit 3DIC for energy reduction
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Challenge: ScalingChallenge: Scaling
Scaling Peripheral Circuits
Smaller memory sub-arrays increases overhead of sense amps and row/column decoders
4F2 cells increases overhead of sense amps and row/column decoders
Need: Technologies and techniques to reduce overhead of
peripheral circuits Circuit Solutions Use of ERDs Use of 3DIC to implement peripheral circuits in a circuit-
optimized technology
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Challenge: ScalingChallenge: Scaling
1R1D cells needed for resistive memories to ensure scalability (1R cells limits array size)
Impact of rectification ratio on scalability with 1R1D cell
On
:Off
Rat
io
Rectifcation
Memory Size
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Opportunity: Memory as Logic Opportunity: Memory as Logic
4F2 programmable ERD memory cells permit high density Look Up Tables and programmable logic Nanocrossbar CMOL
Potential for high-speed (low C) and high density Need to compare to logic ITRS to establish benchmark
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Opportunity: Memory as InterconnectOpportunity: Memory as Interconnect
Use programmable persistent memory elements as routable switchbox interconnect
Use high-density, low-overhead memory in NOC store/forward routing architectures
Example: Using a low-voltage nanocrystal flash device as an interconnect switch
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Other CommentsOther Comments
ERD as a Solid State Disk? Definitely an opportunity but it looks like magnetic disk
will always outscale solid state disk in density and cost/bit.
Instead use inside memory hierarchy, e.g. Disk cache, checkpoint store
ERD as Associative Memory, Bayesian inference calculator, etc.? Some ERD have analog behaviors that have yet to be
exploited or explored E.g. Memristor, Memcapacitor, Meminductor
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Other CommentsOther Comments
Memory in Logic 3DIC and 4F2 memory cells permits memory-heavy
architectures to be revisited But energy/bit-accessed has to better than
energy/FLOP for computation Real need are algorithms that increase spatial locality
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Outline of ERD ChapterOutline of ERD Chapter
Memory Challenges Table with metrics
Solution paths to these challenges Table with metrics
New Opportunities for ERD Architectural and circuit opportunities Review of current memory enhanced architectures???
Nanocrossbar, CMOL, Synaptic
Tables, largely qualitative, somewhat quantitative
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Feedback from GroupFeedback from Group
1. Quantify overhead of peripheral circuits as a function of core size
2. Latency matters too, both memory and interconnect. Typically traded for bandwidth. Quantify.