esterel and other projects

Copyright © 2001 Stephen A. Edwards All rights reserved

Esterel and Other ProjectsEsterel and Other Projects

Prof. Stephen A. Edwards

Columbia University, New York

www.cs.columbia.edu/~sedwards


OutlineOutline

Part 1• The Esterel language• My compiler for it (DAC 2000)

Part 2• New Esterel Compiler Infrastructure• Other projects


The Esterel LanguageThe Esterel Language

emit B;emit B; if C emit D;if C emit D;

Force signal B to be present in this cycle

Emit D if signal C is present



await A;await A; emit B;emit B; if C emit D;if C emit D; pausepause

Wait for next cycle with A present

Wait for next cycle



looploop await A;await A; emit B;emit B; if C emit D;if C emit D; pausepause endend

Infinite loop



looploop await A;await A; emit B;emit B; if C emit D;if C emit D; pausepause endend|||| looploop if B emit C;if B emit C; pausepause endend

Run concurrently



looploop await A;await A; emit B;emit B; if C emit D;if C emit D; pausepause endend|||| looploop if B emit C;if B emit C; pausepause endend

Same-cycle bidirectional

communication



every RESET doevery RESET do looploop await A;await A; emit B;emit B; if C emit D;if C emit D; pausepause endend|||| looploop if B emit C;if B emit C; pausepause endendendend

Restart when RESET present




Good for hierarchical

FSMs




Bad at manipulating

data


The New CompilerThe New Compiler


s=2

C

B

DC

B

A21 s

s=1

RESET

Esterel

Concurrent Control-Flow

Graph

Step 1: Translate




s=2

C

B

DC

B

A21 s

s=1

RESET

Esterel


Graph

Step 1: Translate

s=2

C

B

DC

B

A21 s

s=1

RESET

Scheduled CCFG

Step 2: Schedule




s=2

C

B

DC

B

A21 s

s=1

RESET

s=2

C

B

DC

B

A21 s

s=1

RESET

Esterel


Graph

Scheduled CCFG

Step 1: Translate

Step 2: Schedule

t=0 t=1

DC

s=2 s=1

RESET

A1 s

B2

B C

t0 1

Sequential Control-Flow

Graph

Step 3: Sequentialize




s=2

C

B

DC

B

A21 s

s=1

RESET

s=2

C

B

DC

B

A21 s

s=1

RESET

t=0 t=1

DC

s=2 s=1

RESET

A1 s

B2

B C

t0 1

Esterel


Graph

Scheduled CCFG

Sequential Control-Flow

Graph

Step 1: Translate

Step 2: Schedule

Step 3: Sequentialize

Void foo()Void foo(){{ switch (st) {switch (st) { 0: if (IN=3)0: if (IN=3) st = 5;st = 5; goto L5;goto L5; 1: if (RES)1: if (RES) st = 3;st = 3; goto L8;goto L8; }} L5: switchL5: switch}}

C

Step 4: Generate C




s=2

C

B

DC

B

A21 s

s=1

RESET

s=2

C

B

DC

B

A21 s

s=1

RESET

t=0 t=1

DC

s=2 s=1

RESET

A1 s

B2

B C

t0 1


EsterelC

Generated code is 2 to 100 faster

1/2 to 1the size




s=2

C

B

DC

B

A21 s

s=1

RESET

s=2

C

B

DC

B

A21 s

s=1

RESET

t=0 t=1

DC

s=2 s=1

RESET

A1 s

B2

B C

t0 1


EsterelC

Flow similar to Lin [DAC ‘98]


Step 1: Build Concurrent CFGStep 1: Build Concurrent CFG

every RESET do loop await A; emit B; if C emit D; pause end|| loop if B emit C; pause endend

RESET


Add ThreadsAdd Threads


RESET

Fork

Join


Split at PausesSplit at Pauses


21 s

RESET

2

1


Add Code Between PausesAdd Code Between Pauses


s=2

DC

B

A21 s

s=1

RESET


Build Right ThreadBuild Right Thread


s=2

C

B

DC

B

A21 s

s=1

RESET


Step 2: ScheduleStep 2: Schedule

s=2

C

B

DC

B

A21 s

s=1

RESETAdd arcs for

communication

Topological sort

Optimal scheduling: NP-Complete

“Bad” schedules OK


Step 3: SequentializeStep 3: Sequentialize

Hardest part: Removing concurrency

Simulate the Concurrent CFG

Main Loop:• For each node in scheduled order,

Insert context switch if from different thread Copy node & connect predecessors


Context Switching CodeContext Switching Code

s=0

r

0 21

s=1 s=2 s=3

Save state of suspending

thread

Restore state of resuming

thread


s=2

C

B

DC

B

A21 s

s=1

RESET

Run First NodeRun First Node

RESET RESET


s=2

C

B

DC

B

A21 s

s=1

RESET

Run First Part of Left ThreadRun First Part of Left Thread

B

A21 s

RESET

A1 s

B2


s=2

C

B

DC

B

A21 s

s=1

RESET

Context switch: Save StateContext switch: Save State

t=0 t=1

RESET

A1 s

B2


s=2

C

B

DC

B

A21 s

s=1

RESET

RejoinRejoin

t=0 t=1

RESET

A1 s

B2


s=2

C

B

DC

B

A21 s

s=1

RESET

Run Right ThreadRun Right Thread

t=0 t=1

C

B

RESET

A1 s

B2

B C


s=2

C

B

DC

B

A21 s

s=1

RESET

Context Switch: Restore StateContext Switch: Restore State

t=0 t=1

RESET

A1 s

B2

B C

t0 1


s=2

C

B

DC

B

A21 s

s=1

RESET

Resume Left ThreadResume Left Thread

t=0 t=1

DC

s=2 s=1s=2

DC

s=1

RESET

A1 s

B2

B C

t0 1


s=2

C

B

DC

B

A21 s

s=1

RESET

Step 3: FinishedStep 3: Finished

t=0 t=1

DC

s=2 s=1s=2

C

B

DC

B

A21 s

s=1

RESET RESET

A1 s

B2

B C

t0 1


Existing Esterel CompilersExisting Esterel Compilers

Simulation Speed

Capacityswitch (st) {case 0: st = 1; break;case 1:

Automata V3 [Berry ‘87], Polis [DAC ‘95]



Simulation Speed

CapacityA = B && C;D = A && E;

Logic gatesV4, V5 [Berry ‘92, ‘96]




Simulation Speed

CapacityA = B && C;D = A && E;

Logic gatesV4, V5 [Berry ‘92, ‘96]


CNET [CASES 2k]



Simulation Speed

Capacity

Logic gatesV4, V5 [Berry ‘92, ‘96] New

Compiler


CNET [CASES 2k]


Speed of Generated CodeSpeed of Generated Code

0.1

1

10

100

1000

100 1000 10000

Logic Gates+ Logic OptimizationNewAutomata

Size (source lines)

Average cycle time (s)


Size of Generated CodeSize of Generated Code

1

10

100

1000

10000

100 1000 10000

Logic Gates+ Logic OptimizationNewAutomata

Size (source lines)

Object code size (K)


Part 2Part 2

Present and Future Work


New ProjectsNew Projects

New Esterel compiler

Languages for Device Drivers

Languages for Communication Protocols


ESUIF ESUIF

New, open Esterel compiler designed for research• Source distributed freely

Based on SUIF2 system (suif.stanford.edu)

Modular construction

Standard compiler approach• Front end builds AST• AST dismantled into intermediate form• Intermediate form translated into low-level code• C code ultimately produced


ESUIF StatusESUIF Status

Front-end written, accepts large Esterel examples

Dismantlers partially complete: intermediate form defined

Linker (run statement expansion) to be implemented

Back-end to be implemented


Esterel Compilation PlansEsterel Compilation Plans

Apply discrete-event simulation techniques• Similar to the CNET compiler

Apply Program Dependence Graph representation• Concurrent representation used in optimizing

compilers

Apply “localized partial interpretation” to expand parts of the system into finite-state machines

Techniques will point the way for other synchronous, concurrent languages


Languages for Device DriversLanguages for Device Drivers

Device drivers are those pieces of software that you absolutely need that never seem to work

Tedious, difficult-to-write

Ever more important as systems incorporate customized hardware


Best To DateBest To Date

Thibault, Marlet, and Consel

IEEE Transactions Software Engineering, 1999

Developed the Graphics Adaptor Language for writing XFree86 video card drivers

Report GAL drivers are 1/9th the size of their C counterparts

No performance penalty


GAL S3 driver (fragment)GAL S3 driver (fragment)

chipsets S3_911, S3_924; What driver supports

port svga index := 0x3d4; Write address, then dataport misc := 0x3cc, 0x3c2;

register ChipID := sva(0x30); Logical register

serial begin Access sequence for register misc[3..2] <= (3,- , -, -, -) W; seq(0x12) <=> (-, PLL1, -, -, -) R/W;end;

identification begin Rules for identifying card1: ChipID[7..4] => (0x8 => step 2, 0x 9 => S3_928);2: ChipID[1..0] => (0x1 => S3_911, 0x2 => S3_924);


Future Device Driver WorkFuture Device Driver Work

Develop language for network card drivers under Linux

Study many existing implementations

Develop prototype language, compiler

Explore challenge of porting to other OSes

Apply lessons to other classes of drivers


Languages for Communication Protocols Languages for Communication Protocols Many optimizations for implementing protocol code

• Fast-path optimization• Collapsing layers

Tedious to implement manually

Tend to obfuscate code

Too high-level to be applied to, say, C code

Domain-specific language would allow these optimizations to be automated


SummarySummary

Esterel language

Esterel compiler based on control-flow graph

ESUIF: New Esterel compiler under development

Languages for Device Drivers

Languages for Communication Protocols

esterel and other projects

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