Ethernet Solutions withXilinx Processors

Xilinx, Inc.

2

Agenda

1. Introduction to Ethernet on FPGAs2. Hardware Components

– Processors, MACs, Boards

3. Software Components– Device Drivers & Stacks

4. Performance Tuning with HW Co-Processing– Protocol offload

5. Starting a Design with the Embedded Development Kit(EDK)

6. Demo and Design Examples7. Design Resources CD

3

Ethernet And TCP/IP Networking• Ethernet is the world’s most dominant

networking technology– 95%* of all LAN implementations use the

Ethernet protocol

– Over 750 million* Ethernet ports deployedworldwide

• TCP/IP is the most popular networkingprotocol

– 4.3 billion IPv4 addresses projected to runout soon

• 80% of current FPGA users say theywill use one or more Ethernet ports intheir next generation product

* Source: Instat/MDR

Application: FTP, HTTP

Presentation

(Not Present)

Session (Not Present)

Transport : TCP, UDP

Network : IP

Physical Layer (PHY)

Data Link : 802.x (MAC)

HTTP Request

Ethernet IP TCP HTTP Request

IP TCP HTTP Request

TCP HTTP Request

4

Platform FPGAs: A Great Fit ForEthernet Applications

Application

PHY

Stack

Driver

EMACEthernet on FPGAs

Reduced board spaceReduced pins usageFlexibility: Implement in HW or SWExtreme Circuit Customization

-Application on PPC or MicroBlaze-Critical Code segments in Internal

Memory

-EMAC implemented in FPGA Fabric

-PHY interface using RocketIOMultiGigabit Transceivers

5

Ethernet Applications onFPGAs Hardware Components

• Embedded Processors• EMAC IP• Reference Designs• Xilinx Boards

6

Xilinx 32 Bit Embedded Processors

(DMIPs)

Performance100 300 600

5050

050

00

32-bit P450 MHz

684 D-MIPS

(Slices Used)

32-bit P950 Logic Cells

150 MHz108 D-MIPS

ComplimentaryPortable AcrossArchitectures

Faster

7

Xilinx Ethernet MAC Solutions

XAUI

10/100 1000 10,000

1G Ethernet MAC

GMII to 1000BASE-XPCS/PMA

10G Ethernet MAC

Throughput (Mbps)

10G Ethernet MAC FIFO

1G Ethernet MAC FIFO

Attach To Xilinx Processors

Standalone MAC

Reference Design

1G EMAC w/PLB

10/100 Ethernet MAC w/PLB back-end

10/100 Ethernet MACLite w/ OPB back-end

10/100 Ethernet MACw/ OPB back-end

Virtex-4 Trimode EMAC

Gigabit System Ref Des

8

10/100 Ethernet MACs

• There are 3 versions of the 10/100Ethernet MAC

– PLB 10/100 (PPC)– OPB 10/100 (MB or PPC)– OPB 10/100 Lite (MB or PPC)

• Supports– Features described in IEEE 802.3– MII and RMII PHY– Multiple options for speed, area and

feature tradeoffs• Accessible through Embedded

Development Kit (EDK)– Free evaluation version included– Eval is fully featured, but times out after

8-10 hours

Media Independent Interface (MII)Reduced Media Independent Interface (RMII)

Media Access Control (MAC)Full or Half Duplex

10 BASE-T 100BASE-TX/FX

PHY

Internal ToFPGA

External ToFPGA

9

EMAC Bus Attachment ArchitectureCustomize Your EMAC

• EMAC cores attach to theCoreConnect Bus usingXilinx’s IP Interface (IPIF)technology

• IPIF has a modular structureand allows user to selectivelyconfigure

– DMA : No DMA, Simple,Scatter Gather

– Packet FIFO depth– Core ID Register– Interrupt ID Register– SW Reset Module– DMA Interrupt Coalescing– Master/Slave Interface

MasterAttachment

Register

DMA&

S/G

ReadPacketFIFO

2K, 4K,8K,16K,32KB

WritePacketFIFO

2K, 4K,8K,16K,32KB Ethernet IPIF

IPIF Local Bus

TransmitData

SlaveAttachment

Rx

EthernetMAC

Tx

ReceiveData OPB

or

PLB

Bus

10

10/100 EMAC Comparison Chart

Raw Ethernet : 100 Mb/sRaw Ethernet : 100 Mb/sRaw Ethernet : 100 Mb/sMax Throughput

96Mb/s (Linux)TCP/IP Throughput

None, Simple, SGNoneNone, Simple, SG*DMA modes

Dynamically configurableConfigure at coregeneration time

Dynamically configurableHalf/Full Duplex

With MB, PPCWhen DMA, Statistics, SW

reset etc. features not required

600-800

OPB 10/100 Lite

With PPC(monitoring, control, config)

64 bit PLB data bus

2800-6100

PLB 10/100

With MB, PPC (monitoring, control, config)

32 bit OPB data bus

Typical use

Stats Gathering,VLAN, MIR, SW Reset

Configurable FIFO,

2000-3600Area (LUTs)

OPB 10/100Parameter

NY Y

*Scatter Gather

11

EMAC Solution in Spartan-3 For ~$4

• An EMAC system on a 3S1500occupies about 21% of theresources

– 5,775 out of 26,624 LUT’s• System includes

– Microblaze– OPB 10/100 EMAC– SDRAM Controller– UART– 8KB Internal Memory

• 3S1500 pricing starts at $20 (US)– Effective cost of the EMAC

system in S-3 as low as $4

OPB 10/100 EMAC

XC3S1500

SDRAMCntrl

12

PLB Gigabit Ethernet MAC(PLB GMAC)

• PLB GMAC attaches to theCoreConnect PLB Bus

• Support for– VLAN, Jumbo frames– Half/Full Duplex– Statistics gathering

• Choice of PHY interfaces– 8b GMII– PCS with TBI– Serial PHY

• Evaluation version accessiblethrough EDK

Media Access Control (MAC)Full or Half Duplex

SerialPMD

850 nm

Gigabit Media Independent Interface (GMII)

Serial LAN PCS (8B10B)

SerialPMD

1310 nm

CopperPECL

Copper PHYTen Bit

Interface

1000BASE-T1000BASE-X

CAT 5 UTP

Serial

InFPGA

InterfacesTo

13

DCR bus

Port 3

L L

(DMA Cont) DMAC

Port 2

DDR

LLGMACHost

I/F

Port 1Port 0

PPC405ISPLB

DSPLB

ChecksumOffload

Multi-Ported MemoryController

DMAC

Gigabit Systems Reference Design

• GSRD is a PPC405 reference designtuned for maximum Gigabit performance

• To achieve higher performance, GSRDuses a custom architecture and IP

– LocalLink Gigabit Ethernet MAC(LLGMAC, XAPP536)

– Communications DMA Controller(CDMAC, XAPP535)

– Multi Port Memory Controller (XAPP535)

• TCP transmit rates as high as 780 Mb/s– Ideal for applications requiring high

performance bridging between TCP/IPprotocol and user data interfaces

1

2

3

Flexibility of Platform FPGAs Key For Performance Tuning

14

GSRD: Custom ImplementationEnhances Performance

• Higher bandwidth with Multi PortMemory Controller

– Efficiently shares DDR SDRAMmemory resource betweenprocessor and DMA devices

– Allows point-to-point connectionbetween high bandwidth peripheralsand memory

• Transport Layer Checksum offload– Removes CPU from data path

• DMA with Data Realignment Engine– Allows for zero copy TCP/IP

Getting started with GSRDwww.xilinx.com/gsrd

15

Gigabit MAC Comparison Matrix

1000 Mb/s1000 Mb/sLink Throughput :raw Ethernet frames

780Mpbs**400Mb/sTCP/IP Packets (Treck Stack)TX, Jumbo Frames, 1MB TCP Window

Not Available750 Mb/sUDP Packets (VxWorks PNE)

Medium to High Bandwidth e.g. forbridging TCP/IP to user data sources

Medium Bandwidth requirementTypical Use Case

580Mbps*240Mb/sMax Linux TCP/IP PerformanceTX, Jumbo Frames, 16KB TCP Window

1000BASE-X, GMII

2900-6000 LUTs, 2400 FFs

8361 LUTs, 5653 FFs

PLB_GMAC

1000BASE-X, GMIIPhysical Interfaces

2946 LUTs, 2328 FFs

8490 LUTs, 5775 FFs

FPGA Resources : GMAC : System

GSRD with LLGMACParameter

* Checksum offload with sendfile() zero-copy** Checksum offload with Treck zero-copy enabled

16

Virtex-4 TriMode EMAC (TEMAC)

• 10/100/1000 Mb/s with auto-detect• Can be used standalone or with

embedded PPC405• Seamless connection to MGT• TX/RX Statistics gathering• Jumbo Frame Support• Processor can control the EMAC via

– Device Control Register*– A memory mapped host interface

• UNH compliance tested

• Accessible through EDK Version 6.3iSP1

405Core

ProcessorBlock

ISOC

M

ISPLB

DSPLB

DSOCMControl

ISOCMControl

DSOCM

Reset &Control

APU

APUControl

DCR

Test

DCRControl

Virtex-4 FX devices include2 or 4 dedicated TEMACs

Host

Interface

EMAC

PHY I/F

Statistics

I/F

Client I/F

EMAC

PHY I/F

Statistics

I/F

Client I/F

EMAC

Block

DCR

I/F

*DCR is part of IBM’s CoreConnect Bus

17

Hard EMAC Frees Up LogicResources In FPGA

+25%

+16%

+15%

+11%

# of EMACs/device 2 2 4 4

Logi

c C

ells

x10

00

GSRD Design in V-4 takesGSRD Design in V-4 takes15% less resources15% less resources

compared to Virtex-II Procompared to Virtex-II Pro

** Comparison based on 1G PLB EMAC implementation; Higher sav ings realized when TEMAC features like Tri-speed, RGMII, SGMII, addressmatch, multicast address table lookup are used

18

Partner EMAC Solutions

• Additional Ethernet solutionsare available from XilinxAllianceCORE partners

– CAST

– GDA Technologies

– Paxonet

– Zuken

– Amirix

19

RocketIO Interfaces With PHY

• RocketIO Multi-Gigabit Transceivers(MGT) in Xilinx FPGAs can interfaceGigabit MAC with the PHY

– Can implement 8B/10B function– Can implement Serdes function

• For Optical Carrier– RocketIO can directly drive Optical

Transceivers

• For Copper Carrier– MGT can implement an SGMII interface– SGMII reduces the number of pins

needed to interface with the PHY by~20

Serial SGMII

Optical

FPGA

BOARD

Copper

SFP

1000 Base-TPHY

PLB GMACLLGMAC

PLB GMACLLGMAC

20

Wide Choices Of Development Boards

• Evaluation boards search site: http://www.xilinx.com/xlnx/xebiz/board_search.jsp• Popular PPC boards

– Xilinx ML300 www.xilinx.com/ml300– Xilinx ML310 www.xilinx.com/ml310– Xilinx ML32X www.xilinx.com/ml321– Insight Virtex-II Pro Development Boards– Avnet Virtex-II Pro Development Kit

• Popular MicroBlaze Boards– Xilinx Multimedia board and ML401– Insight V2 and S3 MicroBlaze Development Kits– Avnet V2 and S3 Microblaze Evaluation Kits

ML3XX, ML4XX

21

Ethernet Applications onFPGAs Software Components

• TCP/IP Introduction• Device Drivers• TCP Stacks

22

TCP/IP Introduction

• TCP/IP is a set of protocols that allowsdevices to communicate across a network

• A Platform for a variety of network services– Newsgroups (NNTP)

– Electronic mail (SNMP and MIME)

– File transfer (FTP and ANS)

– Remote boot (bootp and DHCP)

– The World Wide Web (HTTP)

• Several TCP/IP SW Stacks supportingXilinx EMACs are available from Xilinx andits partners

SNMP, DNS, SMTP,SNMP, DNS, SMTP,

FTP, TELNET, HTTP,FTP, TELNET, HTTP,

NTP, ..NTP, ..

IP, ICMP, IP, ICMP, ……

Ethernet, Token Ring, Ethernet, Token Ring, ……

TCPTCP, UDP, , UDP, ……

ARP, RARP, ARP, RARP, ……

TCP/IP Protocol StackTCP/IP Protocol Stack

23

Xilinx Device Driver Architecture

• Xilinx drivers are based on a layeredarchitecture

– Layer 0 and 1 are considered lower layerdrivers which implement a rawcommunication protocol with the HW

– Layer 2 is an adaptor layer which binds anOS API to the HW using Layer 0 and Layer 1

• Xilinx Platform Studio (XPS) generatesthe device drivers

– L0 and L1 drivers for all of its processor IP– L2 EMAC drivers provided for XMK and

VxWorks Operating Systems

Layer 0,1

TCP/IP Stack

Hardware(MAC)

eOS

Layer 2Device

Driver

Application

Kernel Access

Direct Access

24

Listing of TCP/IP StackSupport For Xilinx EMACs

• TCP/IP Stacks from Xilinx– lwIP

– Xilnet

• TCP/IP Stacks in Open Source– Linux (MontaVista)

– cLinux

• TCP/IP Stacks from Partners– WindRiver, TeamF1, QNX, ATI

Nucleus, GHS Integrity, Treck

25

Xilinx Provided TCP/IP Stacks

• Open Source TCP/IP library• Provides RAW API (EDK 6.2i)

and Sockets interface (EDK 6.3i)modes of operation

– Sockets interface requires use ofXilinx Micro Kernel (XMK)

• Compact code size relative toRTOS TCP/IP Stacks

– 90KB (raw mode)• Ideal for standalone applications

that require complete stackfunctionality like Telnet, FTP orWeb servers

• Xilinx in-house networkinglibrary (open source)

• Thin layered stack (~ 12KB)• Code Size more compact than

LWIP but supports a subset offeatures

• Provides sockets interfacemode of operation

• Limitation : Supports onlyserver functionality

• Ideal for network data transferapplications like TFTP

lwIP Xilnet

Both Processors Are Supported

26

Embedded Linux NetworkingSupport For Xilinx EMACs

• One of Linux’ key strength is its suite of networking protocols andapplications

– Stack comes free with Linux, open source– Well-tested with a mature sockets-based programming interface– Fully featured, i.e. IPv6 support– A large number of applications exist, e.g. web server

• Embedded Linux (PowerPC and Virtex-II Pro)– The Linux port for Virtex-II Pro is supported by MontaVista– TCP/IP Stack supports PLB 10/100, OPB 10/100 and PLB GMAC

• cLinux (Microblaze)– The port is maintained by John Williams @ U. of Queensland

www.itee.uq.edu.au/~jwilliams/mblaze-uclinux– TCP/IP Stack based on MontaVista’s driver for Xilinx EMAC– Networking support adds ~500KB to the kernel image

27

BSP Definition Filefor Tornado 2

VxWorks Networking Support ForXilinx EMACs

• Following VxWorks Stackssupport Xilinx 10/100 and 1GEMACs

– VxWorks Native Stack– PNE Router Stack– TeamF1 Stack

• Xilinx Platform Studio (XPS)writes out

– EMAC Layer 2 driver forVxWorks

– Custom BSP for WindRiverTornado IDE

Platform StudioProject Directory Name

GeneratedVxWorks BSPDirectory

XPSGeneratesVxWorks

BSP

28

Partner TCP/IP Support Matrix

SG

SG

SG

SG*

DMASupport

YFrom Xilinx (XAPP546)1GTreck

NFrom Vendor10/100Integrity

YFrom Vendor10/100Neutrino

YFrom Vendor10/100Nucleus

YXPS10/1001G

Linux

YXPS10/100

1GVxWorks

Design Examples In“Ethernet Reference CD”

Reference BSPWhich MACSupported

* Scatter Gather

29

Accelerating TCP Stack In HW• Checksum Offload

30

FPGA Flexibility Enables HardwareAcceleration

• Key advantage of FPGAs is flexibility– Designs can be custom partitioned

between HW and SW at any point in thedesign cycle

• Identifying functions suitable foracceleration

– Profile SW Code to identify CPUconsuming “bottleneck” functions

– Analyze area speed trade-off and selectfunctions to offload

• TCP Stack has several candidates thatare suitable for acceleration

– Checksum– Forwarding Engine (Routing)– IPSEC, Encryption

ProtocolStack

PerformanceBased

Partitioning

PowerPC 405Microblaze

FPGAfabric

Memory

31

Checksum Offload Implementation

• Processor incurs severe penalty for checksumcomputation

– Ethernet packet ingress to memory– PPC extraction of header from memory– Processing of header with software and data

structures from memory– Processed packet assembled in memory– Egress of packet to the host

• Functionality can easily be offloaded into FPGAfabric

– Simple state machine implements and inserts thechecksum logic

– Implemented in ~ 100 LUT’s• Software stack needs minor corresponding change

– Many TCP/IP stacks have pre-built support forchecksum offload

TX DMADescriptor

ChecksumComputeControlInsert

MUX

TX FIFO

GMAC

TX LocalLinkDataStream

CSUM FIFO

32

Transmit Performance Comparisonwith Checksum Offload

158

355

491

785

0

100

200

300

400

500

600

700

800

1500 Byte Packet 9000 Byte Packet

Checksum in SW

Checksum in HW

- Zero Copy API, 1MB TCP Window- Treck TCP/IP Stack

(Jumbo Frames)

2.2X

1.8X

Mbs

GSRD

33

Getting Started With YourXilinx Design

• Embedded Development Kit (EDK)

34

Application Compile

Kernel ConfigDevice Drivers

Header Files

HW Netlist

Simulation FilesDebug Tools

High Level Embedded Flow

.elf .bit

Xilinx PlatformStudioEmbedded IDE

HW Platform Assembly

35

Data2MEM

Download Combined

Image to FPGA

Compiled ELF Compiled BIT

RTOS, Board Support Package

Embedded

Development Kit

Detailed Embedded FlowWith EDK & ISE

Instantiate the ‘System Netlist’ and Implement

the FPGA

?

HDL Entry

Simulation/Synthesis

Implementation

Download Bitstream

Into FPGA

Chipscope

Standard FPGA

HW Development Flow

VHDL or Verilog

System Netlist

Include the BSPand Compile theSoftware Image

?

Code Entry

C/C++ Cross Compiler

Linker

Load Software

Into FLASH

Debugger

Standard Embedded

SW Development Flow

C Code

Board Support

Package

12 3 Compiled BITCompiled ELF

36

With Base System Builder Wizard in XPS,you can build a HW system in minutes!!

Step 1: Build HW Reference Design

• Using XPS, assemble a HWreference design with– Processor: PPC/MB

– Memory: Internal, External

– Peripheral: EMAC, UART, GPIO etc.

• Configure the EMAC and otherperipherals using appropriatemenu functions

• Generate the HW .bit file

• Download to FPGA using Xilinxcable

37

Step 2: Create Design Specific BSP

• Select target EmbeddedOperating System ifapplicable

• Set device driver options

• Generate the BSP– Generated libraries are

customized to the selectedoperating system

38

Step 3: Develop Your SW Application

• Switch to your favorite IDE towork on your Application

– Xilinx provides an Eclipse-basedIDE for application development

• Use the BSP created by XPS toolto create the OS kernel image andSW application for the targetembedded processor

• Generate the executable .elf• Download .elf to board using

Xilinx cable

TCP/IP library

OS kernel

Select OS

eOS IDE

include files

Config files

Header files

…

Compiler

User App

XPS

39

Ethernet Demo and Examples

40

Client Server Demo Over Ethernet

Video Framesin SDRAM

GigEMAC

SGDMA

ETHERNET

PPC405

Demo Theme: 1. Connectivity2. Bandwidth

Mem C

VNC Client

Fiber2

Copper

TreckTCP/IP Stack

MGTGBIC

VNC Server(Application)

41

High Resolution Imaging Over Ethernet

ImageProtocol

Interface toMicroscope

Gb Optics

Ethernetinterface to

WorkStation

GSRD takes bus protocol fromMicroscope and processes

Images to remote Workstationfor storage and analysis

42

A Power Monitoring/Control Unit- An old and outdated System- Monitors and Controls the power

system for Telecom equipment- Operated by a simple command

line interface over RS232

InternetEthernet

Remote Monitoring & Control

RS232

Legacy ImplementationMicroBlaze Enables Remote Monitoring/Control

Hardware: Microblaze, 10/100 MAC, UART, GPIOSoftware: XMK, Http server, SNMP agent, HTML pages- Monitor parameters acquired by the controller (volts, amps, usage..)- Configure the controller settings (set alarm conditions, ..)- Operate the Controller and the associated Power System

43

Other Sample Applications

• Storage Solutions:– RDMA

– iSCSI Bridging

• High-Speed and Reliable Remote Image/VideoCapture

– Medical Imaging, Military, Industrial, etc

• FPGA updates itself over IP network

44

Take Home Reference Design CD

• A Design Reference CD isavailable for help starting yournext Xilinx Ethernet design

• The Reference CD contains– Datasheets/Appnotes– GSRD Reference Design– PLB GMAC Reference Design– Web server design example– Examples based on TCP/IP

stacks from Xilinx and its Alliancepartners

Ethernet Reference Design CD

Reference DesignsTCP/IP Stacks

AppnotesDatasheet

45

Ethernet Examples BasedOn TCP/IP Stacks

•Linux

•

•

TeamF1(VxWorks)

•QNX

•lwIP

•

•

Treck

•

•

Mentor Graphics

Contents on CDStack Source

Ethernet Reference Design CD

Reference DesignsTCP/IP Stacks

AppnotesDatasheet

46

Summary

• Xilinx provides a wide range of options to fityour next Ethernet application

– Cost: Implement an Ethernet system onSpartan-3 for as low as $4

– Performance: TCP/IP Transmissions speeds ofup to 780 Mb/s with GSRD

• Xilinx SW makes it very easy to get startedeven if you are a first time user

– Base System Builder Wizard: ~20 mouseclicks to design completion

• Jump start your next Ethernet Design– A number of design examples are provided for

you on the “Ethernet Reference Design CD”

47

Appendix

48

Audience Poll

• How many of you have– Heard about Xilinx processors– Have used a Xilinx processor– Are SW or HW engineers– Have attended the previous embedded track sessions

• How many need > 650 DMIPS in their application– Processor preference :PPC, MB or both

• EMAC Preference 10/100 v 1G EMAC– Is the processor in the high-speed data path (producer or

consumer of data)?• How many use an embedded OS, which one

49

Glossary Of Terms

• XPS: Xilinx Platform Studio. SW to designwith Xilinx processors

• EDK: Bundling on XPS with Processor IP

• lwip: Light Weight Internet Protocol TCP/IPStack

• IP: Intellectual Property, pre-engineeredblocks of logic implementing specificfunctions

• EMAC: Ethernet MAC

• GEMAC: Gigabit Ethernet MAC

• TEMAC: Tri-Mode Ethernet MAC

• GSRD Gigabit Ethernet Reference Design

• Protocol: A formal specification of howthings should communicate. Think of it asthe language used for networks tocommunicate with each other.

• OSI: Open Systems Interconnection. Thestandard model to describe how computernetworks should work.

• Transmission Control Protocol/InternetProtocol (TCP/IP) is a group or suite ofprotocols that is widely used innetworking. The Internet uses TCP/IP.

• TCP Stack: Library of functions thatimplement various layers of thecommunication protocol in Software

50

Xilinx EMAC Summary Sheet• OPB 10/100 EMAC

The OPB 10/100 EMAC core provides an Ethernet Media Access Control function running at 10 Mbps and 100 Mbps (Fast Ethernet),designed to the IEEE 802.3 specification.

• OPB 10/100 EMAC LiteThe OPB EMAC Lite is a reduced version of the OPB 10/100 Ethernet MAC (EMAC). Like the EMAC core, it supports an IEEE 802.3Media Independent Interface (MII) for interfacing to industry standard Physical Layer (PHY) devices.

• PLB 10/100 EMACThe PLB EMAC is a 10/100 Ethernet MAC which includes an interface to the Processor Local Bus (PLB). It has been designed to theIEEE Std. 802.3 specification.

• 1GEMACThe GEMAC core is designed to the IEEE 802.3-2002 specification and can be user-configured with your choice of three PHY sideinterface options: a GMII interface, a 1000BASE-X PCS with Ten Bit Interface (TBI), or an integrated 1000BASE-X PCS/PMA forsimplified board design.

• PLB GEMACThe PLB Gigabit Ethernet Media Access Controller (PLB GEMAC) IP core delivers Gigabit Ethernet MAC functionality along with abuilt-in 64-bit IBM Processor Local Bus (PLB) interface for seamless connection to the PowerPC® core in Virtex-II Pro™ FPGAs.

• Ethernet 1000BASE-X PCS/PMAThe Xilinx Ethernet 1000BASE-X PCS/PMA LogiCORE module supplies an Ethernet Physical Coding Sublayer (PCS) with a choice ofeither a 1000BASE-X Physical Medium Attachment (PMA) using the integrated RocketIO™ Multi-Gigabit Transceivers in Virtex-IIPro™, or a parallel Ten-Bit Interface for connection to industry standard gigabit Ethernet SerDes devices.

• 10GEMACThe 10-Gigabit Ethernet Media Access Controller IP core is designed to the IEEE 802.3ae-2002 specification and can be configuredwith either an XGMII interface or with a XAUI interface for simplified board design..

• XAUIThe Xilinx 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE provides a 4-lane high-speed serial interface, providing up to 10Gigabits per second (Gbps) total throughput

51

Coming in GigabitEthernet MAC v5.0

• Virtex-4 Support• 1000BASE-X PCS/PMA support will be available as a standalone

module only– Users will have to connect up the 1000BASE-X core manually– New HDL wrappers will be provided– Will make delivery of SGMII and RGMII support easier for Tri-Speed MAC

• Add– User Guide, Design Example

• Remove– Half Duplex support– Distributed Memory option for statistics counter implementation

• Target release date: Q3CY04

52

Ethernet Standards

Media Access Control (MAC)Full Duplex (802.3x) or Half Duplex

GMII

1000 Base-X PHY8B/10B auto-negotiation

1000Base-LX fiber-

optic

1000Base-SX fiber-

optic

1000Base-CX Copper

1000Base-T/TX PMA

1000Base-T/TX PCS

802.3ab

MultimodeFiber

(220-500m)

Single/Multi-mode

Fiber (.55-5KM)

ShieldedCopper Cable

(upto 25m)

CAT5/6 UTP(upto 100m)

10/100Base PHY4B/5B auto-negotiation

10/100Base-

T/TX/FX etc

Da

ta lin

kla

ye

rP

hys

ica

lla

ye

r

53

Code Size for lwIP and Xilnet

800ip.o

828udp.o

2063eth.o

11 KBTotal

3409xilsock.o

2704tcp.o

484arp.o

240icmp.o

16mac.o

Text Size in bytesFilename

10956tcp_out.o

14730etharp.o

21904tcp_in.o

8976ip.o

94 KB (raw API)Total

9455tcp.o

4744inet.o

4740ip_frag.o

4244icmp.o

4212netif.o

3756pbuf.o

2538xemacif.o

Text Size in bytesFilenameLWIP Xilnet