© Semiconductor Components Industries, LLC, 2017

May, 2018 − Rev. 21 Publication Order Number:

EVBUM2529/D

EVBUM2529/D

RSL10 Evaluation andDevelopment Board User's Manual

INTRODUCTION

PurposeThis manual provides detailed information about the

configuration and use of the RSL10 Evaluation andDevelopment Board (RSL10−002GEVB). The Evaluationand Development Board is designed to be used with thesoftware development tools to evaluate the performance andcapabilities of the RSL10 radio System-on-Chip (SoC).

Manual OrganizationThe Evaluation and Development Board Manual contains

the following chapters and appendices:• Chapter 1: Introduction describes the purpose of this

manual, describes the target reader, explains how thebook is organized, and provides a list of suggestedreading for more information.

• Chapter 2: Overview provides an overview of theEvaluation and Development Board described in thismanual.

• Chapter 3: Evaluation and Development Boardprovides the details of the Evaluation and DevelopmentBoard. The chapter is divided into the following topics:♦ Development Board Setup♦ Development Board Design♦ Power Supply♦ Level Translators♦ LED Circuitry♦ RSL10 SoC♦ Measuring the Current Consumption♦ SWJ−DP Debug Port♦ Digital Input/Output (DIO)♦ Power Supply and Test Points

• Appendix A: Connectors provides a complete list ofthe connectors and jumpers on the Evaluation andDevelopment Board.

• Appendix B: Schematics contains the schematics forthe Evaluation and Development Board.

• Appendix C: Bill of Materials contains a list of theparts that are used to manufacture the Evaluation andDevelopment Board.

Further ReadingFor more information, refer to the following documents:

• Getting Started with RSL10

• RSL10 Firmware Reference

• RSL10 Hardware Reference

• RSL10 Datasheet

OVERVIEW

IntroductionThe RSL10 Evaluation and Development Board is used

for evaluating the RSL10 SoC and for applicationdevelopment. The board provides access to all input andoutput connections via 0.1″ standard headers. The on-boardcommunication interface circuit provides communication tothe board from a host PC. The communication interfacetranslates RSL10 SWJ−DP debug port signals to the USB ofthe host PC. There is also an on-board 4-bit level shifter fordebugging; it translates the I/O signal level of RSL10 to the3.3 V digital logic level. It is not enabled by default; youenable it when it is needed.

Evaluation and Development Board FeaturesThe Evaluation and Development Board enables

developers to evaluate the performance and capabilities ofthe RSL10 radio SoC in addition to developing,demonstrating and debugging applications.

Key features of the board include:• J−Link onboard solution provides a SWJ−DP

(serial-wire and/or JTAG) interface that enables you todebug the board via a USB connection with the PC

• Alternate onboard SWJ−DP (serial-wire and/or JTAG)interface for Arm® Cortex®−M3 processor debugging

• Access to all RSL10 peripherals via standard 0.1″headers

• Onboard 4-bit level translator to translate the LPDSP32debug interface at low voltage to a 3.3 V JTAGdebugger

• Antenna matching and filtering network

• Integrated PCB antenna

• Compliance with the Arduino form factor

• Support for PMOD (i.e., J4 is a standard connector)

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EVALUATION AND DEVELOPMENT BOARD

Evaluation and Development Board SetupThis section is an overview of how to configure the

Evaluation and Development Board. Details of the

development board configuration are discussed later in thismanual.

Figure 1 represents an overview of the board setup.

Figure 1. Evaluation and Development Board Setup

RSL10Evaluation andDevelopment

Board

Micro USB Cable

If you want to use an external J−Link debugger instead ofthe onboard one, connect the debugger to connector P2 on

the QFN board, as shown in Figure 2. Notice that for thissetup, you also need a power supply.

Figure 2. Evaluation and Development Board Setup with External J−Link Debugger

Micro USB CableJ−LinkDebugger

10/9 Pin Connector

RSL10 Evaluation andDevelopment Board

P2 or JTAGPort

Power Supply

Evaluation and Development Board DesignThe following sections detail the various sub-circuits of

the RSL10 Evaluation and Development Board. The block

diagram in Figure 3 shows the locations of the variouscircuit sections. Figure 5 and Figure 6 provide3-dimensional illustrations of the QFN board.

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Figure 3. Circuit Location Block Diagram (Top View)

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Figure 4. Circuit Location Block Diagram (Bottom View)

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Figure 5. Three-Dimensional Line Drawing of the Board (Top View)

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Figure 6. Three-Dimensional Line Drawing of the Board (Bottom View)

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Power SupplyThe Evaluation and Development Board can be powered

by one of the following:• Micro USB port with regulator

• External power supply connector (P5) with regulator

• External power supply connector (P5) withoutregulator

Use the jumpers on pin headers P4, P7 and P10 to selecta power supply option as show in Table 1.

Table 1. POWER SUPPLY SELECTION

Power Source Jumper Position on P4 Jumper Position on P7 Jumper Position on P10

Micro USB Port with Regulator 1&2 2&3 1&2

External Power Supply with Regulator 3&4 2&3 1&2

External Power Supply without Regulator 5&6 2&3 2&3

Table 2. MINIMUM/MAXIMUM EXTERNAL REGULATED VOLTAGES

Power Supply Header

Input Voltage

Minimum Typical Maximum

RSL10 and J−Link OB MCU EXT−PSU Regulated 3.3 V 3.6 V 12.0 V

RSL10 and J−Link OB MCU USB − 5.0 V −

RSL10 EXT−PSU Unregulated 1.1 V 1.25 V 3.6 V

Level TranslatorsThe board has level translators for the DIO signals of

RSL10, including the clock signal. The level translatorsfacilitate interfacing to external devices that operate at ahigher voltage than RSL10.

VDDO and 3.3 V are two different power rails. Thetranslator allows a logic signal on the VDDO side to betranslated to either a higher or a lower logic signal voltageon the 3.3 V side, and vice-versa.

The level translation circuitry consists of components U4and the 2x4 header. Signals are translated from the VDDOvoltage reference to 3.3 V (default) voltage provided by theregulator output or by an external supply. The VDDOvoltage is configured by the pin on header P11 (located onthe board edge) to either VBAT_DUT, 3.3 V or other levelwithin the VDDO voltage range, which is 1.1 to 3.3 V.

The NLSX5014 level translators are bi-directional. Theyhave the following features:• Wide voltage operating range: 0.9 V to 4.5 V

• VDDO and 3.3 V are independent

• VDDO can be equal to, or less than, 3.3 V whenconnected to the power rail

To enable the level translators, populate positions R34 andR35 with 0 ohms. By default, the level translators aredisabled. NOTE: Enabling the level translator affects powerconsumption.

LED CircuitryThere are two LEDs on the board. One is a dual color LED,

called LD1, connected to the J−Link emulator

microcontroller unit (MCU). The other is the green LED,connected to DIO 6 of RSL10. You can use this LED withinyour applications as an indication LED by programmingDIO 6. If DIO 6 is high, this LED is on.

Measuring the Current ConsumptionThis section deals with measuring current consumption

for the Evaluation and Development Board.Headers are provided for each of the regulated voltages

for additional capacitance and/or for measurements. RSL10has 16 digital I/Os. The VDDO pin in header P9 configuresthe I/O voltages for power domains to VBAT. The VBAT pinin header P10 configures the VBAT source. The powerselect pin in header P4 configures the power source of theRSL10. In addition the measurements should be done byconnecting an ammeter to current measure header P3 tomeasure the device power consumption in isolation.

To measure the current consumption of RSL10 only, youneed to source the chip using the external power supplywithout the regulator as shown in Table 2. To removeleakage currents during current measurement, remove thejumpers on header SWD. Removing the jumpers betweenthe MCU and RSL10 that connect nRESET, SWDIO andSWCLK prevents current leakage from the JTAG interface,avoiding inaccurate current measurements. In addition,DIOs 4, 5 and 6 must be configured to High−Z (disabled)with no pull up in software. DIOs 4 and 5 are directlyconnected to the Atmel chip and will leak power into it. DIO6 is directly connected to the transistor driving the LED andcan leak power into it.

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SWJ−DP DEBUG PortThe J−Link adapters are typically used to communicate

with RSL10 using the standard Coresight SWJ−DP debugport in a JTAG/SW communication protocol. The 9-pin 0.05in Samtec FTSH header (P1), defined by the ArmCortex−M3 core on the board, connects RSL10 to externaladapters compatible with the Arm Cortex−M3 processor’sSWJ−DP interface. Alternatively, you can connect the microUSB port on the board to a PC.

DIGITAL Input/Output (DIO)RSL10 contains 16 digital I/O (DIO) signals. The DIO

voltage domain is VDDO, while the input voltage can beVBAT or external voltage as outlined in Section “Measuringthe Current Consumption” on page 7.

The DIO signals on RSL10 are multiplexed with severalinterfaces, including:• One I2C interface (DIO [7:8])

• Four external inputs to the low-speed analog to digitalconverters (DIO [0:3])

• One PCM interface

• Two PWM drivers

• Two SPI interfaces (DIO [13:15])

• One UART interface (DIO [4:5])

• Support interfaces that can be used to monitor controlof the RF front-end and Bluetooth® baseband controller

For more information about the DIO multiplexed signals,refer to the RSL10 Hardware Reference.

The board provides access to any of the DIOs or theirmultiplexed signals via the Arduino Headers (Power1,AD1, IOL1, and IOH1).

The LED circuit provides visual monitoring of the DIOs;refer to Section “LED Circuitry” on page 7 for furtherinformation.

Power SuppliesThere are several external power supplies available on

your Evaluation and Development Board.The user can also access signals on various headers on

boards, as described throughout this document.The external power supplies available for QFN boards

are:• VBUS, 5 V from USB connection − available only

when USB is plugged in• V3.3, 3.3 V from LDO − available when regulated

supply is selected• VEXT, (P5 header) unregulated external supply −

available when unregulated supply is selected• Battery (J5 Battery Holder, 12 mm coin cell battery)

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APPENDIX A − CONNECTORS

OverviewThis appendix lists all connectors on the Evaluation and Development Board. The sections that follow provide descriptions

for:• Jumpers and their possible configurations

• Headers

• Switches and their possible configurations

• Connectors

Configuration Header Jumpers

Table 3. JUMPER DESCRIPTIONS

Designator Description

P4 Regulated or Unregulated power supply selection

P10 VBAT Power Source selection (3.3 V, Vext or Battery)

P9 VDDO selection (VBAT_DUT, 3.3 V)

P8 VDD_AT selection (3.3 V, VDDO)

P1 Onboard JTAG debugger connection

Headers

Table 4. HEADER DESCRIPTIONS

Designator Description

POWER1 Arduino Power header 3.3 V, VDDO, nRESET, GND

AD1 Arduino Analog Inputs header A [0:3]

IOL1 Arduino IOL header UART, INT [0:1], SPI2

IOH1 Arduino IOH header I2C, SPI1

P2 External JTAG debug connection header

P3 Current measurement header

P5 External power supply header

P6 Input and output of level shifter

Switches

Table 5. SWITCH DESCRIPTIONS

Designator Description

SW1 Pushbutton switch to reset RSL10

SW2 Pushbutton switch for DIO5

Connectors

Table 6. CONNECTOR DESCRIPTIONS

Designator Description

J1 RF switch connector

J2 Micro USB port for power supply, JTAG and UART emulation

J3 MCU programming connector

J4 Digilent PMOD peripheral connector I2C, SPI1, INT0

J5 Battery Holder (12 mm coin cell)

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APPENDIX B − SCHEMATICS

This appendix contains schematics for the Evaluation and Development Board, version 1.3:• The Top-level (Arduino interface) schematic

• The RSL10 schematic

• The Interface MCU schematic

• The Power Supply schematic

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Figure 7. Top-Level (Arduino Interface) Schematic

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Figure 8. RSL10 SoC Schematic

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Figure 9. Interface MCU Schematic

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4k7

R14

4k7

R20

4k7

VD

D_A

TV

DD

_AT

VB

US

VB

US

IMC

U_T

MS

S

IMC

U_T

CK

S

IMC

U_T

DO

SIM

CU

_TD

ISIM

CU

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SET

R22

150

R23

150

R24

150

R25

150

R28

150

TR

STou

t

TR

ST

in

TD

Iout

TD

Iin

TM

Sout

TM

Sin

TC

Kou

t

TC

Kin

TR

ESo

ut

TR

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in

TD

Oin

TR

ST

in

TD

Iin

TM

Sin

TC

Kin

TR

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in

TD

Oin

RG

LD

1LT

ST−C

195K

GJR

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R15

220

R16

220

VD

D_A

T

C25

100n

F

C27

100n

F

DIO

4

DIO

5

R30

68 R31

68

DIO

4

DIO

5

EVBUM2529/D

www.onsemi.com14

Figure 10. Power Supply Schematic

VB

US

C43

DN

P

C40

C42

1uF

C41

1uF

Vin

1

GN

D2

EN

3N

/C4

Vou

t5

U3

NC

P5

51

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32

T1

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R32

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P

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DD

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56

P4

VL

1

I/O V

L1

2

I/O V

L2

3

I/O V

L3

4

I/O V

L4

5

NC

6

GN

D7

I/O V

cc4

8N

C9

I/O V

cc3

10I/O

Vcc

211

I/O V

cc1

12V

cc13

EN

14

U4

NL

SX50

14

VD

DO

C46

1uF

C47

10nF

R36

10k

C44

10nF

C45

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135

2467

8

P6

2x4

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R35

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R34

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23

IO0

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22

SC

L19

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123

AD

224

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IO1

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16

IO1

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17

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D

21U

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5

R51

10k

R41

10k

R42

10k

R43

10k

R44

DN

P

V3

.3

R45

0 R46

DN

PR

47

0

R48

DN

PR

49

DN

PR

50

DN

P

R52 0

R53 0

SC

L

SDA

DIO

[7..

0]

DIO

7D

IO6D

IO7

DIO

8

DIO

6

DIO

9

INT

0

SP

I_C

S

DIO

9D

IO8

DIO

[15..

8]

VIN

3.3

V

5V

V3.

3

C48

100n

F

1

2

3

J5 BA

T-H

LD

-01

2

21

3

P8

21

3

P9

VD

D_

AT

Sel

ect

VD

DO

Sel

ect

Opt

iona

l Lev

el S

hift

er

21

P5

21

P3

21 3

P7

21 3

P10

VB

AT

VB

AT

Sel

ect

3.3V

Sel

ect

Pow

er S

elec

t

SD

A SC

L INT

0

SP

I_C

S

PO

WE

R S

UP

PL

Y C

ON

FIG

UR

AT

ION

HE

AD

ER

S P

4,

P7,

P10

AR

DU

INO

OR

ION

PO

WE

RE

D V

IN3.3

V:

P4 (

no j

um

per

), P

7(1

-2),

P10(1

-2)

ST

AN

D A

LO

NE

US

B P

OW

ER

ED

: P

4(1

-2),

P7(2

-3),

P10(1

-2)

ST

AN

D A

LO

NE

Vex

t P

OW

ER

ED

: P

4(3

-4),

P7(2

-3),

P10(1

-2)

ST

AN

D A

LO

NE

US

B a

nd V

ext

PO

WE

RE

D:

P4(1

-2),

(5-6

), P

7(2

-3),

P10(2

-3)

(pro

vid

ed e

xte

rnal

ly).

Ran

ge

: 1

.1V

- 3

.3V

VD

DO

is

the

dig

ital

IO

rin

g s

up

ply

4.7u

F

4.7u

F

EVBUM2529/D

www.onsemi.com15

APPENDIX C − BILL OF MATERIALS

Table 7. BILL OF MATERIALS FOR RSL10 QFN EVALUATION AND DEVELOPMENT BOARD VERSION 1.3

Designator Description Footprint DocManufacturerPart Number

SupplierPart Number

AD1 Arduino Stackable Header 6-pin n/a SSQ−106−03−G−S SAM1198−06−ND

C2, C3, C4, C5, C6 Capacitor, NP0, ±2% 0402 GRM1555C1E120GA01D 490−8169−1−ND

C7 CAP CER 2.2 �F 10 V X5R 0402 0402 GRM155R61A225KE95D 490−10451−1−ND

C9, C16,C40 CAP CER 4.7 �F 10 V X5R 0603,CAP CER 4.7 �F 25 V X5R 0603

0603 GRM188R61A475KE15D 490−10477−1−ND

C11 Capacitor, NP0, ±2% 0402 GRM1555C1H101JA01J 490−7754−1−ND

C12, C13 CAP CER 1.5 PF 50 V NP0 0402 0402 GCM1555C1H1R5CA16D 490−13289−1−ND

C14 Capacitor, NP0, ±2% 0402 GRM1555C1E120GA01D 490−8169−1−ND

C10,C18, C19, C20,C21, C23, C25, C27,C29, C30, C31, C32,C33, C36, C37, C38,

C39,C48

Capacitor, NP0, ±2% 0402 GRM155R61E104KA87D 490−5920−1−ND

C22 Capacitor, NP0, ±2% 0402 GRM1555C1E100JA01D 490−6168−1−ND

C24, C34, C35 Capacitor, X5R, ±10% 0603 GRM188R61A106KE69D 490−10474−1−ND

C26, C28 Capacitor, NP0, ±2% 0402 GRM1555C1E180JA01D 490−6172−1−ND

C1, C8, C17, C41, C42,C45, C46

Capacitor, NP0, ±10% 0402 GRM155R61A105KE15D 490−3890−1−ND

C44, C47 Capacitor, NP0, ±2% 0402 GRM155R71H103KA88D 490−4516−1−ND

D1 Ultra low capacitance doublerail-to-rail ESD protection diode

SOT−143B PRTR5V0U2X,215 568−4140−1−ND

IOH1 Arduino Stackable Header 10-pin SSQ−110−03−G−S SAM1198−10−ND

IOL1, POWER1 Arduino Stackable Header 8-Pin SSQ−108−03−G−S SAM1198−08−ND

J1 Coaxial Connector with Switch COAXIAL−SWF MM8130−2600RA2 490−4981−1−ND

J2 MicroUSB−B−SMT FCI_10118193−0001LF 10118193−0001LF 609−4616−1−ND

J4 WR−PHD 2.54 mm Angled DualSocket Header, 12p

613012243121 S5559−ND

J5 HOLDER BATTERY 12 MM COIN 2996 36−2996−ND

L1 FIXED IND 3NH 800MA 170 MOHM SMD

0402 LQG15HS3N0S02D 490−6570−1−ND

L2 FIXED IND 1.8NH 950MA 100 MOHM

0402 LQG15HS1N8S02D 490−2613−1−ND

L3 Inductor, 320 mA, ±5% 0402 HK100515NJ−T 587−1521−1−ND

L4 Imported 0805 CKP2012N2R2M−T 587−2771−1−ND

LD1 Ultra bright AlInGaP Bi-Color LED LED_DUAL_0606 LTST−C195KGJRKT 160−1452−1−ND

LED 1 LED SMARTLED GREEN 570NM0603

0603 LNJ337W83RA LNJ337W83RACT−ND

P1, P4 Header 2x3 SMT 15−91−2060 WM17449−ND

P2 SAMTEC − CONN HEADER 10POSDUAL .05″ SMD KEYING SHROUD

FTSH−105 FTSH−105−01−F−DV−K SAM8796−ND

P3, P5 HEADER, 2POS, 1ROW; Series:961; Pitch Spacing: 2.54 mm; RA

961102−5604−AR 3M9467−ND

P6 2x4 Pin Header 15−91−2080 WM17450−ND

P7, P8, P9, P10 HEADER, 3POS, 1ROW; Series:961; Pitch Spacing: 2.54 mm;

961103−6404−AR 3M9448−ND

Q1 NMOS Transistor SOT65P210X105−3N RU1J002YNTCL RU1J002YNTCLCT−ND

R1, R2, R4, R9, R30,R31

Resistor, ±1%, 0.063 W 0402 ERJ−2RKF68R0X P68.0LCT−ND

EVBUM2529/D

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Table 7. BILL OF MATERIALS FOR RSL10 QFN EVALUATION AND DEVELOPMENT BOARD VERSION 1.3

DesignatorSupplier

Part NumberManufacturerPart NumberFootprint DocDescription

R3, R5, R6, R26, R27,R32,R44, R46, R48,

R49, R50,

Resistor, ±1%, 0.063 W 0402 ERJ−2RKF68R0X,ERJ−2RKF68R0X,ERJ−2RKF68R0X,ERJ−2GE0R00X,ERJ−2GE0R00X,ERJ−2GE0R00X,ERJ−2GEJ103X,ERJ−2GEJ103X,ERJ−2GEJ103X,ERJ−2GE0R00X,ERJ−2GE0R00X,ERJ−2GE0R00X,ERJ−2GE0R00X,ERJ−2GE0R00X,ERJ−2GEJ103X

P68.0LCT−ND, P68.0LCT−ND,P68.0LCT−ND,

P0.0JCT−ND, P0.0JCT−ND,173−8862,

P10KJCT−ND, P10KJCT−ND,P10KJCT−ND,

173−8862, 173−8862, 173−8862,173−8862, 173−8862, P10KJCT−ND

R7, R36, R40, R41,R42,R43, R51

Resistor, ±1%, 0.1 W 0402 ERJ−2GEJ103X P10KJCT−ND

R10, R11 Resistor, ±1%, 0.1 W 0402 ERJ−2RKF39R0X P39.0LCT−ND

R12, R13, R14, R20 Resistor, ±1%, 0.1 W 0402 ERJ−2RKF4701X P4.70KLCT−ND

R15, R16 Resistor, ±1%, 0.1 W 0402 ERJ−2RKF2200X P220LCT−ND

R17, R18, R19, R29 Resistor, ±1%, 0.1 W 0402 ERJ−2RKF6801X P6.80KLCT−ND

R21, R45, R47, R52,R53

Resistor, ±1%, 0.1 W 0402 ERJ−2GE0R00X P0.0JCT−ND

R22, R23, R24, R25,R28

Resistor, ±1%, 0.1 W 0402 ERJ−2RKF1500X 173−8862

R54 Resistor, ±1%, 0.1 W 0402 ERJ−2RKF1003X P100KLCT−ND

SW1, SW2 ALPS − SKHUALE010 − TactileSwitch, SPNO, SMD,

6.5 x 6.2 x 2.5 mm

ALPS_SKHUxxx010_WO_GND SKHUALE010 35−790−00

U1 RSL10 QFN

U2 IC MCU 32 bit 128 kB flash100LQFP

LQFP−100 ATSAM3U2CA−AU ATSAM3U2CA−AU−ND

U3 IC REG LIN 3.3 V 600MA 5TSOP TSOP−5IPC NCP114ASN330T1G NCP114ASN330T1GOSCT−ND

U4 TRANSLATOR LEVEL 4BIT14−TSSOP

TSOP65P640X120−14N NLSX5014DTR2G NLSX5014DTR2GOSCT−ND

U5 Remote 16-bit expander QFN50P400X400 PCA9655EMTTXG PCA9655EMTTXGOSDKR−ND

X1 ECS 48 MHz Crystal XTAL 4 pads ECS−480−8−47−JTN−TR XC1969CT−ND

X2 EPSON TOYOCOM − FC−13532.768 kHz ±20 PPM

XTAL_3215 FC−135 32.768KHZ 20PPM FC−135 32.7680KA−AC−ND

X3 XTAL SMD 3225, 12 MHz, 18 pF,±30 ppm

BT−XTAL_3225 7M−12.000MAAJ−T 887−1121−1−ND

See Jumper Location CONN JUMPER SHORTING GOLDFLASH

CONN JUMPER (2.54mm) Gold SPC02SYAN S9001−ND

See Installation MACHINE SCREW PAN PHILLIPS4−40

n/a NY PMS 440 0025 PH H542−ND

See Installation HEX STANDOFF 4−40 NYLON 3/8″ n/a 1902B 36−1902B−ND

NOTE: Designators C2, C3, C4, C5, C6 and R3, R5, R6, R26, R27, R32,R44, R46, R48, R49, R50 are not populated.

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