© Semiconductor Components Industries, LLC, 2018

June, 2018 − Rev. 01 Publication Order Number:

EVBUM2565/D

EVBUM2565/D

RSL10 SIP Evaluation andDevelopment Board User's Manual

INTRODUCTION

PurposeThis manual provides detailed information about the

configuration and use of the RSL10 SIP Evaluation andDevelopment Board (RSL10−SIP−001GEVB). TheEvaluation and Development Board is designed to be usedwith the software development tools to evaluate theperformance and capabilities of the RSL10 SIP radio.

Manual OrganizationThe Evaluation and Development Board Manual contains

the following chapters and appendices:• Chapter 1: Introduction describes the purpose of this

manual, describes the target reader, explains how thebook is organized, and provides a list of suggestedreading for more information.

• Chapter 2: Overview provides an overview of theEvaluation and Development Board described in thismanual.

• Chapter 3: Evaluation and Development Boardprovides the details of the Evaluation and DevelopmentBoard. The chapter is divided into the following topics:♦ Development Board Setup♦ Development Board Design♦ Power Supply♦ Level Translators♦ LED Circuitry♦ RSL10 SIP♦ Measuring the Current Consumption♦ SWJ−DP Debug Port♦ Digital Input/Output (DIO)♦ Power Supply and Test Points

• Appendix A: Connectors provides a complete list ofthe connectors and jumpers on the Evaluation andDevelopment Board.

• Appendix B: Schematics contains the schematics forthe Evaluation and Development Board.

• Appendix C: Bill of Materials contains a list of theparts that are used to manufacture the Evaluation andDevelopment Board.

Further ReadingFor more information, refer to the following documents:

• Getting Started with RSL10

• RSL10 Firmware Reference

• RSL10 Hardware Reference

• RSL10 SIP Datasheet

OVERVIEW

IntroductionThe RSL10 SIP Evaluation and Development Board is

used for evaluating the RSL10 SIP and for applicationdevelopment. The board provides access to all input andoutput connections via 0.1″ standard headers. The on-boardcommunication interface circuit provides communication tothe board from a host PC. The communication interfacetranslates RSL10 SIP SWJ−DP debug port signals to theUSB of the host PC. There is also an on-board 4-bit levelshifter for debugging; it translates the I/O signal level of theRSL10 SIP to the 3.3 V digital logic level. It is not enabledby default; you enable it when it is needed.

Evaluation and Development Board FeaturesThe Evaluation and Development Board enables

developers to evaluate the performance and capabilities ofthe RSL10 SIP in addition to developing, demonstrating anddebugging applications.

Key features of the board include:• J−Link onboard solution provides a SWJ−DP

(serial-wire and/or JTAG) interface that enables you todebug the board via a USB connection with the PC

• Alternate onboard SWJ−DP (serial-wire and/or JTAG)interface for Arm® Cortex®−M3 processor debugging

• Access to all RSL10 SIP peripherals via standard 0.1″headers

• Onboard 4-bit level translator to translate the LPDSP32debug interface at low voltage to a 3.3 V JTAGdebugger

• Integrated antenna (included as part of the RSL10 SIP)

• Compliance with the Arduino form factor

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EVALUATION AND DEVELOPMENT BOARD

Evaluation and Development Board SetupThis section is an overview of how to configure the

Evaluation and Development Board. Details of the

development board configuration are discussed later in thismanual.

Figure 1 represents an overview of the board setup.

Figure 1. Evaluation and Development Board Setup

RSL10Evaluation andDevelopment

Board

Micro USB Cable

If you want to use an external J−Link debugger instead ofthe onboard one, connect the debugger to connector P2 on

the SiP board, as shown in Figure 2. Notice that for thissetup, you also need a power supply.

Figure 2. Evaluation and Development Board Setup with External J−Link Debugger

Micro USB CableJ−LinkDebugger

10/9 Pin Connector

RSL10 Evaluation andDevelopment Board

P2 or JTAGPort

Power Supply

Evaluation and Development Board DesignThe following sections detail the various sub-circuits of

the RSL10 SIP Evaluation and Development Board. The

block diagram in Figure 3 shows the locations of the variouscircuit sections. Figure 5 and Figure 6 provide3-dimensional illustrations of the SiP board.

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Figure 3. Circuit Location Block Diagram (Top View)

Figure 4. Circuit Location Block Diagram (Bottom View)

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Figure 5. Three-Dimensional Line Drawing of the Board (Top View)

Figure 6. Three-Dimensional Line Drawing of the Board (Bottom View)

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Power SupplyThe Evaluation and Development Board can be powered

by one of the following:• Micro USB port with regulator

• External power supply connector (P5) with regulator

• External power supply connector (P5) withoutregulator

Use the jumpers on pin headers P4, P7 and P10 to selecta power supply option as show in Table 1.

Table 1. POWER SUPPLY SELECTION

Power Source Jumper Position on P4 Jumper Position on P7 Jumper Position on P10

Micro USB Port with Regulator 1&2 2&3 1&2

External Power Supply with Regulator 3&4 2&3 1&2

External Power Supply without Regulator 5&6 2&3 2&3

Table 2. MINIMUM/MAXIMUM EXTERNAL REGULATED VOLTAGES

Power Supply Header

Input Voltage

Minimum Typical Maximum

RSL10 SIP and J−Link OB MCU EXT−PSU Regulated 3.3 V 3.6 V 12.0 V

RSL10 SIP and J−Link OB MCU USB − 5.0 V −

RSL10 SIP EXT−PSU Unregulated 1.1 V 1.25 V 3.6 V

Level TranslatorsThe board has level translators for the DIO signals of the

RSL10 SIP, including the clock signal. The level translatorsfacilitate interfacing to external devices that operate ata higher voltage than the RSL10 SIP.

VDDO and 3.3 V are two different power rails. Thetranslator allows a logic signal on the VDDO side to betranslated to either a higher or a lower logic signal voltageon the 3.3 V side, and vice-versa.

The level translation circuitry consists of components U4and the 2x4 header. Signals are translated from the VDDOvoltage reference to 3.3 V (default) voltage provided by theregulator output or by an external supply. The VDDOvoltage is configured by the pin on header P11 (located onthe board edge) to either VBAT_DUT, 3.3 V or other levelwithin the VDDO voltage range, which is 1.1 to 3.3 V.

The NLSX5014 level translators are bi-directional. Theyhave the following features:• Wide voltage operating range: 0.9 V to 4.5 V

• VDDO and 3.3 V are independent

• VDDO can be equal to, or less than, 3.3 V whenconnected to the power rail

To enable the level translators, populate positions R34 andR35 with 0 ohms. By default, the level translators aredisabled. NOTE: Enabling the level translator affects powerconsumption.

LED CircuitryThere are two LEDs on the board. One is a dual color LED,

called LD1, connected to the J−Link emulator

microcontroller unit (MCU). The other is the green LED,connected to DIO 6 of RSL10 SIP. You can use this LEDwithin your applications as an indication LED byprogramming DIO 6. If DIO 6 is high, this LED is on.

Measuring the Current ConsumptionThis section deals with measuring current consumption

for the Evaluation and Development Board.Headers are provided for each of the regulated voltages

for additional capacitance and/or for measurements. RSL10SIP has 16 digital I/Os. The VDDO pin in header P9configures the I/O voltages for power domains to VBAT.The VBAT pin in header P10 configures the VBAT source.The power select pin in header P4 configures the powersource of the RSL10 SIP. In addition the measurementsshould be done by connecting an ammeter to currentmeasure header P3 to measure the device powerconsumption in isolation.

To measure the current consumption of RSL10 SIP only,you need to source the chip using the external power supplywithout the regulator as shown in Table 2. To removeleakage currents during current measurement, remove thejumpers on header SWD. Removing the jumpers betweenthe MCU and the RSL10 SIP that connect nRESET, SWDIOand SWCLK prevents current leakage from the JTAGinterface, avoiding inaccurate current measurements. Inaddition, DIOs 4, 5 and 6 must be configured to High−Z(disabled) with no pull up in software. DIOs 4 and 5 aredirectly connected to the Atmel chip and will leak power intoit. DIO 6 is directly connected to the transistor driving theLED and can leak power into it.

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SWJ−DP DEBUG PortThe J−Link adapters are typically used to communicate

with RSL10 SIP using the standard Coresight SWJ−DPdebug port in a JTAG/SW communication protocol. The9-pin 0.05 in Samtec FTSH header (P1), defined by theArm Cortex−M3 core on the board, connects RSL10 SIP toexternal adapters compatible with the Arm Cortex−M3processor’s SWJ−DP interface. Alternatively, you canconnect the micro USB port on the board to a PC.

DIGITAL Input/Output (DIO)The RSL10 SIP contains 16 digital I/O (DIO) signals.

The DIO voltage domain is VDDO, while the input voltagecan be VBAT or external voltage as outlined in Section“Measuring the Current Consumption” on page 5.

The DIO signals on the RSL10 SIP are multiplexed withseveral interfaces, including:• One I2C interface (DIO [7:8])

• Four external inputs to the low-speed analog to digitalconverters (DIO [0:3])

• One PCM interface

• Two PWM drivers

• Two SPI interfaces (DIO [13:15])

• One UART interface (DIO [4:5])

• Support interfaces that can be used to monitor controlof the RF front-end and Bluetooth® baseband controller

For more information about the DIO multiplexed signals,refer to the RSL10 Hardware Reference.

The board provides access to any of the DIOs or theirmultiplexed signals via the Arduino Headers (Power1,AD1, IOL1, and IOH1).

The LED circuit provides visual monitoring of the DIOs;refer to Section “LED Circuitry” on page 5 for furtherinformation.

Power SuppliesThere are several external power supplies available on

your Evaluation and Development Board.The user can also access signals on various headers on

boards, as described throughout this document.The external power supplies available for QFN boards

are:• VBUS, 5 V from USB connection − available only

when USB is plugged in• V3.3, 3.3 V from LDO − available when regulated

supply is selected• VEXT, (P5 header) unregulated external supply −

available when unregulated supply is selected• Battery (J5 Battery Holder, 12 mm coin cell battery)

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APPENDIX A − CONNECTORS

OverviewThis appendix lists all connectors on the Evaluation and Development Board. The sections that follow provide descriptions

for:• Jumpers and their possible configurations

• Headers

• Switches and their possible configurations

• Connectors

Configuration Header Jumpers

Table 3. JUMPER DESCRIPTIONS

Designator Description

P4 Regulated or Unregulated power supply selection

P10 VBAT Power Source selection (3.3 V, Vext or Battery)

P9 VDDO selection (VBAT_DUT, 3.3 V)

P8 VDD_AT selection (3.3 V, VDDO)

P1 Onboard JTAG debugger connection

Headers

Table 4. HEADER DESCRIPTIONS

Designator Description

POWER1 Arduino Power header 3.3 V, VDDO, nRESET, GND

AD1 Arduino Analog Inputs header A [0:3]

IOL1 Arduino IOL header UART, INT [0:1], SPI2

IOH1 Arduino IOH header I2C, SPI1

P2 External JTAG debug connection header

P3 Current measurement header

P5 External power supply header

P6 Input and output of level shifter

Switches

Table 5. SWITCH DESCRIPTIONS

Designator Description

SW1 Pushbutton switch to reset RSL10 SIP

SW2 Pushbutton switch for DIO5

Connectors

Table 6. CONNECTOR DESCRIPTIONS

Designator Description

J1 RF switch connector

J2 Micro USB port for power supply, JTAG and UART emulation

J3 MCU programming connector

J5 Battery Holder (12 mm coin cell)

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APPENDIX B − SCHEMATICS

This appendix contains schematics for the Evaluation and Development Board, version 1.3:• The Top-level (Arduino interface) schematic

• The RSL10 SIP schematic

• The Interface MCU schematic

• The Power Supply schematic

Figure 7. Top-Level (Arduino Interface) Schematic

GN

D

AD

01

AD

12

AD

23

AD

34

AD

45

AD

56

AD

1VIN

8G

ND

7G

ND

65V

53V

34

RE

SET

3IO

RE

F21

POW

ER

1

IO8

1IO

92

IO10

3IO

114

IO12

5IO

136

GN

D7

AR

EF

8SD

A9

SCL

10IO

H1

IOH IO

01

IO2

3IO

34

IO4

5IO

56

IO6

7IO

78

IO1

2

IOL

1

IOL

DIO

[15.

.0]

JTAG_TMSJTAG_TCK

RESET

TRSTinTDIin

TDOin

U_R

SL10

RSL

10.S

chD

oc

GN

D

TRSTinTDIin

TMSinTCKinTRESin

TDOin

DIO

4D

IO5

U_I

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face

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ace

MC

U.S

chD

oc

DIO

0D

IO1

DIO

2D

IO3

DIO

6

DIO

[15.

.0]

DIO

13D

IO14

DIO

15

DIO

10D

IO11

DIO

12

U_P

ower

Pow

er.S

chD

oc

VD

DO

5V

VIN

3.3V

2 1

3 45 6

P1 2x3

Pin

Hea

der

DIO

4D

IO5

DIO

8D

IO7

GN

DSP

I_C

LK

1SP

I_D

ATA

I1SP

I_D

ATA

O1

SPI1

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1SW

O/D

IO11

AR

EF

I2C

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A1

I2C

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K1

SWD

IO/D

IO13

SWD

CL

K/D

IO12

SPI_

DA

TAI2

/DIO

16IN

T2

SPI_

CL

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DIO

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M1

INT

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AR

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TX

UA

RT

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J7−B

B

J8−B

B

J20−

BB

VC

OM

3V3_

KN

X

RE

SET

IOR

EF

IOR

EF

5V GN

DG

ND

J21−

BB

A0

A1

A2

A3

I2C

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P_G

PIO

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9

RE

SET

JTAG_TCKJTAG_TMS

TDOinTDIinTRSTin

TMSinTCKinTRESin

GN

D

4 36 5

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Figure 8. RSL10 SIP Schematic

GN

D

DIO

0D

IO1

DIO

2D

IO3

DIO

4D

IO5

DIO

6D

IO7

DIO

[15

..0]

DIO

[15

..0]

JTA

G_T

MS

JTA

G_T

CK

R1

68 R2

68

RE

SET

R9

68R6

DN

P

R5

DN

P

R3

DN

PT

RST

in

TD

Iin

TD

Oin

DIO

13

DIO

14

DIO

15

VD

DO

C1

DN

P0603

C9

DN

PC

10D

NP

VB

AT

_DU

T

SW2

PB S

W

R7

10k

VB

AT

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T

SW1

PB S

WDIO

5

LE

D 1

L06

03G

R4

68

GN

D

V3.

3

DIO

6G

1

D

3

S

2

Q1

NM

OS

12

34

58

710

9

6

P2 FTSH

−10

5

VD

DO

JTA

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JTA

G_T

CK

TD

Oin

TD

Iin

RE

SET

RE

SET

JTA

G_T

MS

JTA

G_T

CK

TD

Oin

TD

Iin

TP1

TP2

TP3

TR

STin

R54

100k

VD

DO

DIO

8D

IO9

DIO

10D

IO11

DIO

12D

IO13

DIO

14D

IO15

OU

T_A

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F1

OU

T_M

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E1

DIO

0C

7

DIO

1B

6

DIO

2A

7

DIO

3A

6

DIO

4B

8

DIO

5A

8

DIO

6A

5

DIO

7B

7

DIO

8B

5

DIO

9C

2

DIO

10A

4

DIO

11B

3

DIO

12A

2

DIO

13B

1

DIO

15C

1

AO

UT

E8

WAKEUPF8

EN_TESTF7

NRESETE7

EXT_CLKC8

SWDCLKA3

TMS/SWDIOA1

GND

D1

GND

D2

GND

E2

DIO

14B

2

VDDOD7

F2

VBATD8

RSL

10_S

iP

J1

F3F4F5F6

G1G2G3G4

G6G7G8

G5

H1H8

J8

K1K8

L1

GNDL8

U1

SWD

CL

K

TM

S/SW

DIO

NR

ESE

T

TP4

VD

DO

VB

AT

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T

NR

ESE

T

RF_

50oh

m

GND

GNDGND

GNDGND

GNDGND

GNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGND

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Figure 9. Interface MCU Schematic

NRSTB47

PA0/TIOB0/NPCS126

PA1/TIOA0/NPCS227

PA10/TWCK0/PWML339

PA11/URXD/PWMFI040

PA12/UTXD/PWMFI141

PA13

/MIS

O10

PA14

/MO

SI11

PA15

/SPC

K/P

WM

H2

12

PA16

/NPC

S0/N

CS

113

PA17

/SC

K0/

AD

TR

G14

PA18

/TX

D0/

PWM

FI2

17

PA19

/RX

D0/

NPC

S318

PA2/TCLK0/AD12BTRG28

PA20

/TX

D1/

PWM

H3

19

PA21

/RX

D1/

PCK

020

PA22

/TX

D2/

RT

S1/A

D12

B0

5

PA23

/RX

D2/

CT

S121

PA24

/TW

D1/

SCK

123

PA25

/TW

CK

1/SC

K2

24

PA26

/TD

/TC

LK

225

RD/PCK0/PA2796

TK/PWMH0/PA2884 RK/PWMH1/PA2985

PA3/MCCK/PCK129

PA30

/TF/

TIO

A2/

AD

12B

16

PA4/MCCDA/PWMH030

PA5/MCDA0/PWMH131

PA6/MCDA1/PWMH232

PA7/MCDA2/PWML033

PA8/MCDA3/PWML137

PA9/TWD0/PWML238

PWMH0/A2/PB090 PWMH1/A3/PB191

D1/

DS

R0/

PB

1070

D2/DCD0/PB1193D3/RI0/PB1294 D4/PWMH0/PB1395

D5/

PWM

H1/

PB

1469

PB

15/D

6/PW

MH

216

PB

16/D

7/PW

MH

315

NA

ND

OE

/PW

ML

0/P

B17

68

NA

ND

WE

/PW

ML

1/P

B18

67

NR

D/P

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L2/

PB

1966

PWMH2/A4/PB292

NC

S0/P

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L3/

PB

2065

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E/R

TS2

/PB

2164

A22

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CL

E/C

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RD

Y/P

CK

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DHSDP76 DHSDM77 VBG78

DFSDM80

PB

3/PW

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PB

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K1/

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GNDBU46

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2

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R13

4k7

R14

4k7

R20

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VB

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VB

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IMC

U_T

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IMC

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IMC

U_T

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SIM

CU

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ISIM

CU

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R22

150

R23

150

R24

150

R25

150

R28

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STou

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220

R16

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F

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DIO

4

DIO

5

R30

68 R31

68

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4

DIO

5

DHSD_NDHSD_P

DFSD_NDFSD_P

TRSTin

TRESin

TRSTout

TRESout

CTSRTSRxDTxD

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Figure 10. Power Supply Schematic

VB

US

4.7μ

F

C43

DN

P

C40

4.7μ

FC

421u

F

C41

1uF

Vin

1

GN

D2

EN

3N

/C4

Vou

t5

U3

NC

P551

SN32

T1G

VB

AT

_DU

T

R32

DN

P

V3.

3V

DD

_AT

1 2

3 4

5 6

P4

VL

1

I/O

VL

12

I/O

VL

23

I/O

VL

34

I/O

VL

45

NC

6

GN

D7

I/O

Vcc

48

NC

9I/

O V

cc3

10I/

O V

cc2

11I/

O V

cc1

12V

cc13

EN

14

U4

NL

SX50

14

VD

DO

C46

1uF

C47

10nF

R36

10k

C44

10nF

C45

1uF

V3.

3

135

2467

8

P6 2x4

Hea

der

R35

0

R34

0

GN

D

VE

XT

V3.

3V

DD

OV

DD

O

R40

10k

VIN

3.3V

5V

V3.

3

1

2

3

J5 BA

T−H

LD−0

12

21

3

P8

21

3

P9

VD

D_A

T S

elec

tV

DD

O S

elec

t

Opt

iona

l Lev

el S

hift

er

21

P5

21

P3

21 3

P7

21 3

P10

VB

AT

VB

AT

Sel

ect

3.3V

Sel

ect

POW

ER

OPT

ION

S

EX

TE

RN

AL

PO

WE

R

CU

RR

EN

T

VR

EG

POW

ER

SU

PPL

Y C

ON

FIG

UR

AT

ION

HE

AD

ER

S P4

, P7,

P10

STA

ND

AL

ON

E U

SB

PO

WE

RE

D: P

4(1−

2), P

7(2−

3), P

10(1−

2)ST

AN

D A

LO

NE

Vex

t PO

WE

RE

D: P

4(3−

4), P

7(2−

3), P

10(1−

2)ST

AN

D A

LO

NE

US

B a

nd V

ext P

OW

ER

ED

: P4(

1−2)

, (5−

6), P

7(2−

3), P

10(2−

3)

VD

DO

is th

e di

gita

l IO

rin

g su

pply

(pro

vide

d ex

tern

ally

). R

ange

: 1.

1V −

3.3

V

EVBUM2565/D

www.onsemi.com12

APPENDIX C − BILL OF MATERIALS

Table 7. BILL OF MATERIALS FOR RSL10 SIP EVALUATION AND DEVELOPMENT BOARD VERSION

Designator Description Footprint Doc

AD1 Arduino Stackable Header 6-pin N/A

C9, C40, C43 CAP CER 4.7 �F 10 V X5R 0603, CAP CER 4.7 �F 25 V X5R0603

0603

C1, C10, C18, C19, C20, C21,C23, C25, C27, C29, C30, C31,C32, C33, C36, C37, C38, C39

Capacitor, NP0, ±2% 0402

C22 Capacitor, NP0, ±2% 0402

C24, C34, C35 Capacitor, X5R, ±10% 0603

C26, C28 Capacitor, NP0, ±2% 0402

C41, C42, C45, C46 Capacitor, NP0, ±10% 0402

C44, C47 Capacitor, NP0, ±2% 0402

D1 Ultra low capacitance double rail-to-rail ESD protection diode SOT−143B

IOH1 Arduino Stackable Header 10-pin

IOL1, POWER1 Arduino Stackable Header 8-Pin

J2 MicroUSB−B−SMT FCI_10118193−0001LF

J5 HOLDER BATTERY 12 MM COIN

LD1 Ultra bright AlInGaP Bi-Color LED LED_DUAL_0606

LED 1 LED SMARTLED GREEN 570NM 0603 0603

P1, P4 Header 2x3 SMT

P2 SAMTEC − CONN HEADER 10POS DUAL .05″ SMDKEYING SHROUD

FTSH−105

P3, P5 HEADER, 2POS, 1ROW; Series: 961; Pitch Spacing:2.54 mm; RA

P6 2x4 Pin Header

P7, P8, P9, P10 HEADER, 3POS, 1ROW; Series: 961; Pitch Spacing:2.54 mm

Q1 NMOS Transistor SOT65P210X105−3N

R1, R2, R4, R9, R30, R31 Resistor, ±1%, 0.063 W 0402

R3, R5, R6, R26, R27, R32 Resistor, ±1%, 0.063 W 0402

R7, R36, R40 Resistor, ±1%, 0.1 W 0402

R10, R11 Resistor, ±1%, 0.1 W 0402

R12, R13, R14, R20 Resistor, ±1%, 0.1 W 0402

R15, R16 Resistor, ±1%, 0.1 W 0402

R17, R18, R19, R29 Resistor, ±1%, 0.1 W 0402

R21, R34, R35 Resistor, ±1%, 0.1 W 0402

R22, R23, R24, R25, R28 Resistor, ±1%, 0.1 W 0402

R54 Resistor, ±1%, 0.1 W 0402

SW1, SW2 ALPS − SKHUALE010 − Tactile Switch, SPNO, SMD,6.5 x 6.2 x 2.5 mm

ALPS_SKHUxxx010_WO_GND

U1 RSL10 SIP N/A

U2 IC MCU 32 bit 128 kB flash 100LQFP LQFP−100

U3 IC REG LIN 3.3 V 600MA 5TSOP TSOP−5IPC

EVBUM2565/D

www.onsemi.com13

Table 7. BILL OF MATERIALS FOR RSL10 SIP EVALUATION AND DEVELOPMENT BOARD VERSION (continued)

Designator Footprint DocDescription

U4 TRANSLATOR LEVEL 4BIT 14−TSSOP TSOP65P640X120−14N

X3 XTAL SMD 3225, 12 MHz, 18 pF, ±30 ppm BT−XTAL_3225

See Jumper Location CONN JUMPER SHORTING GOLD FLASH CONN JUMPER (2.54 mm) Gold

See Installation MACHINE SCREW PAN PHILLIPS 4−40 N/A

See Installation HEX STANDOFF 4−40 NYLON 3/8″ N/A

NOTE: ON Semiconductor reserves the right to substitute materials for equivalent or similar parts.

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