evolution of mos device architecture

8/9/2019 Evolution of MOS Device Architecture

1/12

ECE 3020 Semiconductor Devices B. Lojek Fall 2014

1

Many todays business leaders are driven by Wall Street but do not

really understand the business they represent. They enjoy spending

others money. They claim that all is the question of Money Resources People. They have never realized that they have the

priority wrong. All is a question of People Resources Money.

Strong and creative individuality is priceless.

Evolution of MOS Device Architecture

MOS technology has undergone unprecedented evolution. For the past fifty years, MOS transistor scaling

has provided ever-increasing transistor performance and density. Interestingly enough, many people

predicted in each generation the end of scaling within one or two generation. However, each time the

technology reached the predicted barriers, scaling did not stop. There is no limit to engineering ingenuity;

however, there could be an economic limit when the cost of the scaled device would not be balanced by

benefits.

The Idea Shockley 1952

In 1952 Shockley1reported the unipolar field-effect transistor utilizing the depletion region of a reverse-

biased p-n junction to control the effective cross section of a bar of semiconductor material. An

illustration of the device is shown in Fig. 1.1. The ohmic contacts are referred as the source and drain to

emphasize the fact that they inject and remove only majority carriers. This is in contrast to the emitter and

collector in bipolar transistor. The conductive region between the ohmic contacts is referred as the

channel, with the reverse biased p-n junction space-charge control electrode (gate.) The concept of using

an external electric field normal to the surface of semiconductor to control the carrier density near the

surface was suggested by Shockley and Pearson in 1948.

1W. Shockley, A unipolar field-effect transistor. Proc. IRE, vol. 40 (1952), pp. 1365-1376


2/12


2

Fig. 1.1. Basic unipolar transistor structure.

Experimental measurements have confirmed the general predictions made for these structures and have,

in addition provided some specific information about surface states of the semiconductors. However, no

fully functional device was available until 1959 when M. M. Atalla reported that thermally grown silicon

dioxide has the property of passivating the surface and greatly decreases the density of deep surface traps.

The First Planar Device RCA 1962

Fig. 1.2. The planar metal-oxide-semiconductor field-effect transistor invented by Steven R.

Hofstein and Frederic P. Heiman and fabricated by G. A. Brown and R. R. Vannozzi, at RCA's

research laboratory in Princeton, New Jersey in 1962*

.

* [Electron Devices Meeting, Washington, D.C., October 25-27, 1962]

L ~ 125 m

tox~2000

xj~ 10 m

VDD = 15 -20 V


3/12


3

End of 1960s : PMOS with Metal Gate

L ~ 20 m

tox~1000

xj~ 3 m

VDD = 12 -20 VMain problem: oxide quality

Circa 1970 : NMOS with Metal Gate

L ~ 15 m

tox~800-1000

xj~ 3 m

VDD = 12 -15 V

(1974)

Constant Field Scaling

R. H. Dennard, F. H. Geansslen, H.-N. Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of Ion-

Implanted MOSFETs with Very Small Physical Dimension, IEEE J. Solid-State Circuits, SC-9 (5), p.

256 (1974)


4/12


4

Circa 1975 : NMOS with self-aligned Polysilicon Gate (HMOS High Performance MOS)

L ~ 5 m

tox~400-800

xj~ 1.5 m

VDD = 5 - 10 VThe structure took full advantage of ion-implantation by use of (a) threshold adjust implant, (b) punchthrough

implant, (c) source/drain implant.

(1978) VLSI CAD Methodology & Design Rules

I suggested to Carver that we deliberately design new, simplified MOS-LSI design methods,

deliberately aimed at not just the current expert digital system architect - - but more directly at

even the "budding, novice architect" - - making it so easy to get started that more of them would

try it, and work from architecture all the way to the layout level.

Lynn Conway

Introduction to VLSI Systems, published in late fall, 1979. Within a few years, this seminal text was adopted

for chip design courses at over 100 universities throughout the world.


5/12


5

Citation from the induction of Mead and Conway into the Electronic Design Hall of Fame, in 2002.

By the mid-1970s, digital system designers eager to create higher-performance devices were frustrated by

having to use off-the-shelf large-scale-integration logic. It stymied their efforts to make chips sufficientlycompact or cost-effective to turn their very large-scale visions into timely realities. In 1979, a landmark

book titledIntroduction to VLSI Systems changed all of that. Co-authored by Mead, the Gordon and BettyE. Moore professor of computer science and electrical engineering at the California Institute of

Technology, and Conway, research fellow and manager of the VLSI system design area at the Xerox PaloAlto Research Center, the book provided the structure for a new integrated system design culture that made

VLSI design both feasible and practical. Introduction to VLSI Systems resulted from work done by Meadand Conway while they were part of the Silicon Structures Project, a cooperative effort between Xerox and

Caltech. Mead was known for his ideas on simplified custom-circuit design, which most semiconductormanufacturers viewed with great skepticism but were finding increasing support from computer andsystems firms interested in affordable, high-performance devices tailored to their needs. Conway had

established herself at IBMs research headquarters as an innovator in the design of architectures forultrahigh-performance computers. She invented scalable VLSI design rules for silicon that triggered Mead

and Conways success in simplifying the interface between the design and fabrication of complex chips.The structured VLSI design methodology that they presented, the Mead-Conway concept, helped bringabout a fundamental reassessment of how to put ICs together.

.

Fig. 1.3. Page 34 from Conways Instructor Manual.


6/12


6

Circa 1985 : CMOS with N+ Polysilicon Gate, LOCOS isolation, TiSi Silicide,

and LDD implant

L ~ 0.75 - 1.0m

tox~200 xj~ 0.2-0.4 m

VDD = 5 V

Circa 1990 : CMOS with N+/P+ Polysilicon Gate, LOCOS isolation, and self-

aligned TiSi Silicide

L ~ 0.35 - 0.5 m

tox~120

xj~ 0.15 m

VDD = 3.3 - 5 V


7/12


7

Circa 1995 : CMOS with STI isolation, and P+ pocket (halo) implants

L ~ 0.15 mtox~60

xj~ 0.08 m

VDD = 5 V

Circa late 1990s : CMOS with STI isolation, and retrograde channel doping

L ~ 90 nmtox< 30

xj~ 0.06 m

VDD = 1.8 V


8/12


8

Scaling beyond 90 nm: Challenges and Opportunities

CMOS devices beyond 90 nm are facing a number of scaling challenges (see Fig. 1.4). Increase off-state

current offI from degraded drain-induced barrier lowering and subthreshold slope S caused by poor

short channel effects represents a significant limitation for shorter effective gate lengths. Decreasing gate

oxide thicknessoxt to provide better channel control results in increased gate leakage current and

increased channel doping. Increased channel doping results in decrease mobility and increase random

dopant fluctuation. Decreasing gate pitch increases the parasitic capacitance contribution for both contact-

to-gate and epi-to-gate thus increasing overall gate capacitance. Decreasing source/drain contact opening

increases the source/drain resistance thus decreasing drive current. Decreasing gate pitch decreases the

volume quantity of the stressor materials for both n-MOS (stress induced by overlying films) and p-MOS

(stress induced by embedded SiGe) and therefore decreasing mobility and drive current.

Fig. 1.4. Scaling challenges and opportunities.

FinFET device has been proposed to resolve the short channel effects (SCE). While FinFET provides a

significant resolution of drain-induced barrier lowering and SCE, it has its own challenges:

1) How to maintain high mobility enhancement from the stressor;


9/12


9

2) How to reduce capacitances

3) How to solve a generic source/drain resistance problem

4) How to deal with required exquisite control of etch and patterning of Fins

Intel's 45-nm High-k Metal-gate Process (2007)

Fig. 1.5. Intels 45 nm n-MOS and p-MOS device

The Problem of Planar MOS Device

It has been recognized, that device performance of 90 nm node and beyond has reduced drive current and

increased power consumption. The short-channel effects have several trade-offs, as shown in Fig. 1.6.

The power consumptionconsum

P and the on currenton

I can be approximated by:

/2010

TV S

consum L DD DD leak DDP fC V I V I V

+ + = ActiveP + StandbyP (1.1)

( ) ( ) ( ) ( )on surf DD DD G DD T DD

I N V V C V V V (1.2)

Where is a constant, f is operating frequency, LC is the load capacitance, 0I drain current for

DD TV V= , surfN is the surface carrier concentration in the channel, Sis the S factor, leakI is the total


10/12


10

leakage current including the gate and junctions leakages,GC is the gate capacitance, and is the

velocity.

Fig. 1.6 Factor affecting power consumption

In order to realize low power MOS device, lower DDV , higher TV , smaller S(higher immunity to short-

channel effects), and lower leakI are necessary. However, these requirements clearly conflict with those of

higheronI and are also inconsistent between themselves. According to (1.2), lower DDV and higher TV

lead to significant reduction ofon

I . In addition, thick gate oxideox

t , which is needed for reduction the

direct tunneling current, decreasesonI and increases Sbecause of lower GC . An increase in substrate

concentration ,surfN , is necessary to suppress short-channel effects and reduce S, but causes an increase

inleak

I due to junction tunneling current and gate induced drain leakage current.

As a consequence, new device architecture is needed to overcome these difficulties. The introduction of

channels with high carrier mobility and velocity was suggested as a solution of the scaling problem ofconventional planar devices. This is because the higher carrier mobility channel can provide not only

higheron

I due to higher but also can reduce DDV or increase oxt (i.e. lower GC ) under a constant value

ofon

I and thereby reduce the active or the standby power.


11/12


11

III-V Channel MOSFET (Mobility and Effective Mass Engineering)

Saturation of CMOS performance has been evident in the present 90 and 65 nm technology nodes because

of a variety of physical limitations. Channel engineering is recognized as one of approaches that can

improve behavior of the deeply scaled devices. The high mobility channel materials can enhance the drive

current. Due to their robustness against short channel effects they have currently been recognized as a

mandatory for high performance CMOS. In addition, III-V channel materials eliminate characteristic

dimensional variation of multi-gate structures which is very difficult to control.

Fig. 1.7. Concept of channel formation by selective growth of III-V materials on Si substrates.

Fig. 1.8. Channel formation by selective growth of III-V materials on Si substrate.


12/12


12

Si Ge GaAs InP InAs InSb

n [cm2/Vsec] 1600 3900 9200 5400 40000 77000

me/m0 0.19 / 0.916 0.82 / 1.467 0.067 0.082 0.023 0.014

p [cm2/Vsec] 430 1900 400 200 500 850

mh/m0 0.49 / 016 0.28 / 0.044 0.45 / 0.082 0.45 / 012 0.57 / 0.35 0.44 / 0.016Eg[eV] 1.12 0.66 1.42 1.34 0.36 0.17

Table. 1.1. Mobility, effective mass and band-gap of electrons and holes in principal semiconductors.

evolution of mos device architecture

Documents