excalibur chip - koreatech · 2016-10-31 · introduction to altera devices an industry leader in...
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Excalibur Chip
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Introduction to Altera devices
An industry leader in programmable logic– Inventor of the EPLD in 1983
Programmable Logic Families– Excalibur™ Embedded Processor Solutions
ARM®-Based, Nios II™
– SRAM Based
APEX™ II, APEX™ 20K, Mercury™, HardCopy™, ACEX™ 1K,
FLEX 10K®, FLEX® 6000, FLEX 8000, Cyclone, Cyclone II, Stratix,
Stratix GX, Stratix II
– EEPROM Based
MAX II, MAX® 3000, MAX 7000, MAX 9000, Classic™
Configuration Devices
Software development systems- Quartus® II, MAX+PLUS® II
한국기술교육대학교 임베디드SoC설계및실습2
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Features
32 Bit RISC Processor– Up to 200 MHz ARM922T™
High Performance .18 μm 8LM TSMC Process
AMBA™ Bus Architecture– Industry Standard Bus Architecture
Stripe Memory– Single Port and Dual Port
External Memory I/F– Embedded SDRAM/DDR SDRAM Controller (Dedicated Pin)
– Flash/EEPROM/SRAM (Through EBI Bus)
한국기술교육대학교 임베디드SoC설계및실습3
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Hard Processor PLD Architecture
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Device Summary
한국기술교육대학교 임베디드SoC설계및실습5
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Excalibur Device Packages
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Die Picture
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PLD Area for Customer Design
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Excalibur Stripe Components
32 Bit RISC ProcessorAHB1 & AHB2 BusesPLL SupportMemory
– Single Port
– Dual Port
– SDRAM Controller
Expansion Bus Interface (EBI)Peripherals
– UART
– Interrupt Controller
– Watchdog Timer
– Timer
Reset & Mode control
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Excalibur Stripe Components
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Excalibur MegaWizard
Select ARM®-Based™ Excalibur™– Easily create the desired stripe configuration
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MegaWizard
한국기술교육대학교 임베디드SoC설계및실습11
Hold processor inreset?
Select family anddevice
Boot from FLASH?
Endian?
Reserve pins
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Quartus II Symbol
Schematic Instantiation
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AHB in Excalibur
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AMBA High Performance Bus (AHB)
AMBA - Advanced Micro-controller Bus Architecture
Connects Embedded Stripe and PLD Devices
200MHz Maximum Clock Rate
32 Bit Wide Pipelined Bus– Burst transfers - one cycle per data word
– Non-tristate implementation
Multi-master With Distributed Address Decoding– Single-cycle bus master handover
Split Transactions Extensions– Needed to fully exploit bus bandwidth in a multi-master bus
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AHB1 Bus
Processor Is the Sole Master
Support for Locked Transfers
User Will Not Interface to This Bus
Highest Speed Bus Connection to Memory (200MHz)– SRAM
– SDRAM
– DDR RAM
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AHB1 Bus
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AHB2 Bus
Connects Processor Standard Cell to the PLD Master
and Slave Devices
3 Bus Masters– AHB1-2 bridge
– Configuration logic
– PLD master interface
Multiple Slave Devices
Supports Split Transaction– Needed to fully exploit bus bandwidth
Operates at Half the Frequency of AHB1
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AHB2 Bus
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MegaWizard
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Select Trace/Debug
Select the AHB2 to PLD bridges
Select Interrupt sources