exhibit 3 - imageeventphotos.imageevent.com/banos/ndocpacers82713/show_temp _5_.pdfthe memory bus...

Exhibit 3

Case5:08-cv-00877-PSG Document545 Filed08/27/13 Page1 of 6

HIGHLY CONFIDENTIAL – ATTORNEYS’ EYES ONLY

i

SUMMARY TABLE OF CONTENTS

1. BACKGROUND AND SUMMARY ...................................................................................... 1

2. RELEVANT LEGAL PRINCIPLES ....................................................................................... 4

3. SUMMARY OF MY OPINIONS ............................................................................................ 7

4. OVERVIEW AND BACKGROUND OF THE ASSERTED PATENTS ............................. 10

5. CLAIM CONSTRUCTION ................................................................................................... 52

6. ACER INFRINGES THE ’336 PATENT ............................................................................. 53

7. ACER INFRINGES THE ’890 PATENT ............................................................................. 82

8. HTC INFRINGES THE ’336 PATENT ................................................................................ 94

9. HTC INFRINGES THE ’890 PATENT .............................................................................. 126

10. CONCLUSION .................................................................................................................. 140



-24-

85. The program counter, X register, and Y register provide outputs to an internal address

bus, e.g., the Memory Bus.

86. The Memory Bus provides inputs to the Memory Controller. See OMAP730 Technical

Reference Manual, Figure 1-1 (TI-0000475); OMAP850 Technical Reference Manual, Figure 1-

1 (TI-0006862). In the case that the Program Counter, X register, or Y register holds an address

pointing to external memory, the internal address bus provides the address to the memory

controller.

87. The memory controller includes an address/data bus and a plurality of control lines for

connecting to random access memory. See LSI53Cl030 Ultra320 SCSI Controller Product Brief

at 1 (TPL853_01675894); LSI53C1030 Technical Manual, Figure 2.1 (TPL853_01817065).

88. ARM 9 processors have an apparatus for fetching and supplying either 32-bit ARM

instructions or 16-bit Thumb instructions in parallel. ARM926EJ-S Technical Reference Manual

at 1-2 (TPL853_01469641).

4.3.2 System Clock

89. “System clock” is a term used to refer to a clock that is used to clock the central

processing unit as well as other components that may be associated with it. Some variation of

the system clock is a required element of all Asserted Claims of the ’336 Patent, and also some

Asserted Claims of the ’890 Patent.

90. With the migration of the clock onto the same silicon chip, the methods of generating the

clock signal have evolved. The oscillator that generates the clock signal has to be integrated on

the chip, because the generation of a high frequency clock and bringing it onto the chip through

the outside pins is not possible. Such an on-chip oscillator is in most of the cases implemented

as a ring oscillator. The ring oscillator consists of a closed signal loop containing an odd number

of signal inversions, which is what makes the structure oscillate. The number of inverting stages

used will determine the natural frequency of the ring oscillator, i.e. the frequency at which it will

oscillate. That frequency can be adjusted by choosing an appropriate supply voltage for the ring

oscillator. Such an oscillator is known as a VCO (Voltage Controlled Oscillator). Sometimes,

instead of selecting a particular voltage, the current value is used instead. In such cases, the

oscillator is referred to as an ICO (Current Controlled Oscillator). Because the current and

voltage are related through Ohm’s law, using a VCO or ICO is simply a matter of design choice.



-25-

91. Many of the Accused Products include PLLs. A Phase Lock Loop (PLL) is circuitry that

is used to set the frequency of the free running ring oscillator VCO, to a desired range with

respect to the multiple (or some other rational number) of another oscillator frequency that is

used as a reference frequency. That other reference frequency is usually produced externally to

the chip and that oscillator is encapsulated in a noise free, temperature and voltage controlled

environment assuring the frequency stability of the reference signal. The external reference does

not produce the system clock and it is usually running at a frequency that is 100-200 times lower

than the frequency of the system clock. The system clock is always supplied by the on-chip ring

oscillator (VCO), which is set to a desired range (through the help of PLL) by using the second

reference oscillator frequency.

92. Ring oscillators are most commonly used in microprocessor PLLs to generate the system

clock signal. There are several reasons for ring oscillators to be used as VCOs: (1) they are built

of the same material as the rest of the chip and will exhibit the same change of parameters in

response to temperature, voltage and fabrication process parameters; (2) ring oscillators are

scalable to different process technologies (e.g., the same design can continue to be re-used, even

as the feature sizes on the silicon decreases); and (3) although crystal quartz oscillators have a

good frequency stability (based on the piezo-electric effect and their mechanical dimensions),

they cannot be integrated onto the silicon. In addition, the highest frequency of oscillation that

can be achieved using a quartz crystal is far below the system clock frequencies of today’s

processors. The reasons listed explain why ring oscillators are used almost exclusively with the

silicon chip technology today.

93. Many of the Accused Products in this case have microprocessors made by Qualcomm,

Texas Instruments or LSI Logic. Accordingly, I provide some general explanations about the

system clocks in these microprocessors below that apply to multiple Accused Products. Specific

explanations about the system clocks in the microprocessors found in each of the Accused

Products can be found in the infringement analysis below in Sections 6 and 8, and in the claim

charts of Appendices H and K.


Exhibit 4

Case5:08-cv-00877-PSG Document545-1 Filed08/27/13 Page1 of 58

U.S. District Court

California Northern District (San Jose)

Civil Case Nos. 5:08-cv-00877 and 5:08-cv-00882

OPENING REPORT OF DR. VOJIN G. OKLOBDZIJA

(INFRINGEMENT)

APPENDIX H


2. ACER DESKTOP ASE380-UD48 PIC00011356 - PIC00011401


4. ACER DESKTOP ASPIRE M3100 (ANGORA) PIC A-9


EXHIBIT ACER-A-9: CLAIM CHART FOR INFRINGEMENT OF U.S. PATENT NO. 5,908,336 BY ACER DESKTOP ASPIRE M3100

Claim 1

1. A microprocessor system, comprising

The Acer Desktop Aspire M3100 product contains an ST Microelectronics ST 100404226 microprocessor.



a processing frequency capability of said central processing unit and a speed of said ring oscillator variable speed system clock varying together due to said manufacturing variations and due to at least operating voltage and temperature of said single integrated circuit;

The central processing unit and the ring oscillator variable speed system clock are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency capability of the central processing unit and speed of the ring oscillator variable speed system clock will vary together due to manufacturing variations (see above) and due to operating voltage and temperature of the integrated circuit.

Design of High-Performance Microprocessor Circuits: Chapter 6, Chandra p.98

an on-chip input/output interface connected to exchange coupling control signals, addresses and data with said central processing unit; and

The ST 100404226 microprocessor includes input/output interfaces (e.g. a SATA device) connected to exchange coupling control signals, address and data with the central processing unit.



a second clock independent of said ring oscillator variable speed system clock connected to said input/output interface,

The SATA communication system utilizes embedded timing signals, indicating the presence of a second clock, independent of the CPU clock, either in the Accused Product or in a peripheral device connected to the Accused Product.

wherein a clock signal of said second clock originates from a source other than said ring oscillator variable speed system clock.

The clock signal of the second clock either in the Accused Product or in a peripheral device connected to the Accused Product originates from a source other than the ring oscillator variable speed system clock.

Claim 6

6. A microprocessor system comprising:




unit at a clock rate and being constructed of a second plurality of electronic devices,

The oscillator is constructed of a second plurality of electronic devices.

thus varying the processing frequency of said first plurality of electronic devices and the clock rate of said second plurality of electronic devices in the same way as a

function of parameter variation in one or more fabrication or operational parameters associated with said integrated circuit substrate,

The central processing unit and the oscillator are constructed on a single integrated circuit comprising semiconductor-based transistors, or electronic devices. Because the central processing unit and the oscillator reside on the same integrated circuit, they were constructed using the same process technology and vary in the same way as a function of parameter variation in one or more fabrication or operational parameters.

Design of High-Performance Microprocessor Circuits: Chapter 6, Chandra p. 98




thereby enabling said processing

frequency to track said clock rate in response to said parameter variation;

The central processing unit and the oscillator are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency of the central processing unit is enabled to track the clock rate in response to said parameter variation.



Claim 10

10. In a microprocessor system including a central processing unit, a method for clocking said central processing unit comprising the steps of:





said processing frequency and said clock rate varying in the same way relative to said variation in said one or more fabrication or operational parameters associated with said integrated circuit substrate;

The central processing unit and the variable speed clock are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency of the central processing unit and the variable speed clock will vary in the same way due to fabrication or operational parameters.




connecting an on chip input/output interface between said central processing unit and an off chip external memory bus, and exchanging coupling control signals,

addresses and data between said input/output interface and said central processing unit; and

The ST 100404226 microprocessor includes input/output interfaces (e.g. a SATA device) connected to exchange coupling control signals, address and data with the central processing unit utilizing an off-chip external memory bus.

clocking said input/output interface using an off chip external clock wherein said off chip external clock is operative at a

The SATA communication system utilizes embedded timing signals, indicating the presence of an off chip external clock, independent of the CPU clock, either in the Accused Product or in a peripheral device connected to the Accused Product. The off-



Claim 11







The central processing unit and the ring oscillator variable speed system clock are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency capability of the central processing unit and the speed of the ring oscillator variable speed system clock will vary together due to manufacturing variations (see above) and due to operating voltage and temperature of the integrated circuit.





The ST 100404226 microprocessor includes input/output interfaces (e.g. a SATA device) connected to exchange coupling control signals, address and data with the central processing unit.


The SATA communication system utilizes embedded timing signals, indicating the presence of a second clock, independent of the CPU clock, either in the Accused Product or in a peripheral device connected to the Accused Product.



Claim 13





an entire oscillator disposed upon said integrated circuit substrate and connected to said central processing unit, said oscillator clocking said central processing unit at a clock rate and being constructed of a second plurality of electronic devices,

The claimed oscillator is disposed upon the integrated circuit substrate, connected to the CPU, and is clocking said CPU. The oscillator is constructed of a second plurality of electronic devices.

The presence of an internal PLL is indicated by the connection of Plus and Minus pins to an external resonator frequency reference. The presence of a PLL indicates the presence of a voltage or current controlled oscillator. The claimed oscillator is disposed upon the integrated circuit substrate, connected to the CPU, and is clocking said CPU.

thus varying the processing frequency of said first plurality of electronic devices and the clock rate of said second plurality of electronic devices in the same way as a

function of parameter variation in one or more fabrication or operational parameters associated with said integrated circuit substrate,

The central processing unit and the oscillator are constructed on a single integrated circuit comprising semiconductor-based transistors, or electronic devices. Because the central processing unit and the oscillator reside on the same integrated circuit, they were constructed using the same process technology and vary in the same way as a function of parameter variation in one or more fabrication or operational parameters.



Design of High-Performance Microprocessor Circuits: Chapter 6, Chandra p. 98




thereby enabling said processing

frequency to track said clock rate in response to said parameter variation;

The central processing unit and the oscillator are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency of the central processing unit is enabled to track the clock rate in response to said parameter variation.


an on-chip input/output interface, connected between said central processing unit and an off-chip external memory bus, for facilitating exchanging coupling control signals, addresses and data with said central processing unit; and

The ST 100404226 microprocessor includes input/output interfaces (e.g. a SATA device) connected to exchange coupling control signals, address and data with the central processing unit utilizing an off-chip external memory bus.



Claim 16



The claimed central processing unit is indicated in the STMicroelectronics ST10 Microcontroller Core Webpage, at 1 and ST Microelectronics - Hard Disk Drive ICs at




The central processing unit and the variable speed clock are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency of the central processing unit and the variable speed clock will vary in the same way due to fabrication or operational parameters.


connecting an on chip input/output interface between said central processing unit and an off chip external memory bus,

The ST 100404226 microprocessor includes input/output interfaces (e.g. a SATA device) connected to exchange coupling control signals, address and data with the


11. ACER NOTEBOOK ASPIRE ONE (AOA150-1570) (MACLES)

ACER-A-1


EXHIBIT ACER-A-1 – CLAIM CHART FOR INFRINGEMENT OF U.S. PATENT NO. 5,908,336 by Acer Notebook Aspire One (AOA150-1750) (The “Accused Product”)

Page 1 of 21 HIGHLY CONFIDENTIAL - ATTORNEYS’ EYES ONLY

Claim 1 Claim Element


PIC00012464

The Acer Notebook Aspire One (AOA150-1750) has a Seagate Momentus 5400.5 Hard Disk Drive.

1.a




PIC00012465

The Seagate Momentus Hard Drive contains the LSI Logic B5503A microprocessor.

a single integrated circuit including a central processing unit and an entire ring oscillator variable speed system clock in said single integrated circuit and connected to said central processing unit for clocking said central processing unit,

The LSI Logic B5503A contains an ARM 966E CPU. Casasanta Dep. 23:1-14 (February 20, 2013); LSI - TPLIITC- 00000053.

1.b




LSI - TPLIITC- 00000053

The clock source of the ARM CPU is a ring oscillator within a PLL existing entirely on the IC. The ring oscillator has a multiple odd number of inverters arranged in a loop.

2 A. The source of the clock to the ARM 3 processor in B5503A comes from a PLL. 4 Q. (BY MR. PHAM) Is that PLL located on the 5 chip? 6 A. Yes. 7 Q. Is the PLL entirely on the chip? 8 A. Yes. 9 MR. WALKER: Object to -- object to the

10 extent it calls for a legal conclusion. 11 Q. (BY MR. PHAM) Is there a ring oscillator 12 in the PLL? 13 MR. WALKER: Objection to the extent it 14 calls for a legal conclusion. 15 A. There is a ring oscillator inside the 16 PLL.




17 Q. (BY MR. PHAM) Does the ring oscillator 18 have a multiple odd number of inverters? 19 MR. WALKER: Object to the extent it 20 calls for a legal conclusion. 21 A. Yes. It must have to oscillate. 22 Q. (BY MR. PHAM) How many inverters are 23 there? 24 A. I don't know. 25 Q. Are those inverters arranged in a loop?

Page 28 1 A. Yes.

Casasanta Dep. 27:2 – 28:1.

said central processing unit and said ring oscillator variable speed system clock each including a plurality of electronic devices correspondingly constructed of the same process technology with corresponding manufacturing variations,

This microprocessor is a single integrated circuit: The Central Processing Unit and the on-chip Ring Oscillator (each including a plurality of electronic devices such as transistors) are manufactured and located on the same semiconductor substrate (die) using the same semiconductor manufacturing process: 10 Q. (BY MR. PHAM) Earlier you said you 11 understood the acronym PVT. 12 A. Yes. 13 Q. What does P stand for? 14 A. P stands for process. 15 Q. What does that mean? 16 A. That refers to the silicon technology in 17 which the design or IP is targeted for or developed or 18 designed in. 19 Q. In each of these four chips, is the PLL 20 that controls the microprocessor or microcontroller 21 made of the same silicon technology or, in other words 22 process, as the microprocessor and microcontroller? 23 A. In a given product, the PLL and the 24 microprocessor/microcontroller is made from the same 25 process technology, yes. Process technology across

Casasanta Dep. 133:10-25.

1.c




Id. at 101

These variations (corresponding manufacturing variations) are mean shifted together resulting in certain individual dies capable of operating faster than other dies made using the same manufacturing process.

Because the central processing unit and the ring oscillator variable speed system clock reside on the same integrated circuit, they were constructed using the same process technology and will have corresponding manufacturing variations. One of ordinary skill in the art would understand this with respect to the Accused Products based on generally accepted principles relating to semiconductor ICs. See Design of High-Performance Microprocessor Circuits pp. 98, 101 (Anatha Chandrakasan et al. eds., IEEE Press, 2001) [Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif)] (TPL853_02927444 – TPL853_02927464).


The central processing unit and the ring oscillator variable speed system clock are constructed on the same integrated circuit using the same process technology. Accordingly, the processing frequency capability of the central processing unit and the speed of the ring oscillator variable speed system clock will vary together due to manufacturing variations (see above) and due to operating voltage and temperature of the integrated circuit. One of ordinary skill in the art would understand this with respect to the Accused Products based on generally accepted principles relating to semiconductor ICs. See Design of High-Performance Microprocessor Circuits p. 98 (Anatha Chandrakasan et al. eds., IEEE Press, 2001) [Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif)] (TPL853_02927444 – TPL853_02927464).

1.d




3 Q. (BY MR. PHAM) Does PVT affect jitter? 4 A. Yes. 5 Q. PVT affects jitters for all the PLLs and 6 for chips? 7 A. Yes. 8 Q. And you understand PVT stands for process 9 voltage temperature?

10 A. Yes. Casasanta Dep. 128:3-10. 15 BY MR. PHAM: 16 Q. You just said that by design, the PLL 17 frequencies was designed not to change. But in 18 practice, it's never perfect, correct? 19 A. I testified that the clock source is 20 never ideal. It will have a source of offset 21 characterized by jitter, yes. 22 Q. And such jitter is affected by PVT? 23 A. It is.

Casasanta Dep. 139:15-23.




Claim 6 Claim

Element 6. A microprocessor system comprising:

See Claim Element 1.a.

6.a

a central processing unit disposed upon an integrated circuit substrate, said central processing unit operating at a processing frequency and being constructed of a first plurality of electronic devices;

See Claim Element 1.b. 6.b.1


See Claim Element 1.b. 6.b.2

thus varying the processing frequency of said first plurality of electronic devices and the clock rate of said second plurality of electronic devices in the same way as a function of parameter variation in one or more fabrication or operational parameters associated with said

See Claim Element 1.c. 6.c




integrated circuit substrate, thereby enabling said processing frequency to track said clock rate in response to said parameter variation;

See Claim Element 1.d. 6.d


The host interface (Serdes core), which is an on-chip input/output interface, is connected to exchange coupling control signals, addresses and data with the ARM CPU. The host interface is also connected to the PC host via the SATA off-chip external memory bus.

PIC00012470

4 Q. What does a host interface do? 5 A. That governs communication between the 6 disk and the host. 7 Q. And the host being the PC? 8 A. Correct.

6.e




Claim 7

7. A microprocessor system of claim 6


wherein said one or more operational parameters include operating temperature of said substrate or operating voltage of said substrate.

See Claim Element 1.d.

Claim 9 9. A microprocessor system of claim 6


wherein said oscillator comprises a ring oscillator. See Claim Element 1.b.




Claim 10



providing said central processing unit upon an integrated circuit substrate, said central processing unit being constructed of a first plurality of transistors and being operative at a processing frequency;

See Claim Element 1.b.

providing an entire variable speed clock disposed upon said integrated circuit substrate, said variable speed clock being constructed of a second plurality of transistors;


clocking said central processing unit at a clock rate using said variable speed clock with said central processing unit being clocked by said variable speed clock at a variable frequency dependent upon variation in one or more fabrication or operational parameters associated with said integrated circuit substrate,

See Claim Element 1.c.



connecting an on chip input/output interface between said central processing unit and an off chip external memory bus, and exchanging coupling control signals, addresses and data between said input/output interface and said central processing unit; and

See Claim Element 6.e.

clocking said input/output interface using an off chip external clock wherein said off chip external clock is operative at a frequency independent of a clock frequency of said variable speed clock and

See Claim Element 6.f.

wherein a clock signal from said off chip external clock originates from a source other than said variable speed clock.

See Claim Element 1.g.




Claim 11



a single integrated circuit including a central processing unit and an entire ring oscillator variable speed system clock in said single integrated circuit and connected to said central processing unit for clocking said central processing unit,


said central processing unit and said ring oscillator variable speed system clock each including a plurality of electronic devices correspondingly constructed of the same process technology with corresponding manufacturing variations,

See Claim Element 1.c.




See Claim Element 1.e.


See Claim Element 1.f.

wherein said central processing unit operates asynchronously to said input/output interface. See Claim Element 1.g.

Claim 13





See Claim Element 1.a

a central processing unit disposed upon an integrated circuit substrate, said central processing unit operating at a processing frequency and being constructed of a first plurality of electronic devices;

See Claim Element 1.b



thus varying the processing frequency of said first plurality of electronic devices and the clock rate of said second plurality of electronic devices in the same way as a function of parameter variation in one or more fabrication or operational parameters associated with said integrated circuit substrate,

See Claim Element 1.c

thereby enabling said processing frequency to track said clock rate in response to said parameter variation;

See Claim Element 1.d


See Claim Element 6.e

an off-chip external clock, independent of said oscillator, connected to said input/output interface wherein said off-chip external clock is operative at a frequency independent of a clock frequency of said oscillator and further

See Claim Element 6.f

wherein said central processing unit operates asynchronously to said input/output interface.

See Claim Element 1.g




Claim 14



wherein said one or more operational parameters include operating temperature of said substrate or operating voltage of said substrate.


Claim 15



wherein said oscillator comprises a ring oscillator.





Claim 16


See Claim Element 1.a

providing said central processing unit upon an integrated circuit substrate, said central processing unit being constructed of a first plurality of transistors and being operative at a processing frequency;


providing an entire variable speed clock disposed upon said integrated circuit substrate, said variable speed clock being constructed of a second plurality of transistors;


clocking said central processing unit at a clock rate using said variable speed clock with said central processing unit being clocked by said variable speed clock at a variable frequency dependent upon variation in one or more fabrication or operational parameters associated with said integrated circuit substrate,

See Claim Element 1.c


See Claim Element 1.d

connecting an on chip input/output interface between said central processing unit and an off chip external memory bus, and exchanging coupling control signals, addresses and data between said input/output interface and said central processing unit; and

See Claim Element 6.e

clocking said input/output interface using an off chip external clock wherein said off chip external clock is operative at a frequency independent of a clock frequency of said variable speed clock

See Claim Element 6.f

wherein said central processing unit operates asynchronously to said input/output interface.

See Claim Element 1.g


Exhibit 5


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198

UNITED STATES DISTRICT COURT

NORTHERN DISTRICT OF CALIFORNIA

SAN JOSE DIVISION

ACER, INC., ACER AMERICACORPORATION, and GATEWAY, INC.,

Plaintiffs,

-vs- No. 5:08-cv-00877 PSG

TECHNOLOGY PROPERTIES LTD.,PATRIOT SCIENTIFIC CORPORATION& ALLIACENSE LIMITED,

Defendants./

HTC CORPORATION and HTCAMERICA, INC.,

Plaintiffs,

-vs- No. 5:08-cv-0882 PSG

TECHNOLOGY PROPERTIES LTD.,PATRIOT SCIENTIFIC CORPORATION& ALLIACENSE LIMITED,

Defendants./

VIDEOTAPED DEPOSITION OF

VOJIN OKLOBDZIJA

July 15, 2013

Volume II, Pages 198 -

HIGHLY CONFIDENTIAL - PURSUANT TO PROTECTIVE ORDER

Reported by: WENDY E. ARLEN, CSR #4355, RMR, CRR

Job No: 2001-452289


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199

INDEX OF EXAMINATIONS

EXAMINATION BY: Page

MR. WALKER 203

MR. CHEN 368

--oOo--

INDEX OF EXHIBITS

EXHIBIT NO. DESCRIPTION PAGE

Exhibit 11 Serial ATA, A Comparison with

Ultra ATA Technology

204

Exhibit 12 1/7/03 Serial ATA: High Speed

Serialized AT Attachment, Revision

1.0a

205

Exhibit 13 Acer Server Altos G510 Series

(Leopard)

262

Exhibit 14 A 7-MHz Process, Temperature and

Supply Compensated Clock

Oscillator in 0.2 µm CMOS

269

Exhibit 15 Feb. 2006, Process and Temperature

Compensation in a 7-MHz CMOS Clock

Oscillator, by Sundaresan, et al.

276


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200

INDEX OF EXHIBITS

Exhibit 16 7/1/05 Seagate Vendor Requirements

Specification

283

Exhibit 17 11.Acer Notebook Aspire One

(AOA150-1570(Macles), ACER-A-1

287

Exhibit 18 2/20/13 Deposition of Joseph A.

Casasanta

291

Exhibit 19 Opening Report of Dr. Vojin G.

Oklobdzija (Infringement) Appendix

J

307

Exhibit 20 ARM System Developer's Guide 313

Exhibit 21 2/12/13 Deposition of Jeffrey Kyle

Whitt

323

Exhibit 22 1984 Motorola Microcomputers 353

Exhibit 23 7/2/13 Rebuttal Report of Dr.

Vojin G. Oklobdzija (Validity and

Secondary Considerations)

361

Exhibit 24 Excerpt of TMS34010 User's Guide 365

Exhibit 25 US Patent 4,689,581 401

--oOo--


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201

Deposition of VOJIN OKLOBDZIJA, taken by the

plaintiffs, at AGILITY IP LAW, LLP, 149 Commonwealth

Drive, Menlo Park, California, commencing at 9:06

a.m., Monday, July 15, 2013 before me, WENDY E.

ARLEN, CSR, RMR, CRR.

A P P E A R A N C E S

FOR THE PLAINTIFF HTC CORPORATION AND HTC AMERICA,INC..

COOLEY LLPAttorneys at LawKYLE D. CHEN, Ph.D., Esq.JASON C. FAN, Ph.D., Esq.3175 Hanover StreetPalo Alto, California [email protected]

FOR THE PLAINTIFFS ACER, INC., ACER AMERICACORPORATION, GATEWAY, INC.:

K&L GATES LLPAttorneys at LawTIMOTHY P. WALKER, Esq.Four Embarcadero Center, Suite 1200San Francisco, California [email protected]

THE DEFENDANT:

AGILITY IP LAW, LLPJAMES C. OTTESON, Esq.149 Commonwealth DriveMenlo Park, California [email protected]


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A. Yes.

Q. Do all clocks have jitter at a constant

voltage?

A. Yes.

Q. Do all clocks have jitter at a constant

temperature?

A. Yes.

Q. In performing your infringement analysis, did

you rely on any specific description or specification

of the jitter of any of the LSI parts?

A. I actually haven't considered the clock

jitter itself. What I did rely on in my analysis

is -- is the dead band in the PLL, meaning the

ability of the clock to drift, basically to be free

and out of -- out of the lock.

The jitter is -- this is, let's say, this is

my clock, it is jittery, but it can move over there,

it can travel in that band. So I did not consider

jitter as variability.

MR. WALKER: Let's take a break.

VIDEOGRAPHER: Going off the record, the time

is 10:17.

(Deposition recess taken.)

VIDEOGRAPHER: We are back on the record.

The time is 10:37.


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Q. Is Mr. Zuchowski discussing any of the

accused chips in any of the Acer accused products?

A. No, Mr. Zuchowski is speaking about generally

known facts and something that applies to -- to all

the manufacturing, semiconductor manufacturing.

Q. Let's go to the next element:

"a processing frequency capability of

said central processing unit and a speed of

said ring oscillator variable speed system

clock varying together due to said

manufacturing variations and due to at least

operating voltage and temperature of said

single integrated circuit."

Do you see that?

A. Yes, I see it.

Q. And on the right there is a -- looks like

some quotes and a figure from an article by somebody

named Sundaresan. That's S-u-n-d-a-r-e-s-a-n.

A. That's correct.

Q. Is Mr. Sundaresan's article discussing the

BCM 5702?

A. No.

Q. Is Mr. Sundaresan's article discussing any of

the accused chips on any of the accused Acer

products?


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A. No.

Q. Do you recall what Mr. Sundaresan is

discussing?

A. He is -- he has a general technical article

and he is discussing how the clock speed varies with

supply voltage, temperature, and process condition.

And I think this one figure shows the -- the

variations. This is from his article.

But he's discussing again, just like

Mr. Zuchowski, a generally known fact that if you are

building an oscillator, especially a ring oscillator

or ring oscillator base clock generator, it will vary

due to supply voltage, temperature, and process

conditions. So that's another kind of statement of

fact in a very general way.

Q. Let's go to the next page, and I think this

is a carryover for the same element; is that correct?

A. Yes.

Q. And you have here a quote from an author

named Fetzer, F-e-t-z-e-r, correct?

A. Right.

Q. And is Mr. Fetzer's article discussing the

BCM 5702?

A. No, Mr. Fetzer, as far as I know, is an Intel

guy.


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Q. Is Mr. Fetzer discussing any of the accused

chips on any of the accused Acer products?

A. I don't think Intel will allow him.

MR. WALKER: Let's mark as Exhibit 14 a

document entitled A 7-MHz Process, Temperature and

Supply Compensated Clock Oscillator in 0.2 micrometer

CMOS.

(Deposition Exhibit 14 marked for

identification.)

Q. MR. WALKER: Do you recognize Exhibit 14?

A. Yes, I do. I have that paper.

Q. And is this the Sundaresan paper that you're

referring to in your chart?

A. Yes, that's a Sundaresan paper.

Q. And this Sundaresan paper gets cited over and

over again in your charts; is that correct?

A. If you say over and over, I guess so, right.

Q. I don't mean to be -- it gets cited many

times; is that correct?

A. It gets cited many times, that's correct.

Q. Take a look at the abstract.

A. All right.

Q. The first sentence says: "This paper reports

on the design and implementation of a process,

temperature and supply compensated 7 [megahertz]


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room temperature --

Do you see that?

A. Yeah.

Q. -- and a worst case combined variation of

plus minus 2.6 percent with process, temperature and

supply.

Do you see that?

A. Yeah.

Q. The variation of frequency with power supply

was plus minus 0.31 percent for a supply voltage

range of 2.4 to 2.75 volts.

Do you see that?

A. I see that.

Q. So do you understand him to be describing

there characteristics of the clock he's built?

A. Yes, he is describing characteristic of

temperature and supplied compensated clock oscillator

that he built. That's what his intent was to do.

Q. Do you think he's made a variable speed clock

within the meaning of the claims?

A. Did he make a variable speed clock?

Q. Yes.

A. Well, you know, his -- his intent in this

article is to do the opposite. His intent is to --

to make the one that he is going to compensate. So


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as the normal three stage differential ring

oscillator which he is quoting here would raise the

frequency with voltage, he wants to compensate for

that. So he wants to make it less sensitive to -- to

the operating condition variations.

Q. Is this a variable speed clock that he's made

within the meaning of the claims?

MR. OTTESON: Objection, vague and compound.

THE WITNESS: Okay. Let's qualify that

question. If -- he started with the variable speed,

but then he made it into something opposite.

Q. MR. WALKER: Let's go to the introduction.

A. All right.

Q. The first sentence says: "High precision

clock generation is an important requirement for a

majority of digital circuits."

Do you see that?

A. Yes.

Q. Do you agree with that?

A. Yes.

Q. The next sentence says: "A micro-controller

typically depends on a crystal oscillator to generate

a start-up clock."

Do you see that?

A. I see that.


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this is different from the PLL that controls the

microprocessor or microcontroller, he said yes.

But I don't -- I don't -- I don't believe

there is a band gap discussed in this appendix.

Q. Or dead band.

A. Yeah, dead band discussed in this appendix.

Q. Looking at pages 6 and 7 of 21, Exhibit 17,

you start with a citation to a paper by --

A. Chandrakasan.

Q. Chandrakasan. Thank you. And my question is

whether his paper addresses the B5503A.

A. No, he doesn't talk about B -- about Broadcom

chip in particular.

Q. Well, this is a LSI chip. This is the LSI

B5503.

A. Oh, yeah. Yeah, B55 --

Q. 03A.

A. No.

Q. It does not discuss --

A. No.

Q. Chandrakasan does not discuss the B5503A,

correct?

A. No, he doesn't. As a matter of fact, just

to, you know, correct for the record, it's the edited

book and editor is Chandrakasan, but the particular


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article on process variation is by Duane Boning and

Sani Nassif, and they don't -- they talk generally

about process variations and I do not mention any

chip in particular.

Q. Okay. And they also do not discuss

phase-locked loops, correct?

A. It is an article about variations. So they

don't -- they don't talk about phase-locked loops.

Q. There is a quotation of Casasanta deposition

testimony here concerning jitter. Do you see that?

A. Which page?

Q. Page 7 of 21.

A. I'm there. Let me just read it quickly. I

read it.

Q. Okay. Do you see in this chart any other

evidence of variability of the output of a PLL on the

B5503A?

A. Well, other than a general knowledge of how

they behave, I don't see any -- anything in

particular related to B550 --

Q. 03A.

A. 03?

Q. 03A.

A. Right, 03A. That is discussed. And the

discussion here is about jitter, and as I said,


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299

Do you see that?

A. Yes. So let's say --

Q. I haven't asked a question yet.

A. -- 200 megahertz clock which is -- which is

five nanoseconds. So a hundred picoseconds to five

nanoseconds, that's reasonable number.

Q. All right. Given the fact that the LSI

B5503A will work to its specification if there is

zero jitter as the temperature changes, do you think

Mr. Casasanta's calling the PLL outputs of the LSI

B5503A chip is fair?

MR. OTTESON: Objection, vague.

THE WITNESS: Are you asking me about the

position or you asking a separate question?

Q. MR. WALKER: I'm asking if Mr. Casasanta's

testimony here that LSI considers the output to be

fixed, the output of PLL to be fixed, whether that's

a fair characterization.

A. For the practical purposes it serves them,

yes.

Q. Turn to page 72 of the transcript, starting

at line 4. Mr. Casasanta is asked the question:

"Are there any components between the PLL and the ARM

processor that the output of the PLL has to go

through?"


Exhibit 8


Vojin Oklobdzija December 10, 2010San Francisco, CA

1-800-FOR-DEPOAlderson Reporting Company

1

1 UNITED STATES DISTRICT COURT

2 FOR THE NORTHERN DISTRICT OF CALIFORNIA

3 --oOo--

4 ACER, INC., ACER AMERICA

5 CORPORATION AND GATEWAY, INC.,

6 PLAINTIFFS,

7 vs. No. 5:08-CV-00877

8 TECHNOLOGY PROPERTIES LIMITED,

9 PATRIOT SCIENTIFIC CORPORATION

10 AND ALLIACENSE, ET AL.,

11 DEFENDANTS.

12 _____________________________

13

14

15

16 VIDEOTAPED DEPOSITION OF VOJIN OKLOBDZIJA

17 Friday, December 10, 2010

18

19

20

21

22

23

24 Reported By:

25 KATHLEEN WILKINS, CSR #10068, RPR, CRR, CCRR, CLR




2

1 INDEX

2 INDEX OF EXAMINATIONS

3 PAGE

4 EXAMINATION BY MR. WALKER .......................8

5 AFTERNOON SESSION ..............................95

6 INDEX OF EXHIBITS

7 Exhibit Description

8 Page

9 Exhibit 40 Document entitled, "Subpoena to ...9

10 Testify at a Deposition In A

11 Civil Action"

12 Exhibit 41 Document entitled, "Subpoena to ...9

13 Produce Documents, Information,

14 or Objects or to Permit

15 Inspection of Premises In A

16 Civil Action"

17 Exhibit 42 Curriculum Vitae .................39

18 Exhibit 43 Invoice Bates stamped ............86

19 TPL-VO005758


21 TPL-VO005743, TPL-VO005730 and

22 TPL-VO005740


24 TPL-VO005746 and TPL-VO005738

25




3

1 INDEX OF EXHIBITS (CONTINUED)


3 TPL-VO0005747, TPL-VO0005758

4 and TPL-VO0005737

5 Exhibit 47 Invoices Bates stamped ...........95

6 TPL-VO005751 and TPL-VO0005742

7 Exhibit 48 Document entitled, "Joint Claim ..99

8 Construction and Prehearing

9 Statement"

10 Exhibit 49 United States Patent No. ........103

11 5,809,336


13 5,440,749


15 5,530,890

16

17 ---o0o---

18

19

20

21

22

23

24

25




4

1 DEPOSITION OF VOJIN OKLOBDZIJA

2 BE IT REMEMBERED that on Friday,

3 December 10, 2010, commencing at the hour of 9:10

4 a.m. thereof, at K&L GATES, Four Embarcadero

5 Center, Suite 1200, San Francisco, California,

6 before me, Kathleen A. Wilkins, RPR, CRR, CRP, a

7 Certified Shorthand Reporter, in and for the State

8 of California, personally appeared VOJIN

9 OKLOBDZIJA, a witness in the above-entitled court

10 and cause, who, being by me first duly sworn, was

11 thereupon examined as a witness in said action.

12

13

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20

21

22

23

24

25




5

1 APPEARANCES OF COUNSEL

2 For the Plaintiffs:

3 K&L GATES

4 BY: TIMOTHY P. WALKER, Attorney at Law

5 Four Embarcadero Center, Suite 1200

6 San Francisco, California 94111

7 Telephone: (415) 882-8200

8 E-mail: [email protected]

9

10 For the Defendants TECHNOLOGY PROPERTIES LIMITED

11 AND ALLIACENSE LIMITED:

12 FARELLA, BRAUN & MARTEL, LLP

13 BY: EUGENE Y. MAR, Attorney at Law

14 JOHN L. COOPER, Attorney at Law

15 235 Montgomery Street

16 San Francisco, California 94104

17 Telephone: (415) 954-4927


19 [email protected]

20

21

22

23

24

25




6

1 APPEARANCES OF COUNSEL (Continued)

2 For the Defendants HTC CORPORATION, HTC AMERICA,

3 INC.:

4 COOLEY, LLP

5 BY: MARK WEINSTEIN, Attorney at Law

6 KYLE CHEN, Ph.D., Attorney at Law

7 3175 Hanover Street

8 Palo Alto, California 94304-1130

9 Telephone: (650) 843-5007


11 [email protected]

12 For the Defendant BARCO N.V., a Belgian

13 corporation:

14

15 BAKER & MCKENZIE LLP

16 (Appearing telephonically)

17 Edward K. Runyan, Attorney at Law

18 130 East Randolph Drive, Suite 3900

19 Chicago, Illinois 60601

20 Telephone: (312) 861-8811


22

23 ALSO PRESENT:

24 James Kocal, Videographer

25 --oOo--




207

1 MR. MAR: Object. It's vague and

2 ambiguous and it's compound.

3 THE WITNESS: I would say that it's fair

4 to characterize something fixed if it serves the

5 purpose for which we consider it to be fixed.

6 So let's say if I have a fixed clock in

7 the I/O, and it's stable enough that it doesn't

8 show -- doesn't make any out-of-sync behavior on

9 the other end, it can control the transfer. We

10 call it fixed. We characterize it as fixed. So

11 in a way, it satisfy the function. Its stability

12 satisfies the function to be characterized as

13 fixed.

14 MR. WALKER: Q. Does the same logic

15 apply to the concept of variable? In other words,

16 it has to be variable enough that it accomplishes

17 some purpose, some -- some purpose of variation?

18 MR. MAR: Again, object to the question

19 as vague and ambiguous.

20 THE WITNESS: I don't know how to

21 answer. I would say, you know, something is

22 variable if we characterize it as variable.

23 MR. WALKER: Q. Well, you -- you

24 mentioned the cruise control in a car.

25 A. Right.
