FPGA/ CPLD LABEXPERIMENT 11AIM : To design and simulate Universal Shift Register using Verilog HDL.EDA TOOL USED : Xilinx ISE 8.1iMETHODOLOGY : A register is composed of a group of FFs to store a group of bits. A universal shift register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. In order for the universal shift register to operate in a specific mode, it must first select the mode. To accomplish mode selection the universal register uses a set of two selector switches, S[1] and S[0] as shown in table. Its parallel outputs are A[0], A[1], A[2], A[3] and parallel inputs are I[0], I[1], I[2], I[3]. The control of right and left shift is governed by rtin and lfin respectively. Universal shift registers, as all other types of registers, are used in computers as memory elements. In fact, all the operations in a digital system are performed on registers. Examples of such operations include multiplication, division, and data transfer.Operating modeS[1]S[0]

Hold00

Shift right01

Shift left10

Parallel load11

Fig. 11.1 Block diagram of Universal Shift register

VERILOG CODE : module muxd2(I0, I1, I2, I3, S0, S1, Y);input I0, I1, I2, I3, S0, S1; output Y;assign {Y}=S0?(S1?I3:I1):(S1?I2:I0);endmodulemodule dff(d,clk,res, q);input d,clk,res; output reg q;initial begin q