exploiting architecture for verification dave whipp
DESCRIPTION
A HW Development Flow Big Paper Spec Design Verification RTL Testbench Checkers Tests Scoreboard Assertions C Model Synthesis Directed Randoms BFMs, TLMs Clocks, Resets Assertions ISS Model Coverage Debug (BAD)TRANSCRIPT
Exploiting ArchitectureFor Verification
Dave Whipp
Architecture For Verification Simplify the Design
– Reduce corner cases– Decoupled State Machines– Focus Complexity on Performance
• Tradeoff Performance Vs Schedule
Provide Verification-Friendly Work Products– Models– Test benches– Tests
A HW Development FlowBig Paper Spec
Design
Verification
RTL
Testbench Checkers Tests
Scoreboard
Assertions
C Model
Synthesis
Directed
RandomsBFMs,
TLMs
Clocks, ResetsAssertions
ISS Model
CoverageDebug
(BAD)
A HW Development FlowBig Paper Spec
Design
Verification
RTL
Testbench Checkers Tests
Scoreboard
Assertions
C Model
Synthesis
Directed
RandomsBFMs,
TLMs
Clocks, ResetsAssertions
ISS Model
CoverageDebug
(BAD)
A HW Development Flow (Better)
RTL Scoreboards
Synthesis
Randoms
Clocks, Resets
Design
Verification
Testbench
Small Paper Spec
ISS Model ESL
C Model
Interfaces
Assertions
Directed Tests BFMs
TLMs
Validation
Assertions
Triage
Debug
Coverage
Coverage
What Type of Model?
A EB C D F G
D
GA
BE
CF
How do we model that these are equivalent?
ISS:
TLM:
Exploitation of Executable Models Product Development
– Enable SW development– Validate the Architecture
Verification Bootstrapping– Validate Tests– Functional Checkers– Validate Assertions– Architectural Coverage
Design Verification Testbenches
TransactionProducer
ScenarioGenerator
CoverageModel
DUT
TransactionConsumer
ScenarioChecker
BFM BFM
UTFmodel
Architectural Validation Testbenches
TransactionProducer
ScenarioGenerator
CoverageModel
UTFmodel
TransactionConsumer
ScenarioChecker
How To Reuse Architectural Tests
Architectural
Mic
ro A
rchi
tect
ural
Architectural Bringup Tests
Architectural
Mic
ro A
rchi
tect
ural
Micro-architectural Directed Tests
Architectural
Mic
ro A
rchi
tect
ural
Micro-architectural Directed Tests
Shallow Features
Dee
p In
tera
ctio
ns
Constrained Random Tests
Shallow Features
Dee
p In
tera
ctio
ns
Random Directed Tests
Shallow Features
Dee
p In
tera
ctio
ns
Testing using GraphsShape
Line
Triangle
Solid
Stipple
Short Fat
Long Skinny Filled
Outline
Aspect Body
Dashed
Micro-Architectural Tests
Address Cacheable
Page
Evict dirty
Evict about-to-be-needed
Reuse
New
No
Yes
Conclusion Architects must create Executable
Representations– Validated by Architects– Reused by Verifiers
Not Just Models– Testbenches and VIP– Self-Checking Tests (Directed Random)
Traditional Models serve Multiple Roles– Checkers– Assertions– Coverage